74VHCT374 [FAIRCHILD]
Octal D-Type Flip-Flop with 3-STATE Outputs; 八路D型IP- FL佛罗里达州运与三态输出
| 型号： | 74VHCT374 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Octal D-Type Flip-Flop with 3-STATE Outputs |
| 文件： | 总7页 (文件大小：95K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
July 1997
Revised April 1999
74VHCT374A
Octal D-Type Flip-Flop with 3-STATE Outputs
up. This circuit prevents device destruction due to mis-
matched supply and input voltages.
General Description
The VHCT374A is an advanced high speed CMOS octal
flip-flop with 3-STATE output fabricated with silicon gate
CMOS technology. It achieves the high speed operation
similar to equivalent Bipolar Schottky TTL while maintain-
ing the CMOS low power dissipation. This 8-bit D-type flip-
flop is controlled by a clock input (CP) and an output
enable input (OE). When the OE input is HIGH, the eight
outputs are in a high impedance state.
Note 1: Outputs in OFF-State.
Features
■ High speed: fMAX = 140 MHz (typ) at TA = 25°C
■ High noise immunity: VIH = 2.0V, VIL = 0.8V
■ Power down protection is provided on all inputs and out-
puts
Protection circuits ensure that 0V to 7V can be applied to
the input and output (Note 1) pins without regard to the
supply voltage. This device can be used to interface 3V to
5V systems and two supply systems such as battery back
■ Low power dissipation:
ICC = 4 µA (max) @ TA = 25°C
■ Pin and function compatible with 74HCT374
Ordering Code:
Order Number
74VHCT374AM
74VHCT374ASJ
74VHCT374AMTC
74VHCT374AN
Package Number
M20B
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
M20D
MTC20
N20A
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
D0–D7
CP
Description
Data Inputs
Clock Pulse Input 3-STATE
Output Enable Input 3-STATE
Outputs
OE
O0–O7
© 1999 Fairchild Semiconductor Corporation
DS500030.prf
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Functional Description
Truth Table
The VHCT374A consists of eight edge-triggered flip-flops
with individual D-type inputs and 3-STATE true outputs.
The buffered clock and buffered Output Enable are com-
mon to all flip-flops. The eight flip-flops will store the state
of their individual D inputs that meet the setup and hold
time requirements on the LOW-to-HIGH Clock (CP) transi-
tion. With the Output Enable (OE) LOW, the contents of the
eight flip-flops are available at the outputs. When the OE is
HIGH, the outputs go to the high impedance state. Opera-
tion of the OE input does not affect the state of the flip-
flops.
Inputs
Outputs
Dn
H
L
CP
OE
L
On
H
L
L
X
X
H
Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
= LOW-to-HIGH Transition
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings(Note 2)
Recommended Operating
Conditions (Note 6)
Supply Voltage (VCC
)
−0.5V to +7.0V
−0.5V to +7.0V
DC Input Voltage (VIN
)
Supply Voltage (VCC
)
4.5V to +5.5V
0V to +5.5V
DC Output Voltage (VOUT
)
Input Voltage (VIN
)
(Note 3)
−0.5V to VCC + 0.5V
−0.5V to +7.0V
−20 mA
Output Voltage (VOUT
)
(Note 4)
(Note 3)
0V to VCC
0V to 5.5V
Input Diode Current (IIK
)
(Note 4)
Output Diode Current (IOK
(Note 5)
)
Operating Temperature (TOPR
Input Rise and Fall Time (tr, tf)
CC = 5.0V ± 0.5V
)
−40°C to +85°C
±20 mA
±25 mA
DC Output Current (IOUT
)
V
0 ns/V 20 ns/V
Note 2: Absolute Maximum Ratings are values beyond which the device
may be damaged or have its useful life impaired. The databook specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari-
ables. Fairchild does not recommend operation outside databook specifica-
tions.
DC VCC/GND Current (ICC
)
±75 mA
Storage Temperature (TSTG
Lead Temperature (TL)
(Soldering, 10 seconds)
)
−65°C to +150°C
260°C
Note 3: HIGH or LOW state.
I
absolute maximum rating must be
OUT
observed.
Note 4: When outputs are in OFF-State or when V = OV.
CC
Note 5: V
< GND, V
> V (Outputs Active).
OUT CC
OUT
Note 6: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
T
= 25°C
T = −40°C to +85°C
A
V
(V)
A
CC
Symbol
Parameter
Units
Conditions
Min
2.0
2.0
Typ
Max
Min
Max
V
V
V
V
HIGH Level
4.5
5.5
4.5
5.5
2.0
2.0
IH
V
V
Input Voltage
LOW Level
0.8
0.8
0.8
0.8
IL
Input Voltage
HIGH Level
4.40
3.94
4.50
0.0
4.40
3.80
V
V
V
V
V
V
= V
I
OH
= −50 µA
= −8 mA
= +50 uA
= +8 mA
OH
OL
IN
IN
IH
4.5
4.5
5.5
Output Voltage
LOW Level
or V
I
IL OH
0.1
0.1
= V
I
OL
IH
Output Voltage
3-STATE Output
OFF-State Current
Input Leakage Current
Quiescent Supply Current
0.36
0.44
or V
I
IL OL
I
V
V
V
V
V
= V or V
IH IL
OZ
IN
±0.25
±2.5
µA
= V or GND
OUT
CC
I
0–5.5
5.5
±0.1
±1.0
µA
µA
= 5.5V or GND
IN
IN
IN
IN
I
4.0
40.0
= V or GND
CC
CC
I
Maximum I /Input
= 3.4V
CCT
CC
5.5
0.0
1.35
0.5
1.50
5.0
mA
Other Inputs = V or GND
CC
I
Output Leakage Current
(Power Down State)
V
= 5.5V
OUT
OFF
µA
Noise Characteristics
T
= 25°C
V
(V)
A
CC
Symbol
Parameter
Units
Conditions
Typ
Limits
V
Quiet Output Maximum Dynamic V
5.0
5.0
5.0
5.0
1.2
1.6
−1.6
2.0
V
C
C
C
C
= 50 pF
= 50 pF
= 50 pF
= 50 pF
OLP
OL
L
L
L
L
(Note 7)
V
Quiet Output Minimum Dynamic V
−1.2
V
V
V
OLV
OL
(Note 7)
V
Minimum HIGH Level Dynamic Input Voltage
IHD
(Note 7)
V
Maximum LOW Level Dynamic Input Voltage
0.8
ILD
(Note 7)
Note 7: Parameter guaranteed by design.
3
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AC Electrical Characteristics
T
= 25°C
T = −40°C to +85°C
A
V
(V)
A
CC
Symbol
Parameter
Units
ns
Conditions
Min
Typ
4.1
5.6
6.5
7.3
Max
9.4
Min
Max
10.5
11.5
11.5
12.5
t
t
t
t
t
t
t
t
f
Propagation Delay Time
1.0
1.0
1.0
1.0
C
C
C
C
C
= 15 pF
= 50 pF
= 15 pF
= 50 pF
= 50 pF
PLH
L
L
L
L
L
5.0 ± 0.5
10.4
10.2
11.2
PHL
3-STATE Output Enable Time
3-STATE Output Disable Time
Output to Output Skew
R
R
= 1 kΩ
= 1 kΩ
PZL
L
5.0 ± 0.5
5.0 ± 0.5
5.0 ± 0.5
5.0 ± 0.5
ns
PZH
PLZ
L
7.0
11.2
1.0
1.0
12.0
1.0
ns
PHZ
OSLH
OSHL
MAX
(Note 8)
Maximum Clock Frequency
90
85
140
130
80
75
C
C
= 15 pF
= 50 pF
L
MHz
L
C
Input
V
V
= Open
IN
CC
4
10
10
pF
pF
Capacitance
C
C
Output Capacitance
Power Dissipation Capacitance
9
= 5.0V
OUT
CC
25
pF (Note 9)
PD
Note 8: Parameter guaranteed by design. t
= |t
− t
|; t
= |t
− t
|
OSLH
PLH max
PLH min OSHL
PHL max
PHL min
Note 9: C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average
PD
operating current can be obtained by the equation: I (opr.) = C * V * f + I /8 (per F/F). The total C when n pcs. of the octal D Flip-Flop operates
CC
PD
CC
IN
CC
PD
can be calculated by the equation: C (total) = 20 + 12m.
PD
AC Operating Requirements
T
= 25°C
T = −40°C to +85°C
A
V
(V)
A
CC
Symbol
Parameter
Units
ns
Min
Typ
Max
Min
Max
t
t
t
t
(H)
(L)
Minimum Pulse
W
W
S
5.0 ± 0.5
6.5
8.5
2.5
Width (CP)
Minimum Set-up Time
Minimum Hold Time
5.0 ± 0.5
5.0 ± 0.5
2.5
2.5
ns
2.5
H
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4
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N20A
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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