CD40192BCN [FAIRCHILD]
Synchronous 4-Bit Up/Down Decade Counter . Synchronous 4-Bit Up/Down Binary Counter; 同步4位加/减十进制计数器。同步4位加/减二进制计数器
| 型号： | CD40192BCN |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Synchronous 4-Bit Up/Down Decade Counter . Synchronous 4-Bit Up/Down Binary Counter |
| 文件： | 总7页 (文件大小：77K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
October 1987
Revised January 1999
CD40192BC • CD40193BC
Synchronous 4-Bit Up/Down Decade Counter •
Synchronous 4-Bit Up/Down Binary Counter
All inputs are protected against damage due to static dis-
General Description
The CD40192BC and CD40193BC up/down counters are
charge by clamps to VDD and VSS
.
monolithic complementary MOS (CMOS) integrated cir-
Features
■ Wide supply voltage range: 3V to 15V
cuits. The CD40192BC is
a BCD counter, while the
CD40193BC is a binary counter.
Counting up and counting down is performed by two count
inputs, one being held HIGH while the other is clocked. The
outputs change on the positive-going transition of this
clock.
■ High noise immunity: 0.45 VDD (typ.)
■ Low power TTL compatibility: Fan out of 2 driving 74L
or 1 driving 74LS
■ Carry and borrow outputs for easy expansion to N-bit by
cascading
These counters feature preset inputs that are enabled
when load is a logical “0” and a clear which forces all out-
puts to “0” when it is at logical “1”. The counters also have
carry and borrow outputs so that they can be cascaded
using no external circuitry.
■ Asynchronous clear
■ Equivalent to: MM74C192 and MM74C193
Ordering Code:
Order Number Package Number
Package Description
CD40192BCN
CD40193BCN
CD40193BCM
N16E
N16E
M16A
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Cascading Packages
Pin Assignments for DIP and SOIC
Top View
© 1999 Fairchild Semiconductor Corporation
DS005988.prf
www.fairchildsemi.com
Block Diagrams
CD40192BC Synchronous 4-Bit Up/Down Decade Counter
CD40193BC Synchronous 4-Bit Up/Down Binary Counter
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2
Absolute Maximum Ratings(Note 1)
(Note 2)
Recommended Operating
Conditions (Note 2)
DC Supply Voltage (VDD
Input Voltage (VIN
)
−0.5 to +18 VDC
DC Supply Voltage (V DD
Input Voltage (VIN
)
3 to 15 VDC
)
−0.5 to VDD +0.5 VDC
)
0 to VDD VDC
Operating Temperature Range (TA)
CD40192BC, CD40193BC
Storage Temperature Range (TS)
−65°C to +150°C
−40°C to +85°C
Power Dissipation (PD)
Dual-In-Line
Note 1: “Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed. They are not meant to imply
that the devices should be operated at these limits. The “Recommended
Operating Conditions” and Electrical Characteristics tables provide condi-
tions for actual device operation.
700 mW
500 mW
Small Outline
Lead Temperature (TL)
(Soldering, 10 seconds)
Note 2: V = 0V unless otherwise specified.
260°C
SS
DC Electrical Characteristics (Note 3)
−40°C
+25°C
+85°C
Symbol
Parameter
Conditions
= 5V, V = V or V
SS
Units
Min
Max
Min
Typ
Max
20
Min
Max
I
Quiescent Device
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
20
40
150
300
600
0.05
0.05
0.05
µA
µA
µA
V
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
IN
DD
Current
= 10V, V = V or V
SS
40
IN
DD
= 15V, V = V or V
SS
80
80
IN
DD
V
V
V
LOW Level
= 5V
0.05
0.05
0.05
0.05
0.05
0.05
OL
OH
IL
Output Voltage
= 10V
= 15V
= 5V
V
V
HIGH Level
4.95
9.95
4.95
9.95
4.95
9.95
V
Output Voltage
= 10V
= 15V
V
14.95
14.95
14.95
V
LOW Level
= 5V, V = 0.5V or 4.5V
1.5
3.0
4.0
1.5
3.0
4.0
1.5
3.0
4.0
V
O
Input Voltage
= 10V, V = 1V or 9V
V
O
= 15V, V = 1.5V or 13.5V
V
O
V
HIGH Level
= 5V, V = 0.5V or 4.5V
3.5
7.0
3.5
7.0
3.5
7.0
V
IH
O
Input Voltage
= 10V, V = 1V or 9V
V
O
= 15V, V = 1.5V or 13.5V
11.0
0.52
1.3
11.0
0.44
1.1
11.0
0.36
0.9
V
O
I
I
I
LOW Level Output
Current (Note 4)
= 5V, V = 0.4V
0.88
2.25
8.8
mA
mA
mA
mA
mA
mA
µA
µA
OL
O
= 10V, V = 0.5V
O
= 15V, V = 1.5V
3.6
3.0
2.4
O
HIGH Level Output
Current (Note 4)
= 5V, V = 4.6V
−0.52
−1.3
−3.6
−0.44 −0.88
−1.1 −2.25
−0.36
−0.9
−2.4
OH
O
= 10V, V = 9.5V
O
= 15V, V = 13.5V
−3.0
−8.8
O
−5
Input Current
= 15V, V = 0V
−0.3
−10
−0.3
−1.0
IN
IN
−5
= 15V, V = 15V
0.3
10
0.3
1.0
IN
Note 3: AC Parameters are guaranteed by DC correlated testing.
Note 4: I and I are tested one output at a time.
OH
OL
3
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AC Electrical Characteristics (Note 3)
T
A = 25°C, CL = 50 pF, RL = 200 kΩ, input t = t = 20 ns, unless otherwise specified.
r f
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
or t
or t
or t
Propagation Delay Time
from Count Up or
V
V
V
V
V
= 5V
250
100
80
400
160
130
200
80
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
PHL
PLH
PLH
PLH
DD
DD
DD
DD
DD
= 10V
= 15V
= 5V
Count Down to Q
t
Propagation Delay Time
from Count Up to Carry
120
50
PHL
= 10V
= 15V
= 5V
V
40
65
DD
DD
DD
DD
DD
DD
DD
DD
DD
t
Propagation Delay Time
from Count Down
to Borrow
V
V
V
V
V
V
V
V
120
50
200
80
PHL
= 10V
= 15V
= 5V
40
65
t
Time Prior to Load
That Data Must
100
30
160
50
SU
= 10V
= 15V
= 5V
Be Present
25
40
t
Propagation Delay Time
from Clear to Q
130
60
220
100
80
PHL
= 10V
= 15V
= 5V
V
50
DD
DD
DD
t
or t
or t
Propagation Delay Time
from Load to Q
V
V
300
120
95
480
190
150
200
100
80
PLH
PHL
= 10V
= 15V
= 5V
V
DD
DD
t
Output Transition Time
V
V
V
100
50
TLH
THL
V
= 10V
= 15V
= 5V
DD
DD
40
f
Maximum Count Frequency
V
2.5
6
4
CL
DD
DD
= 10V
= 15V
= 5V
10
V
7.5
15
5
12.5
DD
DD
DD
DD
DD
DD
t
or t
Maximum Count Rise
or Fall Time
V
V
V
V
V
rCL
fCL
= 10V
= 15V
= 5V
1
t
, t
Minimum Count Pulse
Width
120
35
200
80
WH WL
= 10V
= 15V
= 5V
V
28
65
DD
DD
t
Minimum Clear
Pulse Width
V
300
120
95
480
190
150
160
65
WH
V
= 10V
= 15V
= 5V
DD
DD
DD
DD
V
V
V
t
Minimum Load
Pulse Width
100
40
WL
= 10V
= 15V
V
32
55
DD
C
Average Input Capacitance
Load and Data
Inputs (A,B,C,D)
Count Up, Count
Down and Clear
(Note 5)
5
7.5
IN
10
15
pF
C
Power Dissipation Capacity
100
pF
PD
Note 5: C
determines the no load AC power consumption of any CMOS device. For complete explanation, see Family Characteristics application note,
PD
AN-90.
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4
Timing Diagrams
CD40192BC
Sequence:
1. Clear outputs to zero.
2. Load (preset) to BCD seven.
3. Count up to eight, nine, carry, zero, one and two.
4. Count down to one, zero, borrow, nine, eight and seven.
CD40193BC
Sequence:
1. Clear outputs to zero.
2. Load (preset) to binary thirteen.
3. Count up to fourteen, fifteen, carry, zero, one and two.
4. Count down to one, zero, borrow, fifteen, fourteen and thirteen.
5
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Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
Package Number M16A
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N16E
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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