CD4051BCSJX_NL [FAIRCHILD]
Single-Ended Multiplexer, 1 Func, 8 Channel, CMOS, PDSO16,;
| 型号： | CD4051BCSJX_NL |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Single-Ended Multiplexer, 1 Func, 8 Channel, CMOS, PDSO16, 光电二极管 |
| 文件： | 总13页 (文件大小：140K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 1983
Revised April 2002
CD4051BC • CD4052BC • CD4053BC
Single 8-Channel Analog Multiplexer/Demultiplexer •
Dual 4-Channel Analog Multiplexer/Demultiplexer •
Triple 2-Channel Analog Multiplexer/Demultiplexer
General Description
Features
■ Wide range of digital and analog signal levels:
The CD4051BC, CD4052BC, and CD4053BC analog mul-
tiplexers/demultiplexers are digitally controlled analog
switches having low “ON” impedance and very low “OFF”
leakage currents. Control of analog signals up to 15Vp-p
digital 3 – 15V, analog to 15Vp-p
■ Low “ON” resistance: 80Ω (typ.) over entire 15Vp-p
signal-input range for VDD − VEE = 15V
can be achieved by digital signal amplitudes of 3−15V. For
example, if VDD = 5V, VSS = 0V and VEE = −5V, analog sig-
■ High “OFF” resistance:
channel leakage of ±10 pA (typ.) at VDD − VEE = 10V
nals from −5V to +5V can be controlled by digital inputs of
0−5V. The multiplexer circuits dissipate extremely low qui-
escent power over the full VDD−VSS and VDD−VEE supply
■ Logic level conversion for digital addressing signals of
3 – 15V (VDD − VSS = 3 – 15V) to switch analog signals
voltage ranges, independent of the logic state of the control
signals. When a logical “1” is present at the inhibit input ter-
minal all channels are “OFF”.
to 15 Vp-p (VDD − VEE = 15V)
■ Matched switch characteristics:
∆RON = 5Ω (typ.) for VDD − VEE = 15V
CD4051BC is a single 8-channel multiplexer having three
binary control inputs. A, B, and C, and an inhibit input. The
three binary signals select 1 of 8 channels to be turned
“ON” and connect the input to the output.
■ Very low quiescent power dissipation under all
digital-control input and supply conditions:
1 µ W (typ.) at VDD − VSS = VDD − VEE = 10V
■ Binary address decoding on chip
CD4052BC is a differential 4-channel multiplexer having
two binary control inputs, A and B, and an inhibit input. The
two binary input signals select 1 or 4 pairs of channels to
be turned on and connect the differential analog inputs to
the differential outputs.
CD4053BC is a triple 2-channel multiplexer having three
separate digital control inputs, A, B, and C, and an inhibit
input. Each control input selects one of a pair of channels
which are connected in a single-pole double-throw configu-
ration.
Ordering Code:
Order Number Package Number
Package Description
CD4051BCM
CD4051BCSJ
CD4051BCMTC
CD4051BCN
CD4052BCM
CD4052BCSJ
CD4052BCN
CD4053BCM
CD4053BCSJ
CD4053BCN
M16A
M16D
MTC16
N16E
M16A
M16D
N16E
M16A
M16D
N16E
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2002 Fairchild Semiconductor Corporation
DS005662
www.fairchildsemi.com
Connection Diagrams
Pin Assignments for DIP and SOIC
CD4051BC
CD4052BC
CD4053BC
Truth Table
INPUT STATES
“ON” CHANNELS
INHIBIT
C
0
0
0
0
1
1
1
1
*
B
0
0
1
1
0
0
1
1
*
A
0
1
0
1
0
1
0
1
*
CD4051B CD4052B CD4053B
0
0
0
0
0
0
0
0
1
0
0X, 0Y
1X, 1Y
2X, 2Y
3X, 3Y
cx, bx, ax
cx, bx, ay
cx, by, ax
cx, by, ay
cy, bx, ax
cy, bx, ay
cy, by, ax
cy, by, ay
NONE
1
2
3
4
5
6
7
NONE
NONE
*Don’t Care condition.
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2
Logic Diagrams
CD4051BC
CD4052BC
3
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Logic Diagrams (Continued)
CD4053BC
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4
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
DC Supply Voltage (VDD
)
−0.5 VDC to +18 VDC
Input Voltage (VIN
)
−0.5 VDC to VDD +0.5 VDC
DC Supply Voltage (VDD
)
+5 VDC to +15 VDC
Storage Temperature
Range (TS)
Input Voltage (VIN
)
0V to VDD VDC
−65°C to +150°C
Operating Temperature Range (TA)
CD4051BC/CD4052BC/CD4053BC
Power Dissipation (PD)
Dual-In-Line
−55°C to +125°C
700 mW
500 mW
Note 1: “Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed. Except for “Operating Tempera-
ture Range” they are not meant to imply that the devices should be oper-
ated at these limits. The Electrical Characteristics tables provide conditions
for actual device operation.
Small Outline
Lead Temperature (TL)
(soldering, 10 seconds)
260°C
DC Electrical Characteristics (Note 2)
−55°C
Min Max
+25°
125°C
Min Max
Symbol
Parameter
Conditions
Units
Min
Typ
Max
Control A, B, C and Inhibit
IIN
Input Current
V
V
V
V
V
V
V
DD = 15V,
V
EE = 0V
−0.1
−5
−0.1
−10
−1.0
IN = 0V
µA
µA
DD = 15V,
IN = 15V
DD = 5V
DD = 10V
DD = 15V
VEE = 0V
−5
0.1
10
0.1
1.0
IDD
Quiescent Device Current
5
5
150
300
600
10
20
10
20
Signal Inputs (VIS) and Outputs (VOS
)
RON
“ON” Resistance (Peak
for VEE ≤ VIS ≤ VDD
R
L = 10 kΩ
V
DD = 2.5V,
EE = −2.5V
)
(any channel
selected)
V
800
310
200
270
120
80
10
10
5
1050
400
1300
550
Ω
Ω
Ω
Ω
Ω
Ω
or VDD = 5V,
V
V
V
EE = 0V
DD = 5V,
EE = −5V
or VDD = 10V,
V
V
V
EE = 0V
DD = 7.5V,
EE = −7.5V
240
320
or VDD = 15V,
V
V
V
EE = 0V
∆RON
∆ “ON” Resistance
Between Any Two
Channels
R
L = 10 kΩ
DD = 2.5V,
EE = −2.5V
(any channel
selected)
or VDD = 5V,
VEE = 0V
VDD = 5V
VEE = −5V
or VDD = 10V,
V
V
V
EE = 0V
DD = 7.5V,
EE = −7.5V
or VDD = 15V,
VEE = 0V
“OFF” Channel Leakage
VDD=7.5V,
VEE=−7.5V
Current, any channel “OFF” O/I=±7.5V, I/O=0V
±50
±0.01
±0.08
±50
±500
nA
nA
“OFF” Channel Leakage
Current, all channels
“OFF” (Common
OUT/IN)
Inhibit = 7.5V CD4051
±200
±200
±2000
VDD = 7.5V,
VEE = −7.5V,
D4052
±200
±200
±0.04
±0.02
±200
±200
±2000
±2000
O/I = 0V
I/O = ±7.5V
CD4053
5
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DC Electrical Characteristics (Continued)
−55°C
+25°
125°C
Symbol
Parameter
Conditions
Units
Min
Max
Min
Typ
Max
Min
Max
Control Inputs A, B, C and Inhibit
VIL
LOW Level Input Voltage
VEE = VSS
RL = 1 kΩ to VSS
IIS<2 µA on all OFF Channels
V
V
V
V
V
V
V
IS = VDD thru 1 kΩ
DD = 5V
1.5
3.0
4.0
1.5
3.0
4.0
1.5
3.0
4.0
DD = 10V
DD = 15V
DD = 5
V
V
VIH
HIGH Level Input Voltage
3.5
7
3.5
7
3.5
7
DD = 10
DD = 15
11
11
11
Note 2: All voltages measured with respect to VSS unless otherwise specified.
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6
AC Electrical Characteristics (Note 3)
TA = 25°C, tr = tf = 20 ns, unless otherwise specified.
Symbol
tPZH,
tPZL
Parameter
Conditions
VDD
Min
Typ
Max
Units
Propagation Delay Time from
Inhibit to Signal Output
(channel turning on)
Propagation Delay Time from
Inhibit to Signal Output
(channel turning off)
Input Capacitance
Control input
V
EE = VSS = 0V
5V
10V
15V
5V
600
225
160
210
100
75
1200
450
320
420
200
150
R
L = 1 kΩ
ns
C
L = 50 pF
tPHZ,
tPLZ
VEE = VSS = 0V
R
L = 1 kΩ
10V
15V
ns
pF
C
L = 50 pF
CIN
5
7.5
15
Signal Input (IN/OUT)
Output Capacitance
(common OUT/IN)
CD4051
10
COUT
10V
10V
10V
30
15
8
CD4052
V
EE = VSS = 0V
pF
pF
CD4053
CIOS
CPD
Feedthrough Capacitance
Power Dissipation Capacitance
CD4051
0.2
110
140
70
CD4052
pF
%
CD4053
Signal Inputs (VIS) and Outputs (VOS
)
Sine Wave Response
(Distortion)
R
L = 10 kΩ
f
IS = 1 kHz
10V
0.04
V
V
R
IS = 5 Vp-p
EE = VSI = 0V
Frequency Response, Channel
“ON” (Sine Wave Input)
L = 1 kΩ, VEE = 0V, VIS = 5Vp-p
,
10V
10V
10V
40
10
3
MHz
MHz
MHz
20 log10 VOS/VIS = −3 dB
L = 1 kΩ, VEE = VSS = 0V, VIS = 5Vp-p
20 log10 VOS/VIS = −40 dB
RL = 1 kΩ, VEE = VSS = 0V, VIS(A) = 5Vp-p
Feedthrough, Channel “OFF”
R
,
Crosstalk Between Any Two
Channels (frequency at 40 dB) 20 log10 VOS(B)/VIS(A) = −40 dB (Note 4)
tPHL
tPLH
Propagation Delay Signal
Input to Signal Output
V
EE = VSS = 0V
5V
25
15
10
55
35
25
C
L = 50 pF
10V
15V
ns
Control Inputs, A, B, C and Inhibit
Control Input to Signal
Crosstalk
V
EE = VSS = 0V, RL = 10 kΩ at both ends
of channel.
10V
65
mV (peak)
ns
Input Square Wave Amplitude = 10V
tPHL,
tPLH
Propagation Delay Time from
Address to Signal Output
(channels “ON” or “OFF”)
VEE = VSS = 0V
5V
500
180
120
1000
360
C
L = 50 pF
10V
15V
240
Note 3: AC Parameters are guaranteed by DC correlated testing.
Note 4: A, B are two arbitrary channels with A turned “ON” and B “OFF”.
7
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Special Considerations
In certain applications the external load-resistor current
switch must not exceed 0.6V at TA ≤ 25°C, or 0.4V at
A > 25°C (calculated from RON values shown). No VDD
may include both VDD and signal-line components. To
T
avoid drawing VDD current when switch current flows into
IN/OUT pin, the voltage drop across the bidirectional
current will flow through RL if the switch current flows into
OUT/IN pin.
Typical Performance Characteristics
“ON” Resistance vs Signal
Voltage for TA = 25°C
“ON” Resistance as a
Function of Temperature for
V
DD− VEE = 10V
“ON” Resistance as a
“ON” Resistance as a
Function of Temperature for
Function of Temperature for
V
DD− VEE = 15V
VDD − VEE = 5V
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8
Switching Time Waveforms
9
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Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M16A
www.fairchildsemi.com
10
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
11
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16
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12
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
13
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