CD4093BCN [FAIRCHILD]

Quad 2-Input NAND Schmitt Trigger; 四2输入与非施密特触发器
CD4093BCN
型号: CD4093BCN
厂家: FAIRCHILD SEMICONDUCTOR    FAIRCHILD SEMICONDUCTOR
描述:

Quad 2-Input NAND Schmitt Trigger
四2输入与非施密特触发器

触发器 逻辑集成电路 光电二极管
文件: 总8页 (文件大小:91K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
October 1987  
Revised January 1999  
CD4093BC  
Quad 2-Input NAND Schmitt Trigger  
Equal source and sink currents  
No limit on input rise and fall time  
General Description  
The CD4093B consists of four Schmitt-trigger circuits.  
Each circuit functions as a 2-input NAND gate with Schmitt-  
trigger action on both inputs. The gate switches at different  
points for positive and negative-going signals. The differ-  
ence between the positive (VT+) and the negative voltage  
(VT) is defined as hysteresis voltage (VH).  
Standard B-series output drive  
Hysteresis voltage (any input) TA = 25°C  
Typical  
V
V
V
DD = 5.0V  
DD = 10V  
DD = 15V  
V
V
V
V
H = 1.5V  
H = 2.2V  
H = 2.7V  
H = 0.1 VDD  
All outputs have equal source and sink currents and con-  
form to standard B-series output drive (see Static Electrical  
Characteristics).  
Guaranteed  
Applications  
Features  
Wide supply voltage range: 3.0V to 15V  
Wave and pulse shapers  
High-noise-environment systems  
Monostable multivibrators  
Astable multivibrators  
NAND logic  
Schmitt-trigger on each input  
with no external components  
Noise immunity greater than 50%  
Ordering Code:  
Order Number Package Number  
Package Description  
CD4093BCM  
M14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
CD4093BCN  
N14A  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Pin Assignments for SOIC and DIP  
Top View  
© 1999 Fairchild Semiconductor Corporation  
DS005982.prf  
www.fairchildsemi.com  
Absolute Maximum Ratings(Note 1)  
(Note 2)  
Recommended Operating  
Conditions (Note 2)  
DC Supply Voltage (VDD  
Input Voltage (VIN  
)
0.5 to +18 VDC  
0.5 to VDD +0.5 VDC  
65°C to +150°C  
DC Supply Voltage (VDD  
Input Voltage (VIN  
Operating Temperature Range (TA)  
)
3 to 15 VDC  
0 to VDD VDC  
)
)
Storage Temperature Range (TS)  
Power Dissipation (PD)  
Dual-In-Line  
40°C to +85°C  
Note 1: “Absolute Maximum Ratings” are those values beyond which the  
safety of the device cannot be guaranteed; they are not meant to imply that  
the devices should be operated at these limits. The table of “Recom-  
mended Operating Conditions” and “Electrical Characteristics” provides  
conditions for actual device operation.  
700 mW  
500 mW  
Small Outline  
Lead Temperature (TL)  
(Soldering, 10 seconds)  
Note 2: V = 0V unless otherwise specified.  
SS  
260°C  
DC Electrical Characteristics (Note 2)  
40°C  
+25°C  
+85°C  
Symbol  
Parameter  
Conditions  
Units  
Min  
Max  
Min  
Typ  
Max  
1.0  
2.0  
4.0  
Min  
Max  
I
Quiescent Device  
V
V
V
V
V
V
V
V
V
V
V
= 5V  
1.0  
2.0  
4.0  
7.5  
µA  
µA  
µA  
DD  
DD  
DD  
DD  
Current  
= 10V  
= 15V  
15.0  
30.0  
V
LOW Level  
= V  
|I | < 1 µA  
OL  
IN  
DD, O  
Output Voltage  
= 5V  
0.05  
0.05  
0.05  
0
0
0
0.05  
0.05  
0.05  
0.05  
0.05  
0.05  
V
V
V
DD  
DD  
DD  
= 10V  
= 15V  
V
HIGH Level  
= V , |I | < 1 µA  
SS O  
OH  
IN  
Output Voltage  
= 5V  
4.95  
9.95  
4.95  
9.95  
5
4.95  
9.95  
V
V
V
DD  
DD  
DD  
= 10V  
= 15V  
10  
15  
14.95  
14.95  
14.95  
V −  
Negative-Going Threshold  
Voltage (Any Input)  
|I | < 1 µA  
O
T
V
V
V
= 5V, V = 4.5V  
1.3  
2.25  
4.5  
1.5  
3.0  
4.5  
1.8  
4.1  
6.3  
2.25  
4.5  
1.5  
3.0  
4.5  
2.3  
4.65  
6.9  
V
V
V
DD  
DD  
DD  
O
= 10V, V = 9V  
2.85  
4.35  
O
= 15V, V = 13.5V  
6.75  
6.75  
O
V +  
Positive-Going Threshold  
Voltage (Any Input)  
|I | < 1 µA  
O
T
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
= 5V, V = 0.5V  
2.75  
5.5  
3.6  
2.75  
5.5  
3.3  
6.2  
9.0  
1.5  
2.2  
2.7  
3.5  
7.0  
2.65  
5.35  
8.1  
3.5  
7.0  
V
V
V
V
V
V
DD  
DD  
DD  
DD  
DD  
DD  
O
= 10V, V = 1V  
7.15  
O
= 15V, V = 1.5V  
8.25 10.65 8.25  
10.5  
2.0  
10.5  
2.0  
O
V
Hysteresis (V + − V )  
= 5V  
0.5  
1.0  
1.5  
2.35  
4.3  
0.5  
1.0  
1.5  
0.35  
0.70  
1.20  
H
T
T
(Any Input)  
= 10V  
= 15V  
4.0  
4.0  
6.3  
6.0  
6.0  
I
LOW Level Output  
Current (Note 3)  
= V  
DD  
OL  
IN  
= 5V, V = 0.4V  
0.52  
1.3  
0.44  
1.1  
0.88  
2.25  
8.8  
0.36  
0.9  
mA  
mA  
mA  
DD  
DD  
DD  
O
= 10V, V = 0.5V  
O
= 15V, V = 1.5V  
3.6  
3.0  
2.4  
O
I
HIGH Level Output  
Current (Note 3)  
= V  
SS  
OH  
IN  
= 5V, V = 4.6V  
0.52  
1.3  
3.6  
0.44 0.88  
1.1 2.25  
0.36  
0.9  
2.4  
mA  
mA  
mA  
µA  
DD  
DD  
DD  
DD  
DD  
O
= 10V, V = 9.5V  
O
= 15V, V = 13.5V  
3.0  
8.8  
O
5  
I
Input Current  
= 15V, V = 0V  
0.3  
10  
0.3  
1.0  
IN  
IN  
5  
= 15V, V = 15V  
0.3  
10  
0.3  
1.0  
µA  
IN  
Note 3: I  
and I are tested one output at a time.  
OL  
OH  
www.fairchildsemi.com  
2
AC Electrical Characteristics (Note 4)  
T
A = 25°C, CL = 50 pF, RL = 200k, Input t , t = 20 ns, unless otherwise specified  
r f  
Symbol  
, t  
Parameter  
Conditions  
Min  
Typ  
Max  
Units  
t
t
Propagation Delay Time  
V
V
V
V
V
V
= 5V  
300  
120  
80  
450  
210  
160  
145  
75  
ns  
ns  
ns  
ns  
ns  
ns  
pF  
pF  
PHL PLH  
DD  
DD  
DD  
DD  
DD  
DD  
= 10V  
= 15V  
= 5V  
, t  
Transition Time  
90  
THL TLH  
= 10V  
= 15V  
50  
40  
60  
C
C
Input Capacitance  
(Any Input)  
(Per Gate)  
5.0  
24  
7.5  
IN  
Power Dissipation Capacitance  
PD  
Note 4: AC Parameters are guaranteed by DC correlated testing.  
3
www.fairchildsemi.com  
Typical Applications  
Gated Oscillator  
Assume t + t >> t  
+ t  
then:  
1
2
PHL  
PLH  
t
t
= RC n [V /V ]  
DD T  
0
1
= RC n [(V V )/(V V +)]  
DD  
T
DD  
T
+/V ]  
t
= RC n [V  
T
2
T
Gated One-Shot  
(a) Negative-Edge Triggered  
(b) Positive-Edge Triggered  
www.fairchildsemi.com  
4
Typical Performance Characteristics  
Typical Transfer  
Characteristics  
Guaranteed Trigger Threshold  
Voltage vs VDD  
Guaranteed Hysteresis vs VDD  
Guaranteed Hysteresis vs VDD  
Input and Output Characteristics  
V
V
= V  
V  
V
= V +  
NML  
NMH  
IH(MIN)  
OL  
IH(MIN) T (MIN)  
= V  
V  
V
V  
= V V −  
IL(MAX) DD T (MAX)  
OH  
IL(MAX)  
DD  
5
www.fairchildsemi.com  
AC Test Circuits and Switching Time Waveforms  
www.fairchildsemi.com  
6
Physical Dimensions inches (millimeters) unless otherwise noted  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body  
Package Number M14A  
7
www.fairchildsemi.com  
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
Package Number N14A  
LIFE SUPPORT POLICY  
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT  
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD  
SEMICONDUCTOR CORPORATION. As used herein:  
1. Life support devices or systems are devices or systems  
which, (a) are intended for surgical implant into the  
body, or (b) support or sustain life, and (c) whose failure  
to perform when properly used in accordance with  
instructions for use provided in the labeling, can be rea-  
sonably expected to result in a significant injury to the  
user.  
2. A critical component in any component of a life support  
device or system whose failure to perform can be rea-  
sonably expected to cause the failure of the life support  
device or system, or to affect its safety or effectiveness.  
www.fairchildsemi.com  
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.  

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