DM74ALS564AWMX [FAIRCHILD]

Octal D-Type Flip-Flop ; 八D型触发器\n
DM74ALS564AWMX
型号: DM74ALS564AWMX
厂家: FAIRCHILD SEMICONDUCTOR    FAIRCHILD SEMICONDUCTOR
描述:

Octal D-Type Flip-Flop
八D型触发器\n

总线驱动器 总线收发器 触发器 逻辑集成电路 光电二极管
文件: 总6页 (文件大小:62K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
September 1986  
Revised February 2000  
DM74ALS564A  
Octal D-Type Edge-Triggered Flip-Flop with  
3-STATE Outputs  
General Description  
Features  
Switching specifications at 50 pF  
These 8-bit registers feature totem-pole 3-STATE outputs  
designed specifically for driving highly-capacitive or rela-  
tively low-impedance loads. The high-impedance state and  
increased high-logic-level drive provide these registers with  
the capability of being connected directly to and driving the  
bus lines in a bus-organized system without need for inter-  
face or pull-up components. They are particularly attractive  
for implementing buffer registers, I/O ports, bidirectional  
bus drivers, and working registers.  
Switching specifications guaranteed over full tempera-  
ture and VCC range  
Advanced oxide-isolated, ion-implanted Schottky TTL  
process  
3-STATE buffer-type outputs drive bus lines directly  
The eight flip-flops of the DM74ALS564A are edge-trig-  
gered inverting D-type flip-flops. On the positive transition  
of the clock, the Q outputs will be set to the complement of  
the logic states that were set up at the D inputs.  
A buffered output control input can be used to place the  
eight outputs in either a normal logic state (HIGH or LOW  
logic levels) or a high-impedance state. In the high-imped-  
ance state the outputs neither load nor drive the bus lines  
significantly.  
The output control does not affect the internal operation of  
the flip-flops. That is, the old data can be retained or new  
data can be entered even while the outputs are OFF.  
Ordering Code:  
Order Number  
DM74ALS564AWM  
DM74ALS564AN  
Package Number  
M20B  
Package Description  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
N20A  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
© 2000 Fairchild Semiconductor Corporation  
DS006225  
www.fairchildsemi.com  
Function Table  
Logic Diagram  
Output  
Clock  
D
Output  
Control  
Q
L
L
L
H
L
H
L
L
X
X
X
Q0  
Z
H
L = LOW State  
H = HIGH State  
X = Don’t Care  
↑ = Positive Edge Transition  
Z = High Impedance State  
Q
= Previous Condition of Q  
0
www.fairchildsemi.com  
2
Absolute Maximum Ratings(Note 1)  
Supply Voltage  
7V  
7V  
Input Voltage  
Voltage Applied to Disabled Output  
5.5V  
Note 1: The “Absolute Maximum Ratings” are those values beyond which  
the safety of the device cannot be guaranteed. The device should not be  
operated at these limits. The parametric values defined in the Electrical  
Characteristics tables are not guaranteed at the absolute maximum ratings.  
The “Recommended Operating Conditions” table will define the conditions  
for actual device operation.  
Operating Free Air Temperature Range  
Storage Temperature Range  
Typical θJA  
0°C to +70°C  
65°C to +150°C  
N Package  
56.0°C/W  
75.0°C/W  
M Package  
Recommended Operating Conditions  
Symbol  
Parameter  
Min  
4.5  
2
Nom  
Max  
Units  
V
VCC  
VIH  
VIL  
Supply Voltage  
5
5.5  
HIGH Level Input Voltage  
LOW Level Input Voltage  
HIGH Level Output Current  
LOW Level Output Current  
Clock Frequency  
V
0.8  
2.6  
24  
V
IOH  
IOL  
fCLOCK  
tW  
mA  
mA  
MHz  
ns  
0
14  
14  
15↑  
0↑  
0
30  
Width of Clock Pulse  
HIGH  
LOW  
ns  
tSU  
tH  
Data Setup Time (Note 3)  
Data Hold Time (Note 3)  
ns  
ns  
TA  
Free Air Operating Temperature  
70  
°C  
Note 2: This product meets application requirements of 500 temperature cycles from 65°C to +150°C.  
Note 3: The () arrow indicates the positive edge of the Clock is used for reference.  
Electrical Characteristics  
over recommended operating free air temperature range. All typical values are measured at VCC = 5V, T = 25°C.  
A
Symbol  
Parameter  
Conditions  
= 4.5V, I = −18 mA  
Min  
Typ  
Max  
Units  
V
V
Input Clamp Voltage  
HIGH Level  
V
V
V
V
V
V
1.2  
V
V
IK  
CC  
I
= 4.5V  
OH  
CC  
I
= Max  
2.4  
3.2  
OH  
Output Voltage  
= V Max  
IL  
IL  
= 4.5V to 5.5V  
= 4.5V  
I
I
I
= −400 µA  
= 12 mA  
= 24 mA  
V
2  
V
V
V
CC  
CC  
OH  
OL  
OL  
CC  
V
LOW Level  
0.25  
0.35  
0.4  
0.5  
OL  
Output Voltage  
= 2V  
IH  
I
Input Current @ Maximum  
Input Voltage  
I
V
= 5.5V, V = 7V  
0.1  
mA  
CC  
IH  
I
HIGH Level Input Current  
LOW Level Input Current  
Output Drive Current  
OFF-State Output Current  
HIGH Level Voltage Applied  
OFF-State Output Current  
LOW Level Voltage Applied  
Supply Current  
V
V
V
V
V
V
V
V
= 5.5V, V = 2.7V  
20  
µA  
mA  
mA  
IH  
CC  
CC  
CC  
CC  
IH  
I
= 5.5V, V = 0.4V  
0.2  
112  
IL  
IL  
I
= 5.5V, V = 2.25V  
30  
O
O
I
= 5.5V, V = 2V  
IH  
OZH  
20  
µA  
µA  
= 2.7V  
O
I
= 5.5V, V = 2V  
IH  
OZL  
CC  
20  
= 0.4V  
O
I
= 5.5V  
Outputs HIGH  
Outputs LOW  
10  
15  
16  
18  
24  
30  
mA  
mA  
mA  
CC  
CC  
Outputs OPEN  
Outputs Disabled  
3
www.fairchildsemi.com  
Switching Characteristics  
over recommended operating free air temperature range  
Symbol  
Parameter  
Conditions  
= 4.5V to 5.5V  
CC  
From  
To  
Min  
Max  
Units  
f
Maximum Clock Frequency  
Propagation Delay Time  
LOW-to-HIGH Level Output  
Propagation Delay Time  
HIGH-to-LOW Level Output  
Output Enable Time  
V
30  
MHz  
MAX  
t
R
C
= 500Ω  
= 50 pF  
PLH  
L
Clock  
Any Q  
Any Q  
Any Q  
Any Q  
Any Q  
Any Q  
4
4
4
4
2
3
14  
14  
18  
18  
10  
15  
ns  
ns  
ns  
ns  
ns  
ns  
L
t
PHL  
Clock  
t
Output  
Control  
Output  
Control  
Output  
Control  
Output  
Control  
PZH  
to HIGH Level Output  
Output Enable Time  
t
PZL  
to LOW Level Output  
t
Output Disable Time  
PHZ  
from HIGH Level Output  
Output Disable Time  
t
PLZ  
from LOW Level Output  
www.fairchildsemi.com  
4
Physical Dimensions inches (millimeters) unless otherwise noted  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
Package Number M20B  
5
www.fairchildsemi.com  
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Package Number N20A  
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and  
Fairchild reserves the right at any time without notice to change said circuitry and specifications.  
LIFE SUPPORT POLICY  
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT  
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD  
SEMICONDUCTOR CORPORATION. As used herein:  
1. Life support devices or systems are devices or systems  
which, (a) are intended for surgical implant into the  
body, or (b) support or sustain life, and (c) whose failure  
to perform when properly used in accordance with  
instructions for use provided in the labeling, can be rea-  
sonably expected to result in a significant injury to the  
user.  
2. A critical component in any component of a life support  
device or system whose failure to perform can be rea-  
sonably expected to cause the failure of the life support  
device or system, or to affect its safety or effectiveness.  
www.fairchildsemi.com  
www.fairchildsemi.com  
6

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