DM74LS123CW [FAIRCHILD]
Monostable Multivibrator, LS Series, 2-Func, TTL, WAFER;
| 型号： | DM74LS123CW |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Monostable Multivibrator, LS Series, 2-Func, TTL, WAFER 时钟 逻辑集成电路 |
| 文件： | 总8页 (文件大小：94K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 1986
Revised April 2000
DM74LS123
Dual Retriggerable One-Shot
with Clear and Complementary Outputs
General Description
Features
■ DC triggered from active-HIGH transition or active-LOW
The DM74LS123 is a dual retriggerable monostable multi-
vibrator capable of generating output pulses from a few
nano-seconds to extremely long duration up to 100% duty
cycle. Each device has three inputs permitting the choice of
either leading edge or trailing edge triggering. Pin (A) is an
active-LOW transition trigger input and pin (B) is an active-
HIGH transition trigger input. The clear (CLR) input termi-
nates the output pulse at a predetermined time indepen-
dent of the timing components. The clear input also serves
as a trigger input when it is pulsed with a low level pulse
transition ( ). To obtain the best trouble free operation
from this device please read the operating rules as well as
the Fairchild Semiconductor one-shot application notes
carefully and observe recommendations.
transition inputs
■ Retriggerable to 100% duty cycle
■ Compensated for VCC and temperature variations
■ Triggerable from CLEAR input
■ DTL, TTL compatible
■ Input clamp diodes
Ordering Code:
Order Number Package Number
Package Description
DM74LS123M
DM74LS123SJ
DM74LS123N
M16A
M16D
N16E
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Inputs
Outputs
CLEAR
A
X
H
X
L
B
X
X
L
Q
L
L
L
Q
H
H
H
L
X
X
H
H
↑
↑
↓
H
H
L
H = HIGH Logic Level
L = LOW Logic Level
X = Can Be Either LOW or HIGH
↑ = Positive Going Transition
↓ = Negative Going Transition
= A Positive Pulse
= A Negative Pulse
© 2000 Fairchild Semiconductor Corporation
DS006386
www.fairchildsemi.com
Functional Description
The basic output pulse width is determined by selection of
CLEAR input. Retriggering to 100% duty cycle is possible
by application of an input pulse train whose cycle time is
shorter than the output cycle time such that a continuous
“HIGH” logic state is maintained at the “Q” output.
an external resistor (RX) and capacitor (CX). Once trig-
gered, the basic pulse width may be extended by retrigger-
ing the gated active-LOW transition or active-HIGH
transition inputs or be reduced by use of the active-LOW or
Operating Rules
1. An external resistor (RX) and an external capacitor (CX)
are required for proper operation. The value of CX may
vary from 0 to any necessary value. For small time con-
stants high-grade mica, glass, polypropylene, polycar-
bonate, or polystyrene material capacitors may be
used. For large time constants use tantalum or special
aluminum capacitors. If the timing capacitors have
leakages approaching 100 nA or if stray capacitance
from either terminal to ground is greater than 50 pF the
timing equations may not represent the pulse width the
device generates.
2. When an electrolytic capacitor is used for CX a switch-
ing diode is often required for standard TTL one-shots
to prevent high inverse leakage current. This switching
diode is not needed for the DM74LS123 one-shot and
should not be used. In general the use of the switching
diode is not recommended with retriggerable operation.
FIGURE 2.
5. For CX < 1000 pF see Figure 3 for tW vs. CX family
curves with RX as a parameter:
Furthermore, if a polarized timing capacitor is used on
the DM74LS123 the negative terminal of the capacitor
should be connected to the “CEXT” pin of the device
(Figure 1).
FIGURE 3.
6. To obtain variable pulse widths by remote trimming, the
following circuit is recommended:
FIGURE 1.
3. For CX >> 1000 pF the output pulse width (tW) is
defined as follows:
tW = KRX CX
where [RX is in kΩ]
[CX is in pF]
FIGURE 4.
[tW is in ns]
“Rremote” should be as close to the device pin as possible.
K ≈ 0.37
7. The retriggerable pulse width is calculated as shown
below:
4. The multiplicative factor K is plotted as a function of CX
below for design considerations:
T = tW + tPLH = K × RX × CX + tPLH
The retriggered pulse width is equal to the pulse width
plus a delay time period (Figure 5).
FIGURE 5.
www.fairchildsemi.com
2
Operating Rules (Continued)
8. Output pulse width variation versus VCC and tempera-
9. Under any operating condition CX and RX must be kept
tures: Figure 6 depicts the relationship between pulse
width variation versus VCC, and Figure 7 depicts pulse
as close to the one-shot device pins as possible to min-
imize stray capacitance, to reduce noise pick-up, and
to reduce I-R and Ldi/dt voltage developed along their
connecting paths. If the lead length from CX to pins (6)
width variation versus temperatures.
and (7) or pins (14) and (15) is greater than 3 cm, for
example, the output pulse width might be quite different
from values predicted from the appropriate equations.
A non-inductive and low capacitive path is necessary to
ensure complete discharge of CX in each cycle of its
operation so that the output pulse width will be accu-
rate.
10. The CEXT pins of this device are internally connected to
the internal ground. For optimum system performance
they should be hard wired to the system’s return
ground plane.
11. VCC and ground wiring should conform to good high-
FIGURE 6.
frequency standards and practices so that switching
transients on the VCC and ground return leads do not
cause interaction between one-shots. A 0.01 µF to 0.10
µF bypass capacitor (disk ceramic or monolithic type)
from VCC to ground is necessary on each device. Fur-
thermore, the bypass capacitor should be located as
close to the VCC-pin as space permits.
Note: For further detailed device characteristics and output per-
formance please refer to the Fairchild Semiconductor one-shot
application note AN-372.
FIGURE 7.
3
www.fairchildsemi.com
Absolute Maximum Ratings(Note 1)
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Supply Voltage
Input Voltage
7V
7V
Operating Free Air Temperature Range
Storage Temperature
0°C to +70°C
−65°C to +150°C
Recommended Operating Conditions
Symbol
VCC
Parameter
Min
4.75
2
Nom
Max
Units
V
Supply Voltage
5
5.25
VIH
VIL
IOH
IOL
tW
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Current
LOW Level Output Current
Pulse Width
V
0.8
−0.4
8
V
mA
mA
A or B HIGH
A or B LOW
Clear LOW
40
40
40
5
(Note 2)
ns
REXT
CEXT
CWIRE
TA
External Timing Resistor
260
kΩ
µF
pF
°C
External Timing Capacitance
No Restriction
Wiring Capacitance at REXT/CEXT Terminal
Free Air Operating Temperature
50
70
0
Note 2: TA = 25°C and VCC = 5V.
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Typ
Symbol
Parameter
Conditions
Min
Max
Units
(Note 3)
VI
VOH
Input Clamp Voltage
V
V
V
V
V
CC = Min, II = −18 mA
CC = Min, IOH = Max
IL = Max, VIH = Min
CC = Min, IOL = Max
IL = Max, VIH = Min
−1.5
V
V
HIGH Level
2.7
3.4
Output Voltage
LOW Level
VOL
0.35
0.25
0.5
Output Voltage
V
IOL = 4 mA, VCC = Min
0.4
0.1
II
Input Current @ Max Input Voltage
HIGH Level Input Current
LOW Level Input Current
Short Circuit Output Current
Supply Current
V
V
V
V
V
CC = Max, VI = 7V
mA
µA
IIH
IIL
CC = Max, VI = 2.7V
20
CC = Max, VI = 0.4V
−0.4
−100
20
mA
mA
mA
IOS
ICC
CC = Max (Note 4)
−20
CC = Max (Note 5)(Note 6)(Note 7)
12
Note 3: All typicals are at VCC = 5V, TA = 25°C.
Note 4: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 5: Quiescent ICC is measured (after clearing) with 2.4V applied to all clear and A inputs, B inputs grounded, all outputs OPEN, CEXT = 0.02 µF,
and REXT = 25 kΩ.
Note 6: ICC is measured in the triggered state with 2.4V applied to all clear and B inputs, A inputs grounded, all outputs OPEN, CEXT = 0.02 µF,
and REXT = 25 kΩ.
Note 7: With all outputs OPEN and 4.5V applied to all data and clear inputs, ICC is measured after a momentary ground, then 4.5V is applied to the clock.
www.fairchildsemi.com
4
Switching Characteristics
at V
= 5V and TA = 25°C
CC
RL = 2 kΩ
C
L = 15pF
C
L = 15pF
From (Input)
To (Output)
Symbol
Parameters
Units
C
EXT = 0 pF, REXT = 5 kΩ
CEXT = 1000 pF, REXT = 10 kΩ
Min
Max
Min
Max
tPLH
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
A to Q
B to Q
33
ns
ns
tPLH
tPHL
tPHL
44
45
56
Propagation Delay Time
A to Q
B to Q
ns
ns
HIGH-to-LOW Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
tPLH
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Minimum Width of Pulse
at Output Q
Clear to Q
Clear to Q
45
27
ns
ns
tPHL
tWQ(Min)
A or B to Q
A or B to Q
200
ns
tW(out)
Output Pulse Width
4
5
µs
5
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
www.fairchildsemi.com
6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
7
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
www.fairchildsemi.com
8
相关型号：
©2020 ICPDF网 联系我们和版权申明