DM74LS259N [FAIRCHILD]
8-Bit Addressable Latches; 8位可寻址锁存器
| 型号： | DM74LS259N |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 8-Bit Addressable Latches |
| 文件： | 总6页 (文件大小：62K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 1986
Revised March 2000
DM74LS259
8-Bit Addressable Latches
General Description
Features
These 8-bit addressable latches are designed for general
purpose storage applications in digital systems. Specific
uses include working registers, serial-holding registers,
and active-high decoders or demultiplexers. They are mul-
tifunctional devices capable of storing single-line data in
eight addressable latches, and being a 1-of-8 decoder or
demultiplexer with active-high outputs.
■ 8-Bit parallel-out storage register performs serial-to-par-
allel conversion with storage
■ Asynchronous parallel clear
■ Active high decoder
■ Enable/disable input simplifies expansion
■ Direct replacement for Fairchild DM9334
■ Expandable for N-bit applications
■ Four distinct functional modes
■ Typical propagation delay times:
Enable-to-output 18 ns
Four distinct modes of operation are selectable by control-
ling the clear and enable inputs as enumerated in the func-
tion table. In the addressable-latch mode, data at the data-
in terminal is written into the addressed latch. The
addressed latch will follow the data input with all unad-
dressed latches remaining in their previous states. In the
memory mode, all latches remain in their previous states
and are unaffected by the data or address inputs. To elimi-
nate the possibility of entering erroneous data in the
latches, the enable should be held HIGH (inactive) while
the address lines are changing. In the 1-of-8 decoding or
demultiplexing mode, the addressed output will follow the
level of the D input with all other outputs LOW. In the clear
mode, all outputs are LOW and unaffected by the address
and data inputs.
Data-to-output
16 ns
Address-to-output 21 ns
Clear-to-output
■ Fan-out
17 ns
8 mA
IOL (sink current)
IOH (source current) −0.4 mA
■ Typical ICC 22 mA
Ordering Code:
Order Number Package Number
Package Description
DM74LS259M
DM74LS259WM
DM74LS259N
M16A
M16B
N16E
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2000 Fairchild Semiconductor Corporation
DS006418
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Connection Diagram
Function Table
Inputs
Output of
Each
Addressed Other
Function
Clear
E
L
Latch
D
Output
H
H
L
Qi0
Qi0
L
Addressable Latch
Memory
H
L
Qi0
D
8-Line Demultiplexer
Clear
L
H
L
L
Latch Selection Table
Select Inputs
Latch
C
L
B
L
A
L
Addressed
0
1
2
3
4
5
6
7
L
L
H
L
L
H
H
L
L
H
L
H
H
H
H
L
H
L
H
H
H
H = HIGH Level
L = LOW Level
D = the Level of the Data Input
Q
= the Level of Q (i = 0, 1,…7, as Appropriate) before the Indicated
i0
i
Steady-State Input Conditions Were Established.
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2
Absolute Maximum Ratings(Note 1)
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the “Electrical
Characteristics” table are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Supply Voltage
Input Voltage
7V
7V
Operating Free Air Temperature Range
Storage Temperature Range
0°C to +70°C
−65°C to +150°C
Recommended Operating Conditions
Symbol
Parameter
Min
4.75
2
Nom
Max
Units
V
VCC
VIH
VIL
IOH
IOL
tW
Supply Voltage
5
5.25
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Current
LOW Level Output Current
Pulse Width
V
0.8
−0.4
8
V
mA
mA
Enable
Clear
Data
15
15
ns
ns
(Note 5)
tSU
Setup Time
15↑
15↓
2.5↑
2.5↑
0
(Note 2)(Note 3)(Note 4)(Note 5) Select
tH
Hold Time
Data
ns
(Note 2)(Note 3)(Note 5)
Free Air Operating Temperature
Select
TA
70
°C
Note 2: The symbols (↓, ↑) indicate the edge of the clock pulse used for reference: ↑ for rising edge, ↓ for falling edge.
Note 3: Setup and hold times are with reference to the enable input.
Note 4: The select-to-enable setup time is the time before the HIGH-to-LOW enable transition that the select must be stable so that the correct latch is
selected and the others not affected.
Note 5: T = 25°C and V = 5V.
A
CC
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Typ
Symbol
Parameter
Conditions
= Min, I = −18 mA
Min
Max
Units
(Note 6)
V
V
Input Clamp Voltage
V
V
V
V
V
−1.5
V
V
I
CC
I
HIGH Level
= Min, I = Max
OH
OH
CC
2.7
3.4
Output Voltage
LOW Level
= Max, V = Min
IH
IL
V
= Min, I = Max
OL
OL
CC
0.35
0.25
0.5
0.4
0.1
Output Voltage
= Max, V = Min
V
IL
IH
I
= 4 mA, V = Min
CC
OL
I
Input Current @ Max
Input Voltage
V
= Max, V = 7V
I
CC I
mA
µA
V = 10V
I
I
I
HIGH Level Input Current
LOW Level Input Current
Enable
V
V
V
V
V
= Max, V = 2.7V
20
−0.4
−0.8
−100
36
IH
IL
CC
CC
CC
CC
CC
I
= Max, V = 0.4V
I
mA
= Max, V = 0.4V
I
I
I
Short Circuit Output Current
Supply Current
= Max (Note 7)
= Max (Note 8)
−20
mA
mA
OS
CC
22
Note 6: All typicals are at V = 5V, T = 25°C.
CC
A
Note 7: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 8: I is measured with all inputs at 4.5V, and all outputs OPEN.
CC
3
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Switching Characteristics
at VCC = 5V and T = 25°C
A
From (Input)
To (Output)
C
= 50 pF
= 2 kΩ
L
Symbol
Parameter
R
Units
L
Min
Max
t
t
t
t
t
t
t
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
PLH
Enable to Output
Enable to Output
Data to Output
Data to Output
Select to Output
Select to Output
Clear to Output
38
32
35
30
41
38
36
ns
ns
ns
ns
ns
ns
ns
PHL
PLH
PHL
PLH
PHL
PHL
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Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M16B
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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