FAN1655MX [FAIRCHILD]
3A DDR Bus Termination Regulator; 3A DDR总线终端稳压器
| 型号： | FAN1655MX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 3A DDR Bus Termination Regulator |
| 文件： | 总9页 (文件大小：513K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
www.fairchildsemi.com
FAN1655
3A DDR Bus Termination Regulator
Features
Description
• Sinks and sources 2.1A continuous, 3A peak
• 0 to +125°C operating temperature range
• 5mA Buffered VREFOUT = VDDQ/2
• Load regulation: VTT = VREFOUT ꢀ0mV
• On-chip thermal limiting
The FAN1655 is a low-cost bi-directional LDO specifically
designed for terminating DDR memory bus. It can both sink
and source up to 2.1A continuous, 3A peak, providing
enough current for most DDR applications. Load regulation
meets the JEDEC spec, VTT = VREFOUT ꢀ0mV.
• Low Cost SO-1ꢀ, Power-Enhanced eTSSOP or
8-pin 5x6mm MLP packages
• Low-Current Shutdown Mode
The FAN1655 includes a buffered reference voltage capable
of supplying up to 5mA current. On-chip thermal limiting
provides protection against a combination of power overload
and ambient temperature that would create an excessive
junction temperature. A shutdown input puts the FAN1655
into a low power mode.
• Output Short Circuit Protection
Applications
• DDR Terminator VTT supply
The FAN1655 regulator is available in a power-enhanced
eTSSOP™-16, standard SOIC-1ꢀ, and an 8-Lead MLP
package.
Block Diagram
VDDQ
200k
VDD
VDD
VDD
SHDN
-
VREFOUT
VREFIN
+
VTTFORCE
VTTFORCE
+
-
200k
VTTSENSE
FAN1655
VSS VSS
VSS
VSSQ
REV. 1.1.4 3/24/04
PRODUCT SPECIFICATION
FAN1655
Pin Assignments
16
VDD
NC
1
2
3
4
5
6
7
8
VDD
14
VDDQ
VDDQ
VREFOUT
VSSQ
1
2
3
4
5
6
7
VDD
VTTFORCE
VSS
15
14
13
12
11
10
9
VREFOUT
VSSQ
VDD
VTTFORCE
VTTFORCE
VDD
1
2
3
4
8
7
6
5
VDD
VTTFORCE
VSS
13
12
VDDQ
FAN1655
VREFOUT
SHDN
FAN1655M
SHDN
VSS
SHDN
11
10
9
VSS
VREFIN
VTTSENSE
VSS
VTTFORCE
VREFIN
VTTSENSE
NC
VTTFORCE
VDD
VDD
VSS
8
VTTSENSE
GND
16-Lead Plastic eTSSOP-16
JC = 4˚C/W*
14-Lead Plastic SOIC
JC = 37˚C/W, θJA = 88˚C/W
θ
θ
8-Lead MLP Package (5x6mm)
*Thermal impedance is measured with the
power pad soldered to a 0.5 square inch
copper area. The copper area should be
connected to Vss (ground) and positioned
over an internal power or ground plane to
assist in heat dissipation.
θ
JC = 4˚C/W, θJA = 34˚C/W as
measured on FAN1655MP
Eval Board
Pin Definitions
Pin
MLP
1, 4
2, 3
PAD
5
eTSSOP
1, 2, 7
3, 6
SOIC-14
1, 2, 7
3, 6
Pin Name
VDD
Pin Function Description
Input power for the LDO.
VTTFORCE
VSS
The VTT output voltage.
4, 5, 8
10
4, 5, 8
9
IC Ground.
VTTSENSE
VREFIN
Feedback for remote sense of the VTT voltage.
11
10
Alternative input for direct control of VTTOUT and
VREFOUT.
6
12
11
SHDN
Shutdown. This active low shutdown turns off both VTT
and VREFOUT. This pin has an internal pull-down, and
must be externally driven high for the IC to be on.
13
14
15
12
13
14
VSSQ
VREFOUT
VDDQ
Signal Ground.
7
8
Buffered Voltage Reference Output.
VDDQ Input. Attach this pin to the VDDQ supply to
generate VTT and VREFOUT.
9, 16
PAD
NC
No Internal Connection
PAD
Connect PAD to Vss Ground Plane
Typical Application
VDDQ
VDD
VTTFORCE
470µF
10µF
16
1
2
3
4
5
6
7
8
10k
15
14
13
VREFOUT
1nF
SHDN
FAN1655
12
11
10
9
VTTSENSE
(connect to VTTFORCE
at the load)
100µF
1nF
6V
10µF
GND
GND
Figure 1. (eTSSOP pinout shown)
2
REV. 1.1.4 3/24/04
FAN1655
PRODUCT SPECIFICATION
Typical Performance Characteristics
Quiescent Current vs. Temperature
V
REF Output Change vs. IREF
9
1.0
0.5
V
DD = VDDQ = 2.5V
7.5
6
TA = 25˚C
4.5
3
0
-0.5
-1.0
1.5
0
4
-1
0
2
5
6
140
120
40 60 80 100
1
3
-6 -5
-4 -3
-2
-20
0
-60 -40
20
AMBIENT TEMPERATURE (˚C)
V
REF LOAD CURRENT (mA)
Figure 2. Quiescent Current vs.
Ambient Temperature
Figure 3. Reference Output
Load Regulation
100.0
10.0
1.0
1.260
1.255
TA=70°C
TA=25°C
1.250
1.245
1.240
1
1.5
2
2.5
3
-3000
-2000
-1000
0
1000
2000
3000
Peak Load Current (A)
VTT Load Current (mA)
Figure 5. Maximum Non-Repetitive Output
Current vs. Pulse Width
Figure 4. VTT Load Regulation
(FAN1655M SO-14 Package)
REV. 1.1.4 3/24/04
3
PRODUCT SPECIFICATION
FAN1655
Absolute Maximum Ratings
Supply Voltage VDD, VDDQ
Junction Temperature, TJ
Storage Temperature
6V
150˚C
-65 to 150˚C
300˚C
Lead Soldering Temperature, 10 seconds
Power Dissipation, PD
FAN1655M (SOIC-14)
1.4W
FAN1655MTF (e-TSSOP)
FAN1655MP (MLP)
See “Power Dissipation
and Derating”
Recommended Operating Conditions
Parameter
Supply Voltage VDD
Conditions
Min.
2.3
2.2
0
Typ.
2.5
Max.
3.6
Units
V
Supply Voltage VDDQ
Ambient Operating Temperature
VREFIN
2.5
3.0
V
125
1.5
˚C
V
1.1
1.25
Electrical Characteristics
(VDD = VDDQ = 2.5V 0.2V, and TA = 25˚C using circuit in Figure 1, unless otherwise noted.)
The • denotes specifications which apply over the specified operating temperature range.
Parameter
VTT Output Voltage
Conditions
Min.
Typ. Max. Units
IOUT = 0A, VREFIN = open
1.135 1.150 1.165
1.235 1.250 1.265
1.335 1.350 1.365
V
V
V
VDDQ = 2.3V
VDDQ = 2.5V
VDDQ = 2.7V
•
•
•
IOUT = 2.1A, VREFIN = open
1.110 1.150 1.190
1.210 1.250 1.290
1.310 1.350 1.390
V
V
V
VDDQ = 2.3V
VDDQ = 2.5V
VDDQ = 2.7V
VTT Output Slew Rate
VTT Leakage Current
VTT Current Limit
Cload = 10µF
SHDN = 0V
0.3
V/µS
µA
A
•
-50
3.1
50
VREFIN Input Impedance
VREFOUT Output Voltage
100
KΩ
No load
VREFIN = 1.150V • 1.145 1.150 1.155
VREFIN = 1.250V • 1.245 1.250 1.255
VREFIN = 1.350V • 1.345 1.350 1.355
V
V
V
VREFOUT Output Current
VREFOUT Leakage Current
SHDN Logic High
SHDN Logic Low
IDD Supply Current
VDDQ Leakage Current
VDD Leakage Current
SHDN Input Current
Over-Temperature Shutdown
Over-Temperature Hysteresis
VDDQ = 2.3V
SHDN = 0V
•
•
•
•
•
•
•
•
-5
-10
1.667
5
10
mA
µA
V
0.800
20
10
50
75
V
No load, SHDN = 2.7V
SHDN = 0V
SHDN = 0V
7.5
6
3
50
155
30
mA
µA
µA
µA
˚C
˚C
SHDN = 2.7V
4
REV. 1.1.4 3/24/04
FAN1655
PRODUCT SPECIFICATION
Power Dissipation and Derating
The maximum output current (sink or source) for a 1.25V
output is:
Applications Information
Output Capacitor selection
The JEDEC specification for DDR termination requires that
VTT stay within ꢀ0mV of VREF, which must track
PD(MAX)
IOUT(MAX) = ----------------------
1.25
(1)
VDDQ/2 within 1%. During the initial load transient, the
output capacitor keeps the output within spec. To stay within
the ꢀ0mV window, the “load step” due to the load transient
current dropping across the output capacitor’s ESR should be
where PD(MAX) is the maximum power dissipation which is:
T
J(MAX) – TA
25
-----
PD(MAX) = ----------------------------------
(2)
kept to around 25mV: where ESR <
∆I is the maximum load current.
is given in mΩ, and
θJA
∆I
where TJ(MAX) is the maximum die temperature of the IC
and TA is the operating ambient temperature.
For example, to handle a 3A maximum load transient, the
ESR should be no greater than 8mΩ. Furthermore, the output
capacitor must be able to hold the load in spec while the
regulator recovers (about 15µS). A minimum value of ꢀ70µF
is recommended.
FAN1655 has an internal thermal limit at 150°C, which
defines TJ(MAX). For the SOIC-1ꢀ package, θJA is given at
88°C/W. Using equation 2, the maximum dissipation at
TA = 25°C is 1.ꢀW, which is its rated maximum dissipation.
These requirements can be achieved by a combination of
capacitors. FAN1655 requires a minimum of 5mΩ of ESR
in the output and is not stable with all-ceramic output
capacitors.
The e-TSSOP or MLP package, however, use the PCB
copper to cool the IC through the thermal pad on the package
bottom. For maximum dissipation, this pad should be
soldered to the PCB copper, with as much copper area as
possible surrounding it to cool the package. Thermal vias
should be placed as close to the thermal pad as possible to
transfer heat to other layers of copper on the PCB. With large
areas of PCB copper for heat sinking, a θJA of under ꢀ0°C/W
can easily be achieved.
REV. 1.1.4 3/24/04
5
PRODUCT SPECIFICATION
FAN1655
Mechanical Dimensions
16-Lead eTSSOP
-A-
5.0 0.1
0.10 TYP
16
4.00
9
16
9
-B-
6.4
4.4 0.1
7.72
3.40
4.16
3.2
0.2 C B A
ALL LEAD TIPS
1
8
(1.78)
PIN #1 IDENT.
1
8
ALL LEAD TIPS
0.1 C
0.42 TYP
+0.15
0.65 TYP
LAND PATTERN RECOMMENDATION
1.2 MAX
(0.90)
–0.10
-C-
0.10 0.05 TYP
(0.19–0.30)
0.65 TYP
M
0.10
C B A
SEE DETAIL A
1.7 MIN
(0.09–0.20)
9
16
1.5 MIN
12° TOP & BOTTOM
GAGE PLANE
0.25
R0.09MIN
0°–8°
8
1
SEATING PLANE
0.75
0.45
BOTTOM VIEW
(1.00)
DETAIL A
NOTES:
A. CONFORMS TO JEDEC REGISTRATION MO-153, VARIATION ABT,
DATED 10/97.
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH,
AND THE BAR EXTENSIONS.
D. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994.
6
REV. 1.1.4 3/24/04
PRODUCT SPECIFICATION
FAN1655
Mechanical Dimensions
14-Lead SOIC
NOTES:
1. This package conforms to JEDEC MS-012, variation AB, ISSUEC dated May, 1990.
2. All dimensions are in millimeters
3. Standard lead finished
200 microinches / 5.08 microns min.
Lead/Tin (solder) oncopper
0.50
S8.71-8.51;
7.62
8
12
10
9
13
11
14
5.75
1.00
S4.00-3.80
S6.20-5.80;
1.27
2
3
4
5
6
1
7
7.62
LAND PATTERN RECOMMENDATION
S0.51-0.35;
1.27
S0.50-0.25;X45˚
S0.25-0.19;
S0.25-0.10;z
S8˚-0˚
S1.75-1.35;
S1.27-0.40;
SEATING PLANE
7
REV. 1.1.4 3/24/04
PRODUCT SPECIFICATION
FAN1655
Mechanical Dimensions
5mmX6mm 8-Lead MLP
5.0
A
4.50
B
6.25
4.25
3.50
6.0
(1.00)
0.25
C
2X
0.65 TYP
1.27 TYP
TOP VIEW
SIDE VIEW
0.25
C
2X
C
LAND PATTERN RECOMMENDATION
0.10
0.08
(0.25)
1.0 MAX
C
C
0.05
0.00
SEATING
PLANE
4.25
1.75
A
1
2
3
4
0.75
A
A
0.35
PIN #1 IDENT.
(OPTIONAL)
NOTES:
A) DOES NOT FULLY CONFORM TO JEDEC
REGISTRATION MO-229, DATED 11/2001.
3.25
1.25
B) DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONING AND TOLERANCES PER
ASME Y14.5–1994.
8
7
6
5
0.28–0.40 A
0.10 M
1.27
C
C
A B
3.81
A
M
0.05
BOTTOM VIEW
8
REV. 1.1.4 3/24/04
PRODUCT SPECIFICATION
FAN1655
Ordering Information
Part Number
FAN1655M
Temperature Range
0°C to 125°C
0°C to 125°C
0°C to 125°C
0°C to 125°C
0°C to 125°C
Package
SOIC-14
Packing
Rails
FAN1655MX
FAN1655MTF
FAN1655MTFX
FAN1655MPX
SOIC-14
Tape and Reel
Rails
eTSSOP-16
eTSSOP-16
MLP-8
Tape and Reel
Tape and Reel
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER
DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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3/24/04 0.0m 004
Stock#DS30004854
2004 Fairchild Semiconductor Corporation
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