FAN2103EMPX [FAIRCHILD]
3A, 24V Input Integrated Synchronous Buck Regulator; 3A ， 24V输入集成同步降压稳压器
| 型号： | FAN2103EMPX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 3A, 24V Input Integrated Synchronous Buck Regulator |
| 文件： | 总14页 (文件大小：887K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
December 2007
FAN2103 — TinyBuck™
3A, 24V Input Integrated Synchronous Buck Regulator
Features
Description
The FAN2103 TinyBuck™ is an easy-to-use, cost- and
space-efficient, synchronous buck solution. It enables
designers to solve high-current requirements in a small
area with minimal external components.
Over 95% efficiency
Internal power MOSFETs:
High-side RDS(ON) = 31mΩ
Low-side RDS(ON) = 23mΩ
External programming of clock frequency, current limit,
and loop response allows for optimization and flexibility
selecting output filter components and transient response.
Integrated low-side Schottky diode
Programmable frequency operation up to 750KHz
Power-good signal
The summing current mode modulator uses lossless
current sensing for current feedback and over-current,
and includes voltage feedforward.
Wide input range: 3.0V to 24V
Output voltage range: 0.8V to 90%VIN
Input under-voltage lockout (UVLO)
Programmable over-current protection
Under-voltage, over-voltage, and thermal protection
Selectable light-load power-saving mode
5x6mm, 25-pin, 3-pad MLP
Fairchild’s advanced BiCMOS power process,
combined with a thermally efficient MLP package,
provides low-RDS(ON), internal MOSFETs, and the ability
to dissipate high power in a small package.
Under-voltage, thermal shutdown, and power-good are
blanked at start-up, but protect the device from damage
during fault conditions.
Related Application Notes
Applications
AN-5067 – PCB land pattern design and surface
mount guidelines for MLP packages
Thin and light Notebook PCs
Graphics cards
Battery-powered equipment
Set-top box
Point-of-load regulation
Ordering Information
Operating
Part Number
Temperature Range
Package
Packing Method
FAN2103MPX
-10°C to 85°C
-40°C to 85°C
25-Pin Molded Leadless Package (MLP) 5x6mm Tape and Reel
25-Pin Molded Leadless Package (MLP) 5x6mm Tape and Reel
FAN2103EMPX
All packages are lead free per JEDEC: J-STD-020B standard.
© 2007 Fairchild Semiconductor Corporation
FAN2103 Rev. 1.0.3
www.fairchildsemi.com
Typical Application Diagram
VIN
VIN
P2
1
+5V
RRAMP
VCC
15
CHF
CIN
BOOT
Q1
Q2
C4
CBOOT
RAMP
25
VOUT
PGOOD
SW
13
P1
L
COUT
EN
14
RILIM
PWM
MODULATOR
ILIM
17
RT
R(T)
18
PGND
PWM#
FB
P3
24
19
COMP
20
C2
R1
C1
AGND
16
C3
RBIAS
R2
R3
Figure 1. Typical Application
Block Diagram
Figure 2. Block Diagram
© 2007 Fairchild Semiconductor Corporation
FAN2103 Rev. 1.0.3
www.fairchildsemi.com
2
Pin Configuration
Figure 3. MLP 5x6mm Pin Configuration (Bottom View)
Pin Definitions
Pin
Name Description
P1, 6-12
P2, 2-5
SW
VIN
Switching Node.
Power Input Voltage. Connect to the main input power source.
Power Ground. Power return and Q2 source.
P3, 21-23
PGND
High-side Drive BOOT Voltage. Connect through capacitor (CBOOT) to SW. The IC includes
an internal synchronous bootstrap diode to recharge the capacitor on this pin to VCC when
SW is LOW.
1
BOOT
PGOOD
EN
Power-Good Flag. An open-drain output that pulls LOW when FB is outside a ±10% range
of the reference when EN is HIGH. PGOOD does not assert HIGH until the fault latch is
enabled.
13
14
ENABLE. Enables operation when pulled to logic HIGH or left open. Toggling EN resets the
regulator after a latched fault condition. This input has an internal pull-up when the IC is
functioning normally. When a latched fault occurs, EN is discharged by a current sink.
15
16
VCC
Input Bias Supply for IC. The IC’s logic and analog circuitry are powered from this pin.
Analog Ground. The signal ground for the IC. All internal control voltages are referred to
this pin. Tie this pin to the ground island/plane through the lowest impedance connection.
AGND
Current Limit. A resistor (RILIM) from this pin to AGND can be used to program the current-
limit trip threshold lower than the default setting.
17
ILIM
Oscillator Frequency. A resistor (RT) from this pin to AGND sets the PWM switching
frequency.
18
19
20
R(T)
FB
Output Voltage Feedback. Connect through a resistor divider to the output voltage.
Compensation. Error amplifier output. Connect the external compensation network
between this pin and FB.
COMP
Power Save Mode / Forced PWM. Connect to VCC to enable light-load, power-saving mode
of operation. Connect to GND or leave open for fixed-frequency PWM mode.
24
25
PWM#
RAMP
Ramp Amplitude. A resistor (RRAMP) connected from this pin to VIN sets the ramp
amplitude and provides voltage feedforward functionality.
© 2007 Fairchild Semiconductor Corporation
FAN2103 Rev. 1.0.3
www.fairchildsemi.com
3
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only.
Parameter
VIN to PGND
VCC to AGND
BOOT to PGND
BOOT to SW
SW to PGND
All other pins
Conditions
Min.
Max.
28
Unit
V
AGND = PGND
6
V
35
V
-0.3
-5
6.0
V
Transient (t < 20ns, F < 600KHz)
30
V
-0.3
2.0
2.0
VCC+0.3
V
Human Body Model, JESD22-A114
Charged Device Model, JESD22-C101
ESD
kV
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
VCC
Parameter
Bias Voltage
Conditions
VCC to AGND
Min.
4.5
3
Typ.
Max.
5.5
Unit
V
5.0
VIN
Supply Voltage
VIN to PGND
FAN2103M
24
V
-10
-40
+85
+85
+125
°C
°C
°C
TA
TJ
Ambient Temperature
Junction Temperature
FAN2103EM
Thermal Information
Symbol
Parameter
Min.
Typ.
Max.
+150
+300
+215
+220
Unit
°C
TSTG
TL
Storage Temperature
-65
Lead Soldering Temperature, 10 Seconds
Vapor Phase, 60 Seconds
°C
TVP
TI
°C
Infrared, 15 Seconds
°C
P1 (Q2)
P2 (Q1)
P3
4
7
°C/W
°C/W
°C/W
°C/W
W
Thermal Resistance: Junction-to-Case
θJC
4
35(1)
Thermal Resistance: Junction-to-Mounting Surface
Power Dissipation, TA = 25°C
θJ-PCB
PD
2.8(1)
Note:
1. Typical thermal resistance when mounted on a four-layer, two-ounce PCB, as shown in Figure 26. Actual results
are dependent on mounting method and surface related to the design.
© 2007 Fairchild Semiconductor Corporation
FAN2103 Rev. 1.0.3
www.fairchildsemi.com
4
Electrical Specifications
Recommended operating conditions are the result of using the circuit shown in Figure 1 unless otherwise noted.
Parameter
Power Supplies
Conditions
Min.
Typ.
Max.
Unit
SW = Open, FB = 0.7V, VCC = 5V,
8
12
mA
F
SW = 600KHz
VCC Current
Shutdown: EN = 0, VCC = 5V
Power Saving Mode, VCC = 5V, FMIN
Rising VCC
7
10
4.5
4.5
µA
mA
V
2.2
4.3
300
4.1
VCC UVLO Threshold
Hysteresis
mV
Power Output Section
N-Channel (Q1) RDS(ON)
N-Channel (Q2) RDS(ON)
Oscillator
31
23
35
25
mΩ
mΩ
VCC = 5V, 25°C
255
540
300
600
50
345
660
65
KHz
KHz
ns
RT = 50KΩ
RT = 24KΩ
Frequency
Minimum On-Time(2)
16VIN, 1.8VOUT, RT = 30KΩ,
Ramp Amplitude, pk–pk
0.53
100
V
RRAMP = 200KΩ
Minimum Off-Time(2)
150
ns
Reference
FAN2103M, 25°C
794
795
800
800
50
806
805
mV
mV
Reference Voltage (VFB)
FAN2103EM, 25°C
FAN2103M,
Temp. Coefficient (-10 to +85°C)
Temp. Coefficient (-40 to +85°C)
PPM
PPM
FAN2103EM
70
Error Amplifier
DC Gain(2)
Gain Bandwidth Product(2)
80
12
85
15
dB
MHz
V
V
CC = 5V
Output Voltage (VCOMP
)
0.4
1.5
0.8
-850
3.2
Output Current, Sourcing
Output Current, Sinking
FB Bias Current
VCC = 5V, VCOMP = 2.2V
VCC = 5V, VCOMP = 1.2V
VFB = 0.8V, 25°C
2.2
1.2
mA
mA
nA
-650
-450
Protection and Shutdown
Current Limit
RILIM open
3.8
9
5.0
10
7.0
11
A
µA
ILIM Current
25°C, VCC = 5V
Over-Temperature Shutdown
Over-Temperature Hysteresis
Over-Voltage Threshold
Under-Voltage Shutdown
Fault Discharge Threshold
Fault Discharge Hysteresis
Note:
160
30
°C
Internal Temperature
°C
2 Consecutive Clock Cycles
16 Consecutive Clock Cycles
Measured at FB Pin
110
68
115
73
120
78
%VOUT
%VOUT
mV
250
250
Measured at FB Pin (VFB ~500mV)
mV
2. Specifications guaranteed by design and characterization; not production tested.
© 2007 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN2103 Rev. 1.0.3
5
Electrical Specifications (Continued)
Recommended operating conditions are the result of using the circuit shown in Figure 1 unless otherwise noted.
Parameter
Conditions
Min.
Typ.
Max.
Unit
Soft-Start
VOUT to Regulation (T0.8
)
5.3
6.7
ms
ms
Frequency = 600KHz
Fault Enable/SSOK (T1.0
Control Functions
EN Threshold, Rising
EN Hysteresis
)
1.35
250
800
1
2.00
V
mV
KΩ
µA
EN Pull-up Resistance
EN Discharge Current
Auto-restart Mode
FB OK Drive Resistance
800
-8
Ω
FB < VREF
FB > VREF
IOUT < 2mA
VPGOOD = 5V
-14
-11
%VFB
%VFB
V
PGOOD Threshold
107
110
113
0.4
1
PGOOD Output Low
PGOOD Output High
PWM# Threshold
µA
0.6
1.0
0.8
1.2
V
PWM# Input Current
VPWM# = 0.4V
µA
© 2007 Fairchild Semiconductor Corporation
FAN2103 Rev. 1.0.3
www.fairchildsemi.com
6
Typical Characteristics
1.010
1.005
1.000
0.995
0.990
1.20
1.10
1.00
0.90
0.80
-50
0
50
100
150
-50
0
50
100
150
Temperature (oC)
Temperature (oC)
Figure 4. Reference Voltage (VFB) vs. Temperature,
Normalized
Figure 5. Reference Bias Current (IFB) vs.
Temperature, Normalized
1500
1200
900
600
300
0
1.02
1.01
1.00
0.99
0.98
600KHz
300KHz
-50
0
50
100
150
0
20
40
60
80
100
120
140
Temperature (oC)
RT (K )
Ω
Figure 6. Frequency vs. RT
Figure 7. Frequency vs. Temperature, Normalized
1.04
1.02
1.00
0.98
0.96
1.60
1.40
1.20
1.00
0.80
0.60
Q1 ~0.32 %/oC
Q2 ~0.35 %/oC
-50
0
50
100
150
-50
0
50
Temperature (oC)
100
150
Temperature (oC)
Figure 9. ILIM Current (IILIM) vs. Temperature,
Normalized
Figure 8. RDS vs. Temperature, Normalized
(VCC = VGS = 5V)
© 2007 Fairchild Semiconductor Corporation
FAN2103 Rev. 1.0.3
www.fairchildsemi.com
7
Application Circuit
Figure 10. Application Circuit: 1.8 VOUT, 500KHz
Typical Performance Characteristics
Typical operating characteristics using the circuit shown in Figure 10. VIN=16V, VCC=5V, unless otherwise specified.
Power Loss
Efficiency
100
95
90
85
80
75
70
65
60
55
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
Loss8V (W)
Loss12V (W)
Loss_PSM (W)
Loss18V (W)
Effi8V (%)
Effi12V (%)
Effi_PSM_12V(%)
Effi18V (%)
Power Saving Mode, 12VIN
0.00
0.50
1.00
1.50
2.00
2.50
3.00
0.00
0.50
1.00
1.50
2.00
2.50
3.00
Load Current (A)
Load Current (A)
Figure 11. 1.8 VOUT Efficiency Over VIN vs. Load
Figure 12. 1.8 VOUT Dissipation Over VIN vs. Load
Regulation Characteristic
Efficiency
100
1.828
95
90
85
80
75
1.826
1.824
1.822
Vo8V (V)
1.820
1.818
Vo12V (V)
Vo18V (V)
V
V
=8V, 300KHz
=12V, 500Khz
IN
IN
70
65
0.00
0.50
1.00
1.50
2.00
2.50
3.00
0.00
0.50
1.00
1.50
2.00
2.50
3.00
Load Current (A)
Load Current (A)
Figure 13. 1.8 VOUT Regulation vs. Load
Figure 14. 3.3 VOUT Efficiency vs. Load
(Circuit Values Changed)
© 2007 Fairchild Semiconductor Corporation
FAN2103 Rev. 1.0.3
www.fairchildsemi.com
8
Typical Performance Characteristics (Continued)
Typical operating characteristics using the circuit shown in Figure 10. VIN=12V, VCC=5V, unless otherwise specified.
Figure 15. SW and VOUT Ripple, 3A Load
Figure 16. SW and VOUT Ripple, 0.5A Load
Figure 17. Transient Response, 1.5-3A Load
(Circuit Values Changed)
Figure 18. Transient Response, 0.3-3A Load
(Circuit Values Changed)
Figure 19. Start-up, 3A Load
Figure 20.
Shutdown, 3A Load
© 2007 Fairchild Semiconductor Corporation
FAN2103 Rev. 1.0.3
www.fairchildsemi.com
9
Circuit Description
Initialization
Once VCC exceeds the UVLO threshold and EN is
HIGH, the IC checks for an open or shorted FB pin
before releasing the internal soft-start ramp (SS).
Since VCC is used to drive the internal MOSFET gates,
supply current is frequency and voltage dependent.
Approximate VCC current (ICC) can be calculated using:
VCC − 5
227
ICC
= 4.58 + [(
+ 0.013) • (F −128)]
(1)
(mA)
If R1 is open, the error amplifier output (COMP) is forced
LOW and no pulses are generated. After the SS ramp
times out (T1.0), an under-voltage latched fault occurs.
where frequency (F) is expressed in KHz.
Setting the Output Voltage
If the parallel combination of R1 and RBIAS is ≤ 1KΩ, the
internal SS ramp is not released and the regulator does
not start.
The output voltage of the regulator can be set from 0.8V
to ~90% of VIN by an external resistor divider (R1 and
RBIAS in Figure 1).
Soft-Start
The internal reference is 0.8V with 650nA, sourced from
the FB pin to ensure that if the pin is open, the regulator
does not start.
Once SS has charged to 0.8V (T0.8), the output voltage
is in regulation. Until SS reaches 1.0V (T1.0), the “Fault
Latch” and power-saving mode operations are inhibited.
The external resistor divider is calculated using:
To avoid skipping the soft-start cycle, it is necessary to
apply VIN before VCC reaches its UVLO threshold.
VOUT − 0.8V
0.8V
=
+ 650nA
(2)
RBIAS
R1
Soft-start time is a function of oscillator frequency.
Connect RBIAS between FB and AGND.
To minimize noise on the FB node, the values of R1
and RBIAS should be selected to provide a minimum
parallel impedance of 1KΩ.
1.35V
EN
2400 CLKs
0.8V
Setting the Frequency
FB
Oscillator frequency is determined by an external resistor,
RT, connected between the R(T) pin and AGND:
Fault
Latch
Enable
1.0V
0.8V
106
F
=
(3)
(KHz)
SS
(65 • RT ) + 135
3200 CLKs
4000 CLKs
where RT is expressed in KΩ.
(106 /F) −135
T0.8
(4)
RT
=
(KΩ)
65
T1.0
where frequency (F) is expressed in KHz.
The regulator does not start if RT is left open.
Figure 21. Soft-Start Timing Diagram
Calculating the Inductor Value
The regulator does not allow the low-side MOSFET to
operate in full synchronous rectification mode until SS
reaches 95% of VREF (~0.76V). This helps the regulator
start against pre-biased outputs and ensures that
inductor current does not "ratchet" up during the soft-
start cycle.
Typically the inductor is set for a ripple current (ΔIL) of
10% to 35% of the maximum DC load. Regulators
requiring fast transient response use a value on the
high side of this range, while regulators that require very
low output ripple and/or use high-ESR capacitors
restrict allowable ripple current:
VCC UVLO or toggling the EN pin discharges the SS and
resets the IC.
VOUT • (1-D)
ΔIL =
(5)
Bias Supply
L •F
The FAN2103 requires a 5V supply rail to bias the IC
and provide gate-drive energy and controller power.
Connect a >1.0µf X5R or X7R decoupling capacitor
between VCC and PGND. Whenever EN pin is pulled
up to VCC, the 5V supply connected to VCC should be
turned ON after VIN comes up. If the power supply is
turned ON using EN pin with an external control after
VCC and VIN come up, the VCC and VIN power
sequencing is not relevant.
where F is the oscillator frequency, and
VOUT • (1- D)
L =
(6)
ΔIL • F
The selection of inductor influences the entry into
power-saving mode. Consider minimum and maximum
load conditions before inductor selection.
© 2007 Fairchild Semiconductor Corporation
FAN2103 Rev. 1.0.3
www.fairchildsemi.com
10
Because the FAN2103 employs summing current-mode
architecture, Type-2 compensation can be used for
many applications. For applications that require wide
loop bandwidth and/or use very low-ESR output
capacitors, Type-3 compensation may be required.
Setting the Ramp Resistor Value
The internal ramp voltage excursion (ΔVRAMP) during tON
should be set to 0.6V. RRAMP is approximately:
(V −1.8) • VOUT
IN
RRAMP(KΩ)
=
− 2
(7)
18x10−6 • V • F
RRAMP provides feedforward compensation for changes
in VIN. With a fixed RRAMP value, the modulator gain
increases as VIN is reduced, which could make it difficult
to compensate the loop. For designs with low input
voltages (3V to 6.5V), it is recommended that separate
RRAMP and the compensation component values are
used as compared to designs with VIN between 6.5V
and 24V.
IN
where frequency (F) is expressed in KHz.
Setting the Current Limit
There are two levels of current limit thresholds in
FAN2103. The first level of protection is through an
internal default limit set at the factory to limit output
current beyond normal usage levels. The second level
of protection is a flexible one to be set externally by the
user. Current limit protection is enabled whenever the
lower of the two thresholds is reached. The FAN2103
uses its internal low-side MOSFET as the current-
sensing element. The current-limit threshold voltage
(VILIM) is compared to the voltage drop across the low-
side MOSFET, sampled at the end of each PWM off-
time/cycle. The internal default threshold (with ILIM open)
is temperature compensated.
Protection
The converter output is monitored and protected
against extreme overload, short-circuit, over-voltage,
and under-voltage conditions.
An internal “Fault Latch” is set for any fault intended to
shut down the IC. When the fault latch is set, the IC
discharges VOUT by enhancing the low-side MOSFET
until FB<0.25V. The MOSFET is not turned on again
unless FB>0.5V. This behavior discharges the output
without causing undershoot (negative output voltage).
The 10µA current sourced from the ILIM pin can be
used to establish a lower, temperature–dependent,
current-limit threshold by connecting an external
resistor (RILIM) to AGND:
FAULT
0.25/0.5V
PWM GATE
ΔIL
2
DRIVE
(8)
RILIM(KΩ) =10.4 • KT • (IOUT
−
) + 142.5
FB
PWM LATCH
where:
I
OUT = desired current limit set point in Amps,
Figure 23. Latched Fault Response
KT = the normalized temperature coefficient of the
low-side MOSFET (Q2) from Figure 8.
Under-Voltage Shutdown
After 16 consecutive, pulse-by-pulse, current-limit
cycles, the fault latch is set and the regulator shuts
down. Cycling VCC or EN restores operation after a
normal soft-start cycle (refer to Auto-Restart section).
If FB remains below the under-voltage threshold for 16
consecutive clock cycles, the fault latch is set and the
converter shuts down. This fault is prevented from
setting the fault latch during soft-start.
The over-current protection fault latch is active during
the soft-start cycle. Use a 1% resistor for RILIM.
Over-Voltage Protection / Shutdown
Loop Compensation
If FB exceeds 115% • VREF for two consecutive clock
cycles, the fault latch is set and shutdown occurs.
The loop is compensated using a feedback network
around the error amplifier. Figure 22 shows a complete
Type-3 compensation network. Type-2 compensation
eliminates R3 and C3.
A shorted high-side MOSFET condition is detected
when SW voltage exceeds ~0.7V while the low-side
MOSFET is fully enhanced. The fault latch is set
immediately upon detection.
These two fault conditions are allowed to set the fault
latch at any time, including during soft-start.
Auto-Restart
After a fault, EN is discharged with 1µA to a 1.1V
threshold before the 800KΩ pull-up is restored. A new
soft-start cycle begins when EN charges above 1.35V.
Depending on the external circuit, the FAN2103 can be
provisioned to remain latched-off or automatically
restart after a fault.
Figure 22. Compensation Network
© 2007 Fairchild Semiconductor Corporation
FAN2103 Rev. 1.0.3
www.fairchildsemi.com
11
During power-saving mode, the output is regulated to a
slightly higher value than its set point, since the current
Table 1. Fault / Restart Provisioning
EN pin
Pull to GND
VCC
Controller / Restart State
OFF (disabled)
pulse is triggered when FB crosses VREF
.
The IC is prevented from switching in the audible band.
If the FB pin has not dropped to VREF within 40µs of the
last pulse, the IC sinks current through the inductor to
initiate a new cycle.
No restart – latched OFF
Immediate restart after fault
New soft-start cycle after:
Open
Cap to GND
Transition back to PWM mode is achieved when a load
transient causes the output voltage to drop 1.5% below
its regulation point.
t
DELAY (msec) = 3.9 • C(nf)
With EN left open, restart is immediate.
If auto-restart is not desired, tie the EN pin to the VCC
pin or drive it with a logic gate to keep the 1µA current
sink from discharging EN to 1.1V.
1.85
PSM to PWM
PWM to PSM
1.84
1.83
1.82
PSM to PWM
1.81
Transition
PWM to PSM
Transition
1.8
1.79
1.78
0
0.25
0.5
0.75
1
1.25
1.5
Figure 25. Power-Saving Mode Regulation
(Using Figure 10 Circuit)
Power-saving mode operation can be disabled by
connecting the PWM# pin to AGND, allowing only PWM
operation. The PWM# pin has a 1µA pull-down. If <0.6V
is detected, power-saving mode operation is disabled.
Figure 24. Fault Latch with Delayed Auto-Restart
PCB Layout
Over-Temperature Protection
FAN2103 incorporates an over-temperature protection
circuit that sets the fault latch when a die temperature of
about 160°C is reached. The IC is allowed to restart
when the die temperature falls below 130°C.
Power Good (PGOOD) Signal
PGOOD is an open-drain output that asserts LOW
when VOUT is out of regulation, as measured at the FB
pin (thresholds are specified in the Electrical
Specifications section). PGOOD does not assert HIGH
until the fault latch is enabled (T1.0).
Power-Saving Mode
Figure 26. Recommended PCB Layout
The FAN2103 maintains high efficiency at light load by
changing to a discontinuous, constant peak current,
power-saving mode (PSM).
The transition to power-saving mode occurs when the load
is <ΔIL/2 for eight consecutive clock cycles.
In power-saving mode, a constant-peak inductor current
(ΔILPSM) is generated each on-cycle. ΔILPSM is nominally
85% larger than PWM-mode inductor ripple (ΔIL).
© 2007 Fairchild Semiconductor Corporation
FAN2103 Rev. 1.0.3
www.fairchildsemi.com
12
Physical Dimensions
2X
TOP VIEW
2X
RECOMMENDED LAND PATTERN
ALL VALUES TYPICAL EXCEPT WHERE NOTED
SIDE VIEW
SEATING
PLANE
A) DIMENSIONS ARE IN MILLIMETERS.
B) DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) DESIGN BASED ON JEDEC MO-220
VARIATION WJHC
E) TERMINALS ARE SYMMETRICAL AROUND THE
X & Y AXIS EXCEPT WHERE DEPOPULATED.
F) DRAWING FILENAME: MKT-MLP25AREV2
BOTTOM VIEW
Figure 27. 5x6mm Molded Leadless Package (MLP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
© 2007 Fairchild Semiconductor Corporation
FAN2103 Rev. 1.0.3
www.fairchildsemi.com
13
© 2007 Fairchild Semiconductor Corporation
FAN2103 Rev. 1.0.3
www.fairchildsemi.com
14
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