FAN21SV04EMPX [FAIRCHILD]
TinyBuck™ 4A, 24V Single-Input Integrated Synchronous Buck Regulator; TinyBuck一体化™ 4A ， 24V单输入集成式同步降压稳压器
| 型号： | FAN21SV04EMPX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | TinyBuck™ 4A, 24V Single-Input Integrated Synchronous Buck Regulator |
| 文件： | 总18页 (文件大小：787K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 2009
FAN21SV04 — TinyBuck™ 4A, 24V Single-Input
Integrated Synchronous Buck Regulator
Features
Description
Single-Supply Operation with 4A Output Current
The FAN21SV04 TinyBuck™ is a highly efficient,
small-footprint, programmable-frequency, 4A,
integrated synchronous buck regulator.
Wide Input Range with Dual Supply: 3.0V to 24V
Wide Output Voltage Range: 0.8V to 80% VIN
Over 94% Peak Efficiency
FAN21SV04 contains both synchronous MOSFETs
and a controller/driver with optimized interconnects in
one package, which enables designers to solve high-
current requirements in a small area with minimal
external components, thereby reducing cost. On-
board internal 5V regulator enables single-supply
operation for input voltages >6.5V.
1% Reference Accuracy Over Temperature
Fully Synchronous Operation with Integrated
Schottky Diode on Low-Side MOSFET Boosts
Efficiency
Single Supply Device for VIN > 6.5V – 24V
The FAN21SV04 can be configured to drive multiple
slave devices OR synchronize to an external system
clock. In slave mode, FAN21SV04 may be set up to
be free-running in the absence of a master clock
signal.
Programmable Frequency Operation (200-
600KHz)
Synchronizable to External Clock with
Master/Slave Provisions
External compensation, programmable switching
frequency, and current-limit features allow for design
optimization and flexibility. High-frequency operation
allows for all-ceramic solutions.
Power-Good Signal
Accepts Ceramic Capacitors on Output
External Compensation for Flexible Design
Starts on Pre-Bias Outputs
Fairchild’s advanced BiCMOS power process,
combined with low-RDS(ON) internal MOSFETs and a
thermally efficient MLP package, provide the ability to
dissipate high power in a small package. Integration
helps minimize critical inductances, making layout
simpler and more efficient compared to discrete
solutions.
Integrated Bootstrap Diode
Programmable Over-Current Protection
Under-Voltage, Over-Voltage, and Thermal-
Shutdown Protections
5x6mm, 25-Pin, 3-Pad MLP Package
Output over-voltage, under-voltage, over-current, and
thermal-shutdown protections help protect the device
from damage during fault conditions. FAN21SV04
prevents pre-biased output discharge during startup
in point-of-load applications.
Applications
Servers & Telecom
Graphics Cards & Displays
Computing Systems
Related Application Notes
AN-8022 — TinyCalc™ Calculator
Set-Top Boxes & Game Consoles
Point-of-Load Regulation
Ordering Information
Operating
Eco
Packing
Part Number
Temperature Range Status
Package
Method
FAN21SV04MPX
FAN21SV04EMPX
-10°C to 85°C
-40°C to 85°C
Green Molded Leadless Package (MLP) 5x6mm Tape and Reel
Green Molded Leadless Package (MLP) 5x6mm Tape and Reel
For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
© 2009 Fairchild Semiconductor Corporation
FAN21SV04 • Rev. 1.0.1
www.fairchildsemi.com
Typical Application Diagram
Figure 1. Typical Application as Master at VIN=6.5V to 24V
Block Diagram
Figure 2. Block Diagram
© 2009 Fairchild Semiconductor Corporation
FAN21SV04 • Rev. 1.0.1
www.fairchildsemi.com
2
Pin Configuration
Figure 3. MLP 5x6mm Pin Configuration (Bottom View)
Pad / Pin Definitions
Pad / Pin
P1, 6-12
P2, 3-5
Name Description
SW
VIN
Switching Node. Junction of high-side and low-side MOSFETs.
Power Conversion Input Voltage. Connect to the main input power source.
Power Ground. Power return and Q2 source.
P3, 21-23
PGND
High-Side Drive BOOT Voltage. Connect through capacitor (CBOOT) to SW. The IC has an
internal synchronous bootstrap diode to recharge the capacitor on this pin to 5V_Reg when
SW is LOW.
1
2
BOOT
VIN_Reg
PGOOD
Regulator Input Voltage. Input voltage to the internal regulator. Connect to input voltage
>6.5V with 10Ω resistor and a 1µF bypass capacitor at the pin (see Figure 10).
Power-Good. An open-drain output that pulls LOW when the voltage on the FB pin is
outside the specified limits. PGOOD does not assert HIGH until the fault latch is enabled
(see Figure 31).
13
ENABLE. Enables operation when pulled to logic HIGH or left open. Toggling EN resets the
regulator after a latched-fault condition. This input has an internal pull-up. When a latched
fault occurs, EN is discharged by a current sink.
14
15
EN
5V Regulator Output. Internal regulator output that provides power for the IC’s logic and
analog circuitry. This pin should be connected to AGND through a >2.2µf X5R/X7R
capacitor.
5V_Reg
Analog Ground. The signal ground for the IC. All internal control voltages are referred to
this pin. Tie this pin to the ground island/plane through the lowest impedance connection.
16
17
AGND
ILIM
Current Limit. A resistor (RILIM) from this pin to AGND can be used to program the current-
limit trip threshold lower than the internal default setting.
Switching Frequency and Master/Slave Set. Connecting a resistor (RT) to AGND sets the
switching frequency and configures the CLK pin as an output (master). Tying this pin to
5V_Reg through a resistor configures the CLK signal as an input (slave) and establishes
the free-running switching frequency.
18
RT
19
20
FB
Output Voltage Feedback. Connect through a resistor divider to the output voltage.
Compensation. Error amplifier output. Connect the external compensation network
between this pin and FB.
COMP
Clock. Bi-directional signal pin, depending on master/slave configuration. When configured
as a master, this pin represents the clock output that connects directly to the slave(s) for
synchronizing with 180° phase shift.
24
25
CLK
Ramp Amplitude. A resistor (RRAMP) connected from this pin to VIN sets the internal ramp
amplitude and also provides voltage feedforward functionality.
RAMP
© 2009 Fairchild Semiconductor Corporation
FAN21SV04 • Rev. 1.0.1
www.fairchildsemi.com
3
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only.
Parameter
Conditions
Min.
Max.
28
Units
VIN, VIN_Reg to AGND AGND=PGND
V
V
V
V
5V_Reg to AGND
BOOT to PGND
BOOT to SW
AGND=PGND
6
35
-0.5
-0.5
-5
6.0
24.0
30
Continuous
SW to PGND
All other pins
V
V
Transient (t < 20ns, f < 600KHz)
-0.3
6.0
Human Body Model,
JESD22-A114
1.5
2.5
Electrostatic Discharge
Protection Level
ESD
kV
Charged Device Model,
JESD22-C101
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Switching Frequency
Conditions
Min.
200
3.0
Typ.
Max Units
fSW
500
600
24.0
24.0
+85
KHz
VIN to PGND
VIN,
VIN_Reg
Supply Voltage for Power and Bias
V
VIN_Reg to AGND
FAN21SV04MPX
FAN21SV04EMPX
6.5
-10
TA
TJ
Ambient Temperature
Junction Temperature
°C
°C
-40
+85
+125
Thermal Information
Symbol
Parameter
Min.
Typ.
Max.
+150
+300
Units
°C
TSTG
TL
Storage Temperature
-65
Lead Soldering Temperature, 30 Seconds
Thermal Resistance: Junction-to-Case
°C
P1 (Q2)
P2 (Q1)
P3
4
7
°C/W
θJC
4
Thermal Resistance: Junction-to-Mounting Surface(1)
Total Power Dissipation in the package, TA=25°C(1)
35
°C/W
W
θJ-PCB
PD
2.8
Note:
1. Typical thermal resistance when mounted on a four-layer, two-ounce PCB, as shown in Figure 38. Actual results
are dependent upon mounting method and surface related to the design.
© 2009 Fairchild Semiconductor Corporation
FAN21SV04 • Rev. 1.0.1
www.fairchildsemi.com
4
Electrical Characteristics
Recommended operating conditions and using the circuit shown in Figure 1, with VIN, VIN_Reg=12V, unless
otherwise noted.
Parameter
Power Supplies
Conditions
Min.
Typ.
Max. Units
Operating Current
(VIN+VIN_Reg)
VIN=12V, 5V_Reg Open, CLK Open,
22
30
mA
mA
f
SW=500KHz, No Load
EN=High, 5V_Reg Open, CLK Open,
SW=500KHz
VIN_Reg Operating Current
11
4
f
VIN_Reg Quiescent Current
VIN_Reg Standby Current
EN=High, FB=0.9V
EN=0, VIN=12V
5
1
mA
mA
Internal VCC Regulator, No Load,
6.5V<VIN_Reg<24V
5V_Reg Output Voltage
5V_Reg Max. Current Load
VIN_Reg UVLO Threshold
Reference
4.7
5.0
5.6
5.3
V
VIN_Reg=12V
5
6.3
5
mA
V
Rising VIN, VIN=VIN_Reg
Falling VIN, VIN=VIN_Reg
V
Reference Voltage measured
at FB (See Figure 4 for
Temperature Coefficient)
FAN21SV04MPX, TA=25°C
FAN21SV04EMPX, TA=25°C
794
795
800
800
806
805
mV
Oscillator
255
540
300
600
345
660
RT=50kΩ to GND (Master Mode)
RT=24kΩ to GND (Master Mode)
Frequency
KHz
%
Frequency in Slave Mode
Compared to Master Mode
Minimum On Time (2)
RT=24 kΩ to 50kΩ to 5V_Reg
(Slave Mode)
-15
+15
40
80
65
85
ns
%
Duty Cycle
VIN=6.5V, fSW=600KHz
Ramp Amplitude,
Peak–to-Peak(2)
Minimum Off Time (2)
0.5
V
VIN=16V, 1.8VOUT, RT=30kΩ, RRAMP=200kΩ
100
150
ns
Synchronization
CLK Output Pulse Width
CLK Output Sink Current
CLK Output Source Current
CLK Input Pulse Width
CLK Input Source Current
CLK Input Threshold, Rising
Soft-Start
Master (RT to GND)
Master, VCLK=0.4V
Master, VCLK=2V
Slave: VCLK > 2V
Slave: VCLK=1V
Slave
70
85
100
0.35
-2.0
ns
mA
mA
ns
0.25
-2.5
50
-230
1.73
-200
1.83
-170
1.93
µA
V
VOUT to Regulation (T0.8
)
2.5
3.1
ms
ms
Frequency=500KHz
Fault Enable/SSOK (T1.0
Error Amplifier
DC Gain (2)
Gain Bandwidth Product(2)
Output Voltage Swing (VCOMP
Output Current, Sourcing
Output Current, Sinking
FB Bias Current
)
80
12
85
15
dB
MHz
V
VIN_Reg > 6.5V
)
0.4
1.5
0.8
-850
4.0
2.5
5V_Reg=5V, VCOMP=2.2V
5V_Reg=5V, VCOMP=1.2V
VFB=0.8V, TA=25°C
2.2
1.2
mA
mA
nA
1.5
-650
-450
Note:
2. Specifications guaranteed by design and characterization; not production tested.
© 2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN21SV04 • Rev. 1.0.1
5
Electrical Characteristics (Continued)
Recommended operating conditions and using the circuit shown in Figure 1 with VIN, VIN_Reg=12V, unless
otherwise noted.
Parameter
Control Functions
EN Threshold, Rising
EN Hysteresis
Conditions
Min.
Typ.
Max. Units
1.35
250
800
1
2.00
V
mV
KΩ
µA
KΩ
EN Pull-Up Resistance
EN Discharge Current
FB OK Drive Resistance
VIN_Reg >6.5V
Auto-Restart Mode, VIN_Reg>6.5V
800
-11.0
+10.0
1000
-8.0
+13.5
0.4
FB < VREF, 2 Consecutive Clock Cycles(3)
FB > VREF, 2 Consecutive Clock Cycles(3)
IOUT < 2mA
-14.0
+7.0
PGOOD Low Threshold
%VREF
PGOOD Low Voltage
V
PGOOD Leakage Current
Protection and Shutdown
VPGOOD=5V
0.2
1.0
µA
RILIM open, fSW=500KHz, VOUT=1.8V,
Current Limit
5.5
-11
6.5
7.5
-9
A
R
RAMP=200kΩ, 16 Consecutive Clock
Cycles(3)
ILIM Current
VIN_Reg > 6.5V, TA=25°C
-10
+155
+30
115
73
µA
°C
Over-Temperature Shutdown
Over-Temperature Hysteresis
Over-Voltage Threshold
Under-Voltage Shutdown
Fault-Discharge Threshold
Fault-Discharge Hysteresis
Note:
Internal Temperature
°C
2 Consecutive Clock Cycles(3)
16 Consecutive Clock Cycles(3)
Measured at FB pin
110
68
120
78
%VOUT
%VOUT
mV
250
250
Measured at FB pin (VFB ~500mV)
mV
3. Delay times are not tested in production. Guaranteed by design.
© 2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN21SV04 • Rev. 1.0.1
6
Typical Characteristics
VIN=12V, VCC=5V, TA=25°C, unless otherwise specified.
1.010
1.005
1.000
0.995
0.990
1.20
1.10
1.00
0.90
0.80
-50
0
50
100
150
-50
0
50
100
150
Temperature (oC)
Temperature (oC)
Figure 4. Reference Voltage (VFB) vs. Temperature, Figure 5. Reference Bias Current (IFB) vs. Temperature,
Normalized
Normalized
1500
1200
900
600
300
0
1.02
1.01
1.00
0.99
0.98
600KHz
300KHz
-50
0
50
100
150
0
20
40
60
80
100
120
140
Temperature (oC)
RT (K )
Ω
Figure 6. Frequency vs. RT (Master)
Figure 7. Frequency vs. Temperature, Normalized
1.04
1.02
1.00
0.98
0.96
1.60
1.40
1.20
1.00
0.80
0.60
Q1 ~0.32 %/oC
Q2 ~0.35 %/oC
-50
0
50
100
150
-50
0
50
100
150
Temperature (oC)
Temperature (oC)
Figure 8. RDS vs. Temperature, Normalized
(5V_Reg=VGS=5V)
Figure 9. ILIM Current (IILIM) vs. Temperature,
Normalized
© 2009 Fairchild Semiconductor Corporation
FAN21SV04 • Rev. 1.0.1
www.fairchildsemi.com
7
Application Circuit
FAN21SV04
Figure 10. Single-Supply Application Circuit: 1.8VOUT, 500KHz, Master, 8V – 20V Input
FAN21SV04
Figure 11. Single -Supply Application Circuit: 1.2 VOUT, 500KHz, Master 8V – 20V Input
© 2009 Fairchild Semiconductor Corporation
FAN21SV04 • Rev. 1.0.1
www.fairchildsemi.com
8
Typical Performance Characteristics
Typical operating characteristics using the Figure 10 circuit; VIN=12V, VCC=5V, TA=25°C, unless otherwise specified.
95
3.3V Eff 8-20V 500kHz
95
1.8V_Eff 8-20V_500kHz
90
90
85
85
8Vin
12Vin
80
80
8V
16Vin
12V
20Vin
75
70
75
70
16V
20V
0
0.5
1
1.5
2
2.5
3
3.5
4
0
0.5
1
1.5
2
2.5
3
3.5
4
Load(A)
Load(A)
Figure 12. 1.8 VOUT Efficiency Over VIN vs. Load
Figure 13. 3.3 VOUT Efficiency, 500KHz(4)
95
3.3V_Eff 8-20V_300kHz
1.8V_Eff 8-20V_300kHz
95
90
85
80
75
70
90
85
8V
8V
80
75
70
12V
16V
20V
12V
16V
20V
0
0.5
1
1.5
2
2.5
3
3.5
4
0
0.5
1
1.5
2
2.5
3
3.5
4
Load(A)
Load(A)
Figure 14. 1.8 VOUT Efficiency, 300KHz(4)
Figure 15. 3.3 VOUT Efficiency, 300KHz(4)
95
1.2V_Eff 8-20V_500kHz
95
90
85
80
75
70
90
85
80
75
70
5V_Eff 8-20V_300kHz
8Vin
12Vin
16Vin
20Vin
8V
12V
16V
20V
0
0.5
1
1.5
2
2.5
3
3.5
4
0
0.5
1
1.5
2
2.5
3
3.5
4
Load(A)
Load (A)
Figure 16. 1.2 VOUT Efficiency, 500KHz (Figure 11)
Note:
Figure 17. 5 VOUT Efficiency, 300KHz(4)
4. Circuit values for this configuration change in Figure 10.
© 2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN21SV04 • Rev. 1.0.1
9
Typical Performance Characteristics (Continued)
Typical operating characteristics using the Figure 10 circuit; VIN=12V, VCC=5V, TA=25°C, unless otherwise specified.
0.10
0.15
Line Regulation
Load Regulation
0.08
0.05
No load
0.1
0.05
0
0.5A Load
12V
16V
0.03
0.00
-0.03
-0.05
-0.08
-0.10
-0.05
-0.1
-0.15
0
0.5
1
1.5
2
2.5
3
3.5
4
0
5
10
15
20
25
Input Voltage (V)
Load(A)
Figure 18. 1.8 VOUT Line Regulation
Figure 19. 1.8 VOUT Load Regulation
70
70
60
50
40
30
20
10
0
Peak Case Tempr over Mosfet Location
@Room Tempr - 3.3V Output, 500kHz
60
50
40
30
20
10
0
Peak Case Tempr over Mosfet Location
@Room Tempr - 5V Output, 300kHz
12V_HS
12V_LS
24V_HS
24V_LS
12V_HS
12V_LS
0
0.5
1
1.5
2
2.5
3
3.5
4
0
0.5
1
1.5
2
2.5
3
3.5
4
Load(A)
Load(A)
Figure 20. Peak MOSFET Temperatures
Figure 21. Peak Case Temperature Over MOSFET
Locations 5V Output (300KHz)
3.3V Output, 12V and 24V Input (500KHz)(5)
95
90
85
80
75
70
Recommended FAN21SV04 Safe Operating Area curves for 70 Deg
Temperature rise VIN = 20V, Natural Convection.
1.8V_Eff 12V Input
6
5
4
3
300kHz
400kHz
500kHz
600kHz
2
300KHz
500KHz
1
600Khz
0
0
2
4
6
8
10
12
14
0
0.5
1
1.5
2
2.5
3
3.5
4
Output Voltage (Volts)
Load(A)
Figure 23. Typical Output Operating Area Based on
Thermal Limitations
Figure 22. 1.8 VOUT Efficiency Over fSW
Note:
5. Circuit values for this configuration change in Figure 10.
© 2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN21SV04 • Rev. 1.0.1
10
Typical Performance Characteristics (Continued)
Typical operating characteristics using the Figure 10 circuit. VIN=12V unless otherwise specified.
VOUT, 1V/div
VOUT, 100mv/div
EN, 1V/div
CLK, 5V/div
IOUT, 2A/div
PGOOD, 5V/div
Figure 24. CLK and VOUT at Startup
Figure 25. Transient Response, 2-4A Load
VOUT, 1V/div
EN, 2V/div
SW, 10V/div
SW, 10V/div
Figure 26. Startup on Pre-Bias
Figure 27. Restart on Fault
CLK, 5V/div
VOUT, 1V/div
SW, 5V/div
CLK, 5V/div
EN, 5V/div
PGOOD, 5V/div
Figure 29. Slave (500KHz Free-Run to 600KHz
Synchronization)
Figure 28. Shutdown, 1A Load
© 2009 Fairchild Semiconductor Corporation
FAN21SV04 • Rev. 1.0.1
www.fairchildsemi.com
11
Circuit Operation
PWM Generation
Internal Regulator
Refer to Figure 2 for the PWM control mechanism.
FAN21SV04 uses the summing-mode method of control
to generate the PWM pulses. An amplified current-
sense signal is summed with an internally generated
ramp and the combined signal is compared with the
output of the error amplifier to generate the pulse width
to drive the high-side MOSFET. Sensed current from
the previous cycle is used to modulate the output of the
summing block. The output of the summing block is
also compared against a voltage threshold set by the
FAN21SV04 facilitates single-supply operation for input
voltages >6.5V. At startup, the output of the internal
regulator tracks the input voltage and comes into
regulation (5V) when VIN_Reg exceeds the UVLO
threshold. The EN pin is released at the same time. The
output voltage of the internal regulator (5V_Reg) is set
to 5V. The internal regulator supplies power to all the
control circuits including the drivers.
For applications with VIN<6.5V, FAN21SV04 can be
used if VIN_Reg is provided with a separate low-power
source >6.5V. VIN_Reg supply should come up after
VIN during dual-supply operation. The VIN_Reg pin
should always be decoupled with at least a 10Ω resistor
and a 1µF ceramic capacitor (see Figure 10, Figure 11).
RLIM resistor to limit the inductor current on a cycle-by-
cycle basis. RRAMP resistor helps set the charging
current for the internal ramp and provides input voltage
feed-forward function. The controller facilitates external
compensation for enhanced flexibility.
Since 5V_Reg is used to drive the internal MOSFET
gates, high peak currents are present on the 5V_Reg
pin. Connect a >2.2µf X5R or X7R decoupling capacitor
between the 5V_Reg pin and AGND. For VIN>20V
operation, use a 3.3Ω resistor in series with the boot
capacitor to reduce noise into the regulator.
Initialization
Once VIN_Reg voltage exceeds the UVLO threshold
and EN is HIGH, the IC checks for a shorted FB pin
before releasing the internal soft-start ramp (SS).
If the parallel combination of R1 and RBIAS is ≤ 1kΩ, the
internal SS ramp is not released and the regulator does
not start.
In addition to supplying power for the control circuits
internally, 5V_Reg output can be used as a reference
voltage for other applications requiring low noise
reference voltage. 5V_Reg is capable of sourcing up to
5mA of output current.
Enable
FAN21SV04 has an internal pull-up to the enable (EN)
pin so that the IC is enabled once VIN_Reg exceeds the
UVLO threshold. Connecting a small capacitor across
EN and AGND delays the rate of voltage rise on the EN
pin. The EN pin also serves for the restart whenever a
fault occurs (refer to the Auto-Restart section). If the
regulator is enabled externally, the external EN signal
should go HIGH only after 5V_Reg is established. For
applications where such sequencing is required,
FAN21SV04 can be enabled (after the VCC comes up)
with external control, as shown in Figure 30.
When EN is pulled LOW externally, 5V_Reg output is
still present, but the IC is in standby mode with no
switching.
Soft-Start
FAN21SV04 uses an internal digital soft-start circuit to
slowly ramp up the output voltage and limit inrush
current during startup. When 5V_Reg is in regulation
and EN is HIGH, the circuit releases SS and enables
the PWM regulator. Soft-start time is a function of the
switching frequency (number of clock cycles).
If auto-restart is not desired, tie the EN pin HIGH with a
logic gate to keep the 1µA current sink from discharging
EN to 1.1V. Figure 32 shows one method to pull up EN
to VCC for a latch configuration.
Once internal SS ramp has charged to 0.8V (T0.8), the
output voltage is in regulation. Until SS ramp reaches
1.0V (T1.0), only the over-current-protection circuit is
active during soft-start and all other output protections
are inhibited.
In dual-supply operation mode, it is necessary to apply
VIN before VIN_Reg reaches its UVLO threshold to
avoid skipping the soft-start cycle.
VIN_Reg UVLO or toggling the EN pin discharges the
SS and resets the IC.
Figure 30. Enabling with External Control
© 2009 Fairchild Semiconductor Corporation
FAN21SV04 • Rev. 1.0.1
www.fairchildsemi.com
12
Over-Temperature Protection
The chip incorporates an over-temperature protection
circuit that sets the fault latch when a die temperature of
about 155°C is reached. The IC is allowed to restart
when the die temperature falls below 125°C.
Auto-Restart
After a fault, the EN pin is discharged with 1µA current
pull-down to a 1.1V threshold before the internal 800kΩ
pull-up is restored. A new soft-start cycle begins when
EN charges above 1.35V.
Depending on the external circuit, the FAN21SV04 can
be configured to remain latched off or automatically
restart after a fault, as listed in Table 1.
Table 1. Fault / Restart Configurations
EN Pin
Controller / Restart State
Pull to GND
OFF (Disabled)
Connected to
5V_Reg with
100KΩ
No Restart – Latched OFF
Open
Immediate Restart After Fault
New Soft-Start Cycle After EN is
HIGH (Auto Restart Mode)
Cap to GND
With EN left open, restart is immediate.
Figure 31. Typical Soft-Start Timing Diagram
If auto-restart is not desired, tie the EN pin HIGH with a
logic gate to keep the 1µA current sink from discharging
EN to 1.1V. Figure 32 shows one method to pull up EN
to VCC for a latch configuration.
Startup on Pre-Bias
The regulator does not allow the low-side MOSFET to
operate in full synchronous mode until SS reaches 95%
of VREF (~0.76V). This enables the regulator to startup
on a pre-biased output and ensures that output is not
discharged during the soft-start cycle.
Protections
The converter output is monitored and protected
against extreme overload, short-circuit, over-voltage,
and under-voltage conditions.
Under-Voltage Protection
If FB remains below the under-voltage threshold for 16
consecutive clock cycles, the fault latch is set and the
converter shuts down. This protection is not active until
the internal SS ramp reaches 1.0V during soft-start.
Figure 32. Enable Control with Latch Option
Power Good (PGOOD) Signal
PGOOD is an open-drain output that asserts LOW
when VOUT is out of regulation, as measured at the FB
pin. The thresholds are specified in the Electrical
Specifications section. PGOOD does not assert HIGH
until soft start is complete (T1.0) (see Figure 31).
Over-Voltage Protection
If FB exceeds 115% • VREF for two consecutive clock
cycles, the fault latch is set and shutdown occurs.
A shorted high-side MOSFET condition is detected
when SW voltage exceeds ~0.7V while the low-side
MOSFET is fully enhanced. The fault latch is set
immediately upon detection.
The OV/UV fault conditions are not allowed to set the
fault latch during soft-start. They are active only after
T1.0 (see Figure 31).
© 2009 Fairchild Semiconductor Corporation
FAN21SV04 • Rev. 1.0.1
www.fairchildsemi.com
13
Application Information
5V_Reg Output
The 5V_Reg pin is the output of the internal regulator
that supplies all power to the control circuit. It is
important to keep this pin decoupled to AGND with a
>2.2µf X5R or X7R decoupling capacitor. In addition, for
operation with VIN>20V, add a 3.3Ω resistor in series
with the boot capacitor to reduce the switching noise
into the regulator.
transient response use a higher ripple-current setting
while regulator designs that require higher efficiency
keep ripple current on the low side and operate at a
lower switching frequency. The inductor value is
calculated by the following formula:
VOUT
VOUT • (1-
)
V
(3)
IN
L =
ΔIL • f
where f is the switching frequency.
Setting the Output Voltage
The output voltage of the regulator can be set from 0.8V
to ~80% of VIN by an external resistor divider (R1 and
RBIAS in Figure 1). For output voltages >3.3V, output
current rating may need to be de-rated depending on
the ambient temperature, power dissipated in the
package, and the PCB layout (refer to Thermal
Information table on page 4, Figure 20, Figure 21, and
Figure 23).
Setting the Ramp Resistor Value
RRAMP resistor plays a critical role by providing charging
current to the internal ramp capacitor and also serving
as a means to provide input voltage feedforward.
RRAMP is calculated by the following formula:
(VIN − 1.8) • VOUT
RRAMP(KΩ)
=
− 2
(4)
(30.5 − 4.5 • IOUT ) • V • f • 10−6
The internal reference is set to 0.8V with 650nA
sourced from the FB pin to ensure that the regulator
does not start if the pin is left open.
IN
where frequency (f) is expressed in KHz.
For wide input operation, first calculate RRAMP for the
minimum and maximum input voltage conditions and
use larger of the two values calculated.
The external resistor divider is calculated using:
VOUT − 0.8V
0.8V
=
+ 650nA
(1)
RBIAS
R1
In all applications, current through the RRAMP pin must
be greater than 10µA from the equation below for
proper operation:
Connect RBIAS between FB and AGND.
If R1 is open (see Figure 1), the output voltage is not
regulated and a latched fault occurs after the SS is
complete (T1.0).
VIN −1.8
RRAMP + 2
≥ 10μA
(5)
If the parallel combination of R1 and RBIAS is ≤ 1KΩ, the
internal SS ramp is not released and the regulator does
not start.
If the calculated RRAMP values in Equation (4) result in a
current less than 10µA, use the RRAMP value that
satisfies Equation (5). In applications with large Input
ripple voltage, the RRAMP resistor should be adequately
decoupled from the input voltage to minimize ripple on
the ramp pin.
Setting the Switching Frequency
Switching frequency is determined by a resistor, RT,
connected between the RT pin and AGND (Master
Mode) or 5V_Reg (Slave Mode):
Setting the Current Limit
There are two levels of current-limit thresholds in
FAN21SV04. The first level of protection is through an
internal default limit set at the factory to provide cycle-
by-cycle current limit and prevent output current
beyond normal levels. The second level of protection
where RT is expressed in kΩ:
(106 /f )−135
(2)
RT
=
(KΩ)
65
is set at the ILIM pin by connecting a resistor (RILIM
)
where frequency (f) is expressed in KHz.
between ILIM and AGND. Current-limit protection is
enabled whenever the lower of the two thresholds is
reached (see Figure 33). The FAN21SV04 uses its
internal low-side MOSFET as the current-sensing
element. The current-limit threshold voltage (VILIM) is
compared to the voltage drop across the low-side
MOSFET sampled at the end of each PWM off-time
cycle. The internal default threshold (ILIM open) is
temperature compensated.
In Slave Mode, the switching frequency is about 10%
slower for the same RT. The regulator does not start if
RT is open in Master Mode.
Calculating the Inductor Value
Typically the inductor value is chosen based on ripple
current (ΔIL), which is chosen between 10 to 35% of the
maximum DC load. Regulator designs that require fast
© 2009 Fairchild Semiconductor Corporation
FAN21SV04 • Rev. 1.0.1
www.fairchildsemi.com
14
Since the FAN21SV04 employs summing current-mode
architecture, Type-2 compensation can be used for
many applications. For applications that require wide
loop bandwidth and/or use very low-ESR output
capacitors, Type-3 compensation may be required.
RRAMP provides feedforward compensation for changes
in VIN. With a fixed RRAMP value, the modulator gain
increases as VIN is reduced, which can make it difficult
to compensate the loop. For low-input-voltage-range
designs (3V to 8V), RRAMP and the compensation
component values are different as compared to designs
with VIN between 8V and 24V.
Figure 33. ILIM Network
Master / Slave Configuration
The ILIM pin can source a 10µA current that can be
used to establish a lower, temperature-dependent,
current-limit threshold by connecting an external
resistor (RILIM) to AGND. RILIM can be approximated with
the equation:
When first enabled, the IC determines if it is configured
as a master or slave for synchronization, depending on
how RT is connected.
Table 2. Master / Slave Configuration
(VIN −1.8)• VOUT •3.33•106
RILIM(KΩ) = 95+15.1•IOUT
+
(6)
RT to:
GND
Master / Slave
Master
CLK Pin
Output
Input
(RRAMP + 2)• VIN •f
where:
5V_Reg
Slave, free-running
IOUT = Full load current in Amps;
VOUT = Set output voltage;
VIN = Input voltage;
Slaves free-run in the absence of an external clock
signal input when RT is connected to 5V_Reg, allowing
regulation to be maintained. It is not recommended to
leave RT open when running in Slave Mode to avoid
noise pick up on the clock pin.
RRAMP = Ramp resistor used in KΩ; and
f
= Selected switching frequency in KHz.
After 16 consecutive pulse-by-pulse current-limit cycles,
the fault latch is set and the regulator shuts down. Cycling
VIN_Reg or EN restores operation after a normal soft-
start cycle (refer to the Auto-Restart section).
Slave free-running frequency should be set at least
25% lower than the incoming synchronizing pulse
frequency. Maximum synchronizing clock frequency is
recommended to be below 600KHz.
The over-current protection fault latch is active during
the soft-start cycle. Use a 1% resistor for RILIM. For a
given RRAMP and RILIM setting, the current-limit point
varies slightly in an inverse relationship to VIN. If RILIM is
not connected, the IC uses the internal default current-
limit threshold.
Synchronization
The synchronization method employed by the
FAN21SV04 also provides the following features for
maximum flexibility.
Loop Compensation
Synchronization to an external system clock
The control loop is compensated using a feedback
network around the error amplifier. Figure 34 shows a
complete Type-3 compensation network. Type-2
compensation eliminates R3 and C3.
Multiple FAN21SV04s can be synchronized to a
single master or system clock
Independently programmable phase adjustment for
one or multiple slaves
Free-running capability in the absence of system
clock or, if the master is disabled/faulted, the
slaves can continue to regulate at a lower
frequency
COMP
C2
C1
VREF
The FAN21SV04 master outputs an 85ns-wide clock
(CLK) signal, delayed 180o from its leading PWM edge.
This feature allows out-of-phase operation for the slaves,
thereby reducing the input capacitance requirements
when more than one converter is operating on the same
input supply. The leading SW-node edge is delayed
~40ns from the rising PWM signal.
R2
R1
FB
VOUT
R3
R3
RBIAS
C3
Figure 34. Compensation Network
On a slave, synchronization is rising-edge triggered.
The CLK input pin has a 1.8V threshold and a 200µA
current source pull-up.
© 2009 Fairchild Semiconductor Corporation
FAN21SV04 • Rev. 1.0.1
www.fairchildsemi.com
15
In Master Mode, the clock signals go out after power-
good signal asserts HIGH. Likewise, in Slave Mode,
synchronization to an external clock signal occurs after
the power-good signal goes HIGH. Until then, the
converter operates in free-run mode.
PCB Layout
Good PCB layout and careful attention to temperature
rise is essential for reliable operation of the regulator.
Four-layer PCB with two-ounce copper on the top and
bottom side and thermal vias connecting the layers is
recommended. Keep power traces wide and short to
minimize losses and ringing. Do not connect AGND to
PGND below the IC. Connect AGND pin to PGND at the
output OR to the PGND plane.
Figure 35. Synchronization Timing Diagram
VIN
SW
PGND
PGND
VOUT
Figure 36. Slave-CLK-Input Block Diagram
Figure 38. Recommended PCB Layout
One or more slaves can be connected directly to a
master or system clock to achieve a 180o phase shift.
Figure 37. Slaves with 180o Phase Shift
Since the synchronizing circuit utilizes a narrow reset
pulse, the actual phase delay is slightly more than 180o.
The FAN21SV04 is not intended for use in single-
output, multi-phase regulator applications.
© 2009 Fairchild Semiconductor Corporation
FAN21SV04 • Rev. 1.0.1
www.fairchildsemi.com
16
Physical Dimensions
2X
TOP VIEW
2X
RECOMMENDED LAND PATTERN
ALL VALUES TYPICAL EXCEPT WHERE NOTED
SIDE VIEW
SEATING
PLANE
OPTIONAL LEAD DESIGN
(LEADS# 1, 24 & 25 ONLY)
SCALE: 1.5X
A) DIMENSIONS ARE IN MILLIMETERS.
B) DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994
BOTTOM VIEW
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) DESIGN BASED ON JEDEC MO-220
VARIATION WJHC
E) TERMINALS ARE SYMMETRICAL AROUND THE
X & Y AXIS EXCEPT WHERE DEPOPULATED.
F) DRAWING FILENAME: MKT-MLP25AREV3
Figure 39. 5x6mm Molded Leadless Package (MLP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2009 Fairchild Semiconductor Corporation
FAN21SV04 • Rev. 1.0.1
www.fairchildsemi.com
17
© 2009 Fairchild Semiconductor Corporation
FAN21SV04 • Rev. 1.0.1
www.fairchildsemi.com
18
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