FAN21SV06MPX [ONSEMI]
-6A，24V 单输入，集成式同步降压稳压器;
| 型号： | FAN21SV06MPX |
| 厂家： | 
ONSEMI |
| 描述： | -6A，24V 单输入，集成式同步降压稳压器 稳压器 |
| 文件： | 总17页 (文件大小：1261K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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FAN21SV06 — TinyBuck™
6 A, 24V Single-Input Integrated Synchronous Buck
Regulator with Synchronization Capability
Description
Features
The FAN210SV06 TinyBuckTM is a highly efficient,
small-footprint, programmable-frequency, 6 A integrated
synchronous buck regulator.
.
.
.
Single-Supply Operation with 6 A Output Current
Over 94% Efficiency
Fully Synchronous Operation with Integrated
Schottky Diode on Low-Side MOSFET Boosts
Efficiency
FAN21SV06 contains both synchronous MOSFETs and
a controller/driver with optimized interconnects in one
package, which enables designers to solve high-current
requirements in a small area with minimal external
components, thereby saving cost. On-board internal 5 V
regulator enables single-supply operation for input
voltages >6.5 V.
.
.
.
Single Supply Device for VIN > 6.5 V – 24 V
Programmable Frequency Operation (200-600 KHz)
Externally Synchronizable Clock with Master/Slave
Provisions
The FAN21SV06 can be configured to drive multiple
slave devices OR synchronize to an external system
clock. In slave mode, FAN21SV06 may be set up to be
free-running in the absence of a master clock signal.
.
.
.
.
.
.
.
.
.
Wide Input Range with Dual Supply: 3.0 V to 24 V
Output Voltage Range: 0.8 V to 80%VIN
Power-Good Signal
External compensation, programmable switching
frequency, and current-limit features allow for design
optimization and flexibility. High-frequency operation
allows for all ceramic solutions.
Accepts Ceramic Capacitors on Output
External Compensation for Flexible Design
Starts Up on Pre-Bias Outputs
Fairchild’s advanced BiCMOS power process combined
with low-RDS(ON) internal MOSFETs and a thermally
efficient MLP package provide the ability to dissipate
high power in a small package. Integration helps to
minimize critical inductances making layout simpler and
more efficient compared to discrete solutions.
Integrated Bootstrap Diode
Programmable Over-Current Protection
Under-Voltage, Over-Voltage, and Thermal-
Shutdown Protections
.
5 x 6 mm, 25-pin, 3-pad MLP
Output over-voltage, under-voltage, over-current and
thermal-shutdown protections help protect the device
from damage during fault conditions. FAN21SV06
prevents pre-biased output discharge during startup in
point-of-load applications.
Applications
.
.
.
.
.
Servers & Telecom
Graphics Cards & Displays
High-End Computing Systems
Set-Top Boxes & Game Consoles
Point-of-Load Regulation
Ordering Information
Operating
Packing
Part Number
FAN21SV06MPX
FAN21SV06EMPX
Temperature Range
Package
Method
-10°C to 85°C
Molded Leadless Package (MLP) 5 x 6 mm
Tape and Reel
-40°C to 85°C
© 2006 Semiconductor Components Industries, LLC.
August-2017, Rev. 2
Publication Order Number:
FAN21SV06/D
Typical Application Diagram
IN
VIN
Boot
Diode
CHF
CIN
5V_Reg
BOOT
SW
C4
R5
Q1
Q2
CBOOT
VIN_Reg
OUT
C5
L
COUT
RAMP
PWM
+
DRIVER
Power
Good
RRAMP
PGND
CLK
FB
POWER
MOSFETS
EN
ILIM
RT
Enable
RILIM
R1
RT
R3
C3
AGND
COMP
C1
RBIAS
C2
R2
Figure 1. Typical Application, Master, VIN=6.5 V to 24 V
Block Diagram
VIN_Reg
Reg
5V
BOOT
VIN
Boot
Diode
5V_Reg
ILIM
Current Limit
Comparator
IILIM
Int ref
COMP
FB
CBOOT
Error
Amplifier
R
S
Q
PWM
Comparator
Gate
Drive
Circuit
VOUT
SW
L
SS
VREF
COUT
CLK
Summing
Amplifier
AGND
PGND
OSC
RAMP
GEN
Current
Sense
EN
RAMP
Figure 2. Block Diagram
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2
Pin Configuration
Figure 3. MLP 5 x 6 mm Pin Configuration (Bottom View)
Pad / Pin Definitions
Pad / Pin
P1, 6-12
P2, 3-5
Name
SW
Description
Switching Node. Junction of high-side and low-side MOSFETs.
Power Input Voltage. Supply voltage for the converter.
Power Ground. Power return and Q2 source.
VIN
P3, 21-23
PGND
High-Side Drive BOOT Voltage. Connect through capacitor (CBOOT) to SW. The IC has an
internal synchronous bootstrap diode to recharge the capacitor on this pin to 5 V.
1
2
BOOT
Regulator Input Voltage. Input voltage to the internal regulator. Connect to input voltage
>6.5 V with 1 µF bypass capacitor at the pin.
VIN_Reg
Power-Good. An open-drain output that pulls LOW when the voltage on the FB pin is
outside the limits specified in the electrical specs. PGOOD does not assert HIGH until the
fault latch is enabled.
13
14
15
PGOOD
EN
ENABLE. Enables operation when pulled to logic HIGH or left open. Toggling EN resets the
regulator after a latched-fault condition. This input has an internal pull-up. When a latched
fault occurs, EN is discharged by a current sink.
5V Regulator Output. Internal regulator output that provides power for the IC’s logic and
analog circuitry. This pin should be connected to AGND through a >2.2 µf X5R/X7R
capacitor.
5V_Reg
Analog Ground. The signal ground for the IC. All internal control voltages are referred to
this pin. Tie this pin to the ground island/plane through the lowest impedance connection.
16
17
AGND
ILIM
Current Limit. A resistor (RILIM) from this pin to AGND can be used to program the current-
limit trip threshold lower than the internal default setting.
Oscillator Frequency and Master/Slave Set. Connecting a resistor (RT) to AGND sets the
oscillator frequency and configures the CLK pin as an output (master). Tying this pin to
5 V_Reg through a resistor configures the CLK signal as an input (slave) and establishes
the free-running oscillator frequency.
18
RT
19
20
FB
Output Voltage Feedback. Connect through a resistor divider to the output voltage.
Compensation. Error amplifier output. Connect the external compensation network
between this pin and FB.
COMP
Clock. Bi-directional signal pin, depending on master/slave configuration. When configured
as a master, this pin represents the clock output that connects directly to the slave(s) for
synchronizing with 180° phase shift.
24
25
CLK
Ramp Amplitude. A resistor (RRAMP) connected from this pin to VIN sets the internal ramp
amplitude and also provides voltage feedforward functionality.
RAMP
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3
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Parameter
Conditions
Min.
Max.
Units
VIN, VIN_Reg to
AGND
AGND=PGND
AGND=PGND
28
V
5V_Reg to AGND
BOOT to PGND
BOOT to SW
6
35
V
V
V
V
V
V
-0.5
-0.5
-5
6.0
24.0
30
Continuous
SW to PGND
All other pins
ESD
Transient (t < 20 ns, f < 600 KHz)
-0.3
1.5
2.5
6.0
Human Body Model, JESD22-A114
Charged Device Model, JESD22-C101
kV
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. ON
Semiconductor does not recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Conditions
Min.
200
3.0
Typ.
Max Units
fSW
Switching Frequency
500
600
24.0
24.0
+85
KHz
V
VIN to PGND
VIN,
VIN_Reg
Supply Voltage for Power and Bias
VIN_Reg to AGND
FAN21SV06MX
FAN21SV06EMX
6.5
V
-10
°C
°C
°C
TA
TJ
Ambient Temperature
Junction Temperature
-40
+85
+125
Thermal Information
Symbol
Parameter
Lead Soldering Temperature, 30sec
Thermal Resistance: Junction-to-Case
Min.
Typ.
Max.
Units
°C
TSTG
TL
Storage Temperature
-65
+150
+300
°C
P1 (Q2)
P2 (Q1)
P3
4
7
°C/W
°C/W
°C/W
°C/W
W
θJC
4
35(1)
Thermal Resistance: Junction-to-Mounting Surface(1)
Total Power Dissipation in the package, TA=25°C(1)
θJ-PCB
PD
2.8
Note:
1. Typical thermal resistance when mounted on a four-layer, two-ounce PCB, as shown in Figure 37. Actual results
are dependent upon mounting method and surface related to the design.
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4
Electrical Characteristics
Recommended operating conditions, using the circuit in Figure 1, with VIN, VIN_Reg=12 V, unless otherwise noted.
Parameter
Conditions
Min.
Typ.
Max. Units
Power Supplies
Operating Current
(VIN+VIN_Reg)
VIN=12 V, 5 V_Reg open, CLK open,
22
30
mA
mA
f
SW=500 KHz, No Load
EN=High, 5 V_Reg open, CLK open,
fSW=500 KHz
VIN_Reg Operating Current
11
4
VIN_Reg Quiescent Current
VIN_Reg Standby Current
EN=High, FB=0.9 V
EN=0, VIN=12 V
5
1
mA
mA
V
4.7
5.0
5.3
Internal VCC Regulator, No Load
(6.5 V <VIN_Reg<24 V)
5V_Reg Output Voltage
VIN_Reg=12 V)
5
mA
5V_Reg Max Current Load
Rising VIN, VIN=VIN_Reg
Falling VIN, VIN=VIN_Reg
5.6
6.3
5
V
V
VIN_Reg UVLO Threshold
Reference
Reference Voltage measured
at FB (See Figure 4 for
Temperature Coefficient)
FAN21SV06M, 25°C
FAN21SV06EM, 25°C
794
795
800
800
806
805
mV
mV
Oscillator
255
540
300
600
345
660
KHz
KHz
RT=50 kΩ to GND (Master Mode)
RT=24 kΩ to GND (Master Mode)
Frequency
Frequency in Slave Mode
compared to Master Mode
RT=24 kΩ to 50kΩ to 5 V_Reg
-15
+15
%
(Slave Mode)
Minimum On-Time (2)
40
80
65
85
ns
%
Duty Cycle
VIN=6.5 V, fSW=600 KHz
Ramp Amplitude,
Peak–to-Peak(2)
Minimum Off-Time (2)
0.5
V
16 VIN, 1.8 VOUT, RT=30 kΩ, RRAMP=200 kΩ
100
150
ns
Synchronization
CLK Output Pulse Width
CLK Output Sink Current
CLK Output Source Current
CLK Input Pulse Width
CLK Input Source Current
CLK Input Threshold, Rising
Soft-Start
Master (RT to GND)
Master, VCLK=0.4 V
Master, VCLK=2 V
Slave: VCLK > 2 V
Slave: VCLK=1 V
Slave
70
85
100
0.35
-2.0
ns
mA
mA
ns
0.25
-2.5
50
-230
1.73
-200
1.83
-170
1.93
µA
V
VOUT to Regulation (T0.8
)
2.5
3.1
ms
ms
Frequency=500 KHz
Fault Enable/SSOK (T1.0
Error Amplifier
DC Gain (2)
Gain Bandwidth Product(2)
Output Voltage Swing (VCOMP
Output Current, Sourcing
Output Current, Sinking
FB Bias Current
)
80
12
85
15
dB
MHz
V
VIN_Reg > 6.5 V
)
0.4
1.5
0.8
-850
4.0
2.5
5V_Reg=5 V, VCOMP=2.2 V
5V_Reg=5 V, VCOMP=1.2 V
VFB=0.8 V, 25°C
2.2
1.2
mA
mA
nA
1.5
-650
-450
Note:
2. Specifications guaranteed by design and characterization; not production tested.
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5
Electrical Characteristics (Continued)
Recommended operating conditions using the circuit in Figure 1 with VIN, VIN_Reg=12 V, unless otherwise noted.
Parameter
Control Functions
EN Threshold, Rising
EN Hysteresis
Conditions
Min.
Typ.
Max. Units
1.35
250
-6
2.00
-4
V
mV
EN Pull-Up Current
EN Discharge Current
FB OK Drive Resistance
VIN_Reg >6.5 V
-8
µA
Auto-Restart Mode, VIN_Reg>6.5 V
1
µA
800
-11.0
+10.0
1000
-8.0
KΩ
%VREF
FB < VREF, 2 Consecutive Clock Cycles(3)
FB > VREF, 2 Consecutive Clock Cycles(3)
IOUT < 2 mA
-14.5
+6.5
PGOOD LOW Threshold
+13.5 %VREF
PGOOD Low Voltage
0.4
1.0
V
PGOOD Leakage Current
Protection and Shutdown
VPGOOD=5 V
0.2
9
µA
R
ILIM Open, fsw=500 KHz,, VOUT=1.8 V,
Rramp=200 kΩ, 16 Consecutive Clock
Current Limit
7
11
-9
A
Cycles(3)
ILIM Current
VIN_Reg > 6.5 V, 25°C
-11
-10
155
30
µA
°C
Over-Temperature Shutdown
Over-Temperature Hysteresis
Over-Voltage Threshold
Under-Voltage Shutdown
Fault-Discharge Threshold
Fault-Discharge Hysteresis
Note:
Internal Temperature
°C
2 Consecutive Clock Cycles(3)
16 Consecutive Clock Cycles(3)
Measured at FB pin
110
68
115
73
120
78
%VOUT
%VOUT
mV
250
250
Measured at FB pin (VFB ~50 mV)
mV
3. Delay times are not tested in production. Guaranteed by design.
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6
Typical Characteristics
1.010
1.005
1.000
0.995
0.990
1.20
1.10
1.00
0.90
0.80
-50
0
50
100
150
-50
0
50
100
150
Temperature (oC)
Temperature (oC)
Figure 4. Reference Voltage (VFB) vs. Temperature,
Normalized
Figure 5. Reference Bias Current (IFB) vs.
Temperature, Normalized
1500
1200
900
600
300
0
1.02
1.01
1.00
0.99
0.98
600KHz
300KHz
-50
0
50
100
150
0
20
40
60
80
100
120
140
Temperature (oC)
RT (K )
Ω
Figure 6. Frequency vs. RT (Master)
Figure 7. Frequency vs. Temperature, Normalized
1.04
1.02
1.00
0.98
0.96
1.60
1.40
1.20
1.00
0.80
0.60
Q1 ~0.32 %/oC
Q2 ~0.35 %/oC
-50
0
50
100
150
-50
0
50
100
150
Temperature (oC)
Temperature (oC)
Figure 8. RDS vs. Temperature, Normalized
(5 V_Reg=VGS=5 V)
Figure 9. ILIM Current (IILIM) vs. Temperature,
Normalized
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7
Application Circuit
Figure 10. Single-Supply Application Circuit: 1.8 VOUT, 500 KHz, Master
FAN21SV06
6.5-24 V
3.3-8 VIN
VIN
5V_Reg
PGOOD
+5V
15
2.2u
X5R
10K
100K
2.2
3.3n
3 x 4.7u
X7R
13
24
20
VIN_Reg
2
VOUT
CLK
1.0u
X5R
2.49K
COMP
RAMP
BOOT
62
2.49K
25
1
4.7n
56p
FB
ILIM
EN
19
17
14
18
* Cooper Industries
DR1050-2R2-R
4.7n
0.1u
VOUT
SW
200K
4.7n
2.2u *
RT
1.5
30.1K
4.99K
4 x 22u
X5R
AGND
PGND
390p
16
Figure 11. Dual-Supply Application Circuit: 1.2 VOUT, 600 KHz, Master 3.3 V – 8 V Input
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8
Typical Performance Characteristics
Typical operating characteristics using the circuit shown in Figure 10, unless otherwise specified.
95
95
90
85
80
75
70
3.3V_Eff 8-24V_300Khz
1.8V_Eff 8-24V_300Khz
90
85
80
75
70
8V
8V
12V
16V
20V
24V
12V
16V
20V
24V
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Load (A)
Load (A)
Figure 12. 1.8 VOUT Efficiency Over VIN vs. Load
Figure 13. 3.3 VOUT Efficiency vs. Load
(Circuit Value Changes)
0.2
0.15
0.1
Line Regulation
Load Regulation
No Load
0.5A
0.15
0.1
0.05
0
0.05
0
0
1
2
3
4
5
6
7
-0.05
-0.1
-0.15
-0.2
0
5
10
15
20
25
-0.05
-0.1
12VInput
16VInput
-0.15
-0.2
Load (A)
Input Voltage (V)
Figure 14. 1.8 VOUT Line Regulation
Figure 15. 1.8 VOUT Load Regulation
90
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
20
10
0
Peak CaseTempr over Mosfet Location
@ Room Tempr - 5V Output, 300Khz
Peak CaseTempr over Mosfet Location
@ Room Tempr - 3.3V Output, 500Khz
14V_HS
14V_LS
12Vin_HS
12Vin_LS
24Vin_HS
24Vin_LS
1
2
3
4
5
6
Load (A)
1
2
3
4
5
6
Load (A)
Figure 16. Peak Case Temp over MOSFET Locations
3.3 V Output, 12 V and 24 V Input (500 KHz)
Figure 17. Peak Case Temp. Over MOSFET Locations
5 V Output (300 KHz)
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9
Typical Performance Characteristics (Continued)
Typical operating characteristics using the circuit shown in Figure 10. VIN=12 V, unless otherwise specified.
VOUT
VOUT
EN
CLK
IOUT
PGood
Figure 18. CLK and VOUT at Startup
Figure 19. Transient Response, 3-6 A Load
VOUT
EN
SW
SW
Figure 20. Startup on Pre-Bias
Figure 21. Restart on Fault
VOUT
CLK
SW
CLK
EN
PGood
Figure 23. Slave (500 KHz Free-Run to 600 KHz
Synchronization)
Figure 22. Shutdown, 1 A Load
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10
Typical Performance Characteristics (Continued)
Typical operating characteristics using the circuit shown in Figure 10, unless otherwise specified.
95
90
85
80
75
70
95
90
85
80
75
70
1.8V_Eff 8-24V_600Khz
3.3V_Eff 8-24V_600Khz
8V
8V
12V
16V
20V
24V
12V
16V
20V
24V
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Load (A)
Load (A)
Figure 24. 1.8 VOUT Efficiency 600 KHz
Figure 25. 3.3 VOUT Efficiency 600 KHz
3
2.5
2
5V_PWRLOSS_12-24V_300Khz
95
90
85
80
75
70
5V_Eff12-24V_300Khz
Using DR1050-2R2-R
Inductor from Cooper
Using DR1050-2R2-R
Inductor from Cooper
1.5
1
12V
12V
16V
20V
24V
0.5
0
16V
20V
24V
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Load (A)
Load (A)
Figure 26. 5 VOUT Efficiency 300 KHz
(Circuit Values Change)
Figure 27. Device Power Loss (5 VOUT, 300 KHz)
(Circuit Values Change)
95
7
6
5
4
3
2
1
0
Vout Vs Load Current
Input Voltage = 20V
Temperature rise = 80DegC
1.8V_Eff, 12V Input
90
85
80
75
70
20Vin_500Khz
20Vin_600Khz
300Khz
400Khz
500Khz
600Khz
0
1
2
3
4
5
6
7
8
9
10
11
12
13
0
1
2
3
4
5
6
Vout (V)
Load (A)
Figure 28. 1.8 VOUT Efficiency Over fSW
(Circuit Values Change)
Figure 29. Typical Output Operating Area Based on
Thermal Limitations (Circuit Values Change)
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11
Circuit Operation
PWM Generation
Soft-Start
FAN21SV06 uses an internal digital soft-start circuit to
slowly ramp up the output voltage and limit inrush
current during startup. When 5 V_Reg is in regulation
and EN is high, the circuit releases SS and enables the
PWM regulator. Soft-start time is a function of switching
frequency (number of clock cycles).
Refer to Figure 2 for the PWM control mechanism.
FAN21SV06 uses the summing-mode method of control
to generate the PWM pulses. An amplified current-
sense signal is summed with an internally generated
ramp and the combined signal is compared with the
output of the error amplifier to generate the pulse width
to drive the high-side MOSFET. Sensed current from the
previous cycle is used to modulate the output of the
summing block. The output of the summing block is also
compared against a voltage threshold set by the RLIM
resistor to limit the inductor current on a cycle-by-cycle
basis. The controller facilitates external compensation
for enhanced flexibility.
Once internal SS ramp has charged to 0.8 V (T0.8), the
output voltage is in regulation. Until SS ramp reaches
1.0 V (T1.0), only over-current-protection circuit is active
during soft-start and all other output protections are
inhibited.
In dual-supply operation mode, it is necessary to apply
VIN before VIN_Reg reaches its UVLO threshold to
avoid skipping the soft-start cycle.
Initialization
Once VIN_Reg voltage exceeds the UVLO threshold
and EN is high, the IC checks for an open or shorted FB
pin before releasing the internal soft-start ramp (SS).
If R1 is open (Figure 1), error amplifier output (COMP) is
forced LOW and no pulses are generated. After the SS
ramp times out (T1.0), an under-voltage fault occurs.
If the parallel combination of R1 and RBIAS is ≤ 1 kΩ, the
internal SS ramp is not released and the regulator does
not start.
Internal Regulator
FAN21SV06 facilitates single-supply operation for input
voltages >6.5 V. At startup, the output of the internal
regulator tracks the input voltage and comes into
regulation (5 V) when VIN_Reg exceeds the UVLO
threshold. The EN pin is released at the same time. The
output voltage of the internal regulator (5 V_Reg) is set
to 5 V. The internal regulator supplies power to all the
control circuits including the drivers.
For applications with VIN<6.5 V, FAN21SV06 can be
used if VIN_Reg is provided with a separate low-power
source >6.5 V. VIN_Reg supply should come up after
VIN during dual-supply operation. The VIN_Reg pin
should always be decoupled with at least 1 µF ceramic
capacitor (see Figure 11).
Figure 30. Typical Soft-Start Timing Diagram
Since VCC is used to drive the internal MOSFET gates,
high peak currents are present on the 5V_Reg pin.
Connect a >2.2 µf X5R or X7R decoupling capacitor
between the 5 V_Reg pin and PGND.
VIN_Reg UVLO or toggling the EN pin discharges the
SS and resets the IC.
Startup on Pre-Bias
In addition to supplying power for the control circuits
internally, 5 V_Reg output can be used as a reference
voltage for other applications requiring low noise
reference voltage. 5 V_Reg is capable of sourcing up to
5 mA of output current.
The regulator does not allow the low-side MOSFET to
operate in full synchronous mode until SS reaches 95%
of VREF (~0.76 V). This enables the regulator to startup
on a pre-biased output and ensures that output is not
discharged during the soft-start cycle.
When EN is pulled LOW externally, 5 V_Reg output is
still present but the IC is in standby mode with no
switching.
Protections
The converter output is monitored and protected against
extreme overload, short-circuit, over-voltage, and under-
voltage conditions.
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12
Under-Voltage Protection
If FB remains below the under-voltage threshold for 16
consecutive clock cycles, the fault latch is set and the
converter shuts down. This fault is prevented from
setting the fault latch during soft-start.
Over-Voltage Protection
If FB exceeds 115% • VREF for two consecutive clock
cycles, the fault latch is set and shutdown occurs.
Figure 31. Enable Control with Latch Option
A shorted high-side MOSFET condition is detected
when SW voltage exceeds ~0.7 V while the low-side
MOSFET is fully enhanced. The fault latch is set
immediately upon detection.
Power Good (PGOOD) Signal
PGOOD is an open-drain output that asserts LOW when
VOUT is out of regulation, as measured at the FB pin.
The thresholds are specified in the Electrical
Specifications section. PGOOD does not assert HIGH
until soft start is complete (T1.0).
These two fault conditions are allowed to set the fault
latch at any time, including during soft-start.
Over-Temperature Protection
Application Information
Setting the Output Voltage
The chip incorporates an over-temperature-protection
circuit that sets the fault latch when a die temperature of
about 155°C is reached. The IC is allowed to restart
when the die temperature falls below 125°C.
The output voltage of the regulator can be set from
0.8 V to ~80% of VIN by an external resistor divider (R1
and RBIAS in Figure 1). For output voltages >3.3 V,
output current rating may need to be de-rated depending
on the ambient temperature, power dissipated in the
package and the PCB layout. (Refer to Thermal
Information table and Figure 29.)
EN / Auto-Restart
After a fault, EN pin is discharged with 1 µA current pull
down to a 1.1 V threshold before the internal 800 kΩ pull
up is restored. A new soft-start cycle begins when EN
charges above 1.35 V.
The internal reference is set to 0.8 V with 650 nA
sourced from the FB pin to ensure that the regulator
does not start if the pin is left open.
Depending on the external circuit, the FAN21SV06 can
be configured to remain latched off or automatically
restart after a fault, as listed in Table 1.
The external resistor divider is calculated using:
Table 1. Fault / Restart Configurations
VOUT − 0.8V
0.8V
=
+ 650nA
EN pin
Controller / Restart State
(1)
RBIAS
R1
Pull to GND
Standby
Connect RBIAS between FB and AGND.
Connected to
5 V_Reg
No restart – latched OFF
Setting the Clock Frequency
Open
Immediate restart after fault
Oscillator frequency is determined by a resistor, RT, that is
connected between the (RT)pin and AGND (Master Mode)
or 5 V_Reg (Slave Mode):
New soft-start cycle after:
EN is HIGH (Auto Restart Mode)
Cap to GND
With EN left open, restart is immediate.
106
f(KHz)
=
(2)
If auto-restart is not desired, tie the EN pin high with a
logic gate to keep the 1 µA current sink from discharging
EN to 1.1 V. Figure 31 shows one method to pull up EN
to VCC for a latch configuration.
(65 • RT ) +135
where RT is expressed in kΩ.
(106 / f )−135
(3)
RT
=
(KΩ)
65
where frequency (f) is expressed in KHz. In slave mode,
the switching frequency is about 10% slower for the
same RT.
The regulator does not start if RT is open in Master
mode.
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13
Since the ILIM voltage is set by a 10 µA current source
into the RILIM resistor, the basic equation for setting the
reference voltage is:
Calculating the Inductor Value
Typically the inductor value is chosen based on ripple
current (ΔIL) which is chosen between 10 to 35% of the
maximum DC load. Regulator designs that require fast
transient response use a higher ripple-current setting
while regulator designs that require higher efficiency
keep ripple current on the low side and operate at a
lower switching frequency.
V
RILIM = 10µA*RILIM
To calculate RILIM
RILIM = VRILIM/ 10µA
(7)
:
(8)
The voltage VRILIM is made up of two components, VBOT
(which relates to the current through the low-side
MOSFET) and VRMPEAK (which relates to the peak
current through the inductor). Combining those two
voltage terms results in:
VOUT •(1-D)
ΔIL =
(4)
L • f
where f is the oscillator frequency, and
VOUT • (1-D)
L =
RILIM = (VBOT + VRMPEAK)/ 10µA
(9)
(5)
ΔIL • f
R
ILIM = {0.96 + (ILOAD * RDSON *KT*8)} +
(10)
{D*(VIN – 1.8)/(fSW*0.03*10^-3*RRAMP)}/10µA
Setting the Ramp-Resistor Value
As a starting point, set the internal ramp amplitude
where:
(∆VRAMP) to 0.5 V. RRAMP is approximately:
VBOT = 0.96 + (ILOAD * RDSON *KT*8);
(V −1.8)•VOUT
IN
RRAMP(KΩ)
=
− 2
VRMPEAK = D*(VIN – 1.8)/(fSW*0.03*10^-3*RRAMP);
ILOAD = the desired maximum load current;
(6)
18x10−6 •V • f
IN
where frequency (f) is expressed in KHz.
RDSON = the nominal RDSON of the low-side MOSFET;
Refer to AN-6033 — FAN21SV06 Design Guide to
determine the optimal RRAMP value.
KT = the normalized temperature coefficient for the
low-side MOSFET (on datasheet graph);
Setting the Current Limit
D = VOUT/VIN duty cycle;
The current limit system involves two comparators. The
MAX ILIMIT comparator is used with a VILIM fixed-voltage
reference and represents the maximum current limit
allowable. This reference voltage is temperature
compensated to reflect the RDSON variation of the low-
side MOSFET. The ADJUST ILIMIT comparator is used
where the current limit needs to be set lower than the
fSW = Clock frequency in kHz; and
RRAMP = chosen ramp resistor value in kΩ.
After 16 consecutive, pulse-by-pulse, current-limit
cycles, the fault latch is set and the regulator shuts
down. Cycling VCC or EN restores operation after a
normal soft-start cycle (refer to the Auto-Restart
section).
VILIM fixed reference. The 10 µA current source does not
track the RDSON changes over temperature, so change is
added into the equations for calculating the ADJUST
ILIMIT comparator reference voltage, as is shown below.
Figure 32 shows a simplified schematic of the over-
current system.
The over-current protection fault latch is active during
the soft-start cycle. Use 1% resistor for RILIM
.
Loop Compensation
The control loop is compensated using a feedback
network around the error amplifier. Figure 33 shows a
complete Type-3 compensation network. Type-2
compensation eliminates R3 and C3.
PWM
COMP
RAMP
+
_
VERR
PWM
MAX
ILIMIT
+
_
VCC
VILIM
10µA
ADJUST
ILIMIT
ILIMTRIP
+
_
ILIM
RILIM
Figure 32. Current-Limit System Schematic
Figure 33. Compensation Network
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14
Since the FAN21SV06 employs summing current-mode
architecture, Type-2 compensation can be used for
many applications. For applications that require wide
loop bandwidth and/or use very low-ESR output
capacitors, Type-3 compensation may be required.
the power-good signal goes high. Until then, the converter
operates in free-run mode.
RRAMP provides feedforward compensation for changes
in VIN. With a fixed RRAMP value, the modulator gain
increases as VIN is reduced, which could make it difficult
to compensate the loop. For low-input-voltage-range
designs (3 V to 8 V), RRAMP and the compensation
component values are going to be different as compared
to designs with VIN between 8 V and 24 V.
Figure 34. Synchronization Timing Diagram
Master/Slave Configuration
When first enabled, the IC determines if it is configured as
a master or slave for synchronization, depending on how
RT is connected.
Table 2. Master / Slave Configuration
RT to:
GND
Master / Slave
Master
CLK Pin
Output
Input
Figure 35. Slave-CLK-Input Block Diagram
One or more slaves can be connected directly to a master
or system clock to achieve a 180o phase shift.
5V_Reg
Slave, free-running
Slaves free-run in the absence of an external clock signal
input when RT is connected to 5 V_Reg, allowing
regulation to be maintained. It is not recommended to
leave RT open when running in slave mode to avoid
noise pick up on the clock pin.
Slave free-running frequency should be set at least 25%
lower than the incoming synchronizing pulse frequency.
Maximum synchronizing clock frequency is recommended
to be below 600 KHz.
Figure 36. Slaves with 180o Phase Shift
Since the synchronizing circuit utilizes a narrow reset
pulse, the actual phase delay is slightly more than 180o.
Synchronization
The FAN21SV06 is not intended for use in single-output,
multi-phase regulator applications.
The synchronization method employed by the
FAN21SV06 also provides the following features for
maximum flexibility.
PCB Layout
Good PCB layout and careful attention to temperature
rise is essential for reliable operation of the regulator.
Four-layer PCB with 2-ounce copper on the top and
bottom side and thermal vias connecting the layers is
recommended. Keep power traces wide and short to
minimize losses and ringing. Do not connect AGND to
PGND below the IC. Connect AGND pin to PGND at the
output OR to the PGND plane.
.
.
Synchronization to an external system clock
Multiple FAN21SV06s can be synchronized to a
single master or system clock
.
.
Independently programmable phase adjustment for
one or multiple slaves
Free-running capability in the absence of system
clock or, if the master is disabled/faulted, the slaves
can continue to regulate at a lower frequency
The FAN21SV06 master outputs an 85 ns-wide clock
(CLK) signal, delayed 180o from its leading PWM edge.
This feature allows out-of-phase operation for the slaves,
thereby reducing the input capacitance requirements
when more than one converter is operating on the same
input supply. The leading SW-node edge is delayed
~40 ns from the rising PWM signal.
On a slave, synchronization is rising-edge triggered. The
CLK input pin has a 1.8 V threshold and a 200 µA current
source pull-up.
In Master mode, the clock signals go out after power-good
signal asserts high. Likewise, in Slave mode
synchronization to an external clock signal occurs after
Figure 37. Recommended PCB Layout
www.onsemi.com
15
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