FAN3100CSX_技术文档

January 2009

FAN3100

Single 2A High-Speed, Low-Side Gate Driver

Features

Description

The FAN3100 2A gate driver is designed to drive an N-

channel enhancement-mode MOSFET in low-side

switching applications by providing high peak current

pulses during the short switching intervals. The driver is

available with either TTL (FAN3100T) or CMOS

(FAN3100C) input thresholds. Internal circuitry provides

an under-voltage lockout function by holding the output

low until the supply voltage is within the operating

range. The FAN3100 delivers fast MOSFET switching

performance, which helps maximize efficiency in high-

frequency power converter designs.

3A Peak Sink/Source at V_DD= 12V

4.5 to 18V Operating Range

2.5A Sink / 1.8A Source at V_OUT= 6V

Dual-Logic Inputs Allow Configuration as

Non-Inverting or Inverting with Enable Function

Internal Resistors Turn Driver Off If No Inputs

13ns Typical Rise Time and 9ns Typical Fall-Time

with 1nF Load

Choice of TTL or CMOS Input Thresholds

MillerDrive™ Technology

FAN3100 drivers incorporate MillerDrive™ architecture

for the final output stage. This bipolar-MOSFET

combination provides high peak current during the

Miller plateau stage of the MOSFET turn-on / turn-off

process to minimize switching loss, while providing rail-

to-rail voltage swing and reverse current capability.

Typical Propagation Delay Time Under 20ns with

Input Falling or Rising

6-Lead 2x2mm MLP or 5-Pin SOT23 Packages

Rated from –40°C to 125°C Ambient

The FAN3100 also offers dual inputs that can be

configured to operate in non-inverting or inverting mode

and allow implementation of an enable function. If one

or both inputs are left unconnected, internal resistors

bias the inputs such that the output is pulled low to hold

the power MOSFET off.

Applications

Switch-Mode Power Supplies

High-Efficiency MOSFET Switching

Synchronous Rectifier Circuits

DC-to-DC Converters

The FAN3100 is available in a lead-free finish 2x2mm

6-lead Molded Leadless Package (MLP), for smallest

size with excellent thermal performance, or industry-

standard 5-pin SOT23.

Motor Control

Functional Pin Configurations

Figure 1. 2x2mm 6-Lead MLP (Top View)

Figure 2. SOT23-5 (Top View)

FAN3100 • Rev. 1.0.2

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Ordering Information

Input

Part Number

Package

Packing Method Quantity / Reel

Eco Status

Threshold

FAN3100CMPX

FAN3100CSX

FAN3100TMPX

FAN3100TSX

CMOS

TTL

Green

RoHS

Green

RoHS

6-Lead 2x2mm MLP

5-Pin SOT23

Tape & Reel

3000

6-Lead 2x2mm MLP

5-Pin SOT23

TTL

For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.

Package Outlines

IN+ 1

AGND 2

VDD 3

6 IN

5 PGND

4 OUT

Figure 3. 2x2mm 6-Lead MLP (Top View)

Figure 4. SOT23-5 (Top View)

Thermal Characteristics⁽¹⁾

(2)

(3)

(4)

(5)

(6)

Package

Units

Θ_JL

Θ_JT

Θ_JA

Ψ_JB

Ψ_JT

6-Lead 2x2mm Molded Leadless Package (MLP)

2.7

56

133

99

58

2.8

51

42

5

°C/W

SOT23-5

157

Notes:

1. Estimates derived from thermal simulation; actual values depend on the application.

2. Theta_JL (Θ_JL): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any

thermal pad) that are typically soldered to a PCB.

3. Theta_JT (Θ_JT): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is

held at a uniform temperature by a top-side heatsink.

4. Theta_JA (Θ_JA): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airflow.

The value given is for natural convection with no heatsink, as specified in JEDEC standards JESD51-2, JESD51-5, and

JESD51-7, as appropriate.

5. Psi_JB (Ψ_JB): Thermal characterization parameter providing correlation between semiconductor junction temperature and an

application circuit board reference point for the thermal environment defined in Note 4. For the MLP-6 package, the board

reference is defined as the PCB copper connected to the thermal pad and protruding from either end of the package. For the

SOT23-5 package, the board reference is defined as the PCB copper adjacent to pin 2.

6. Psi_JT (Ψ_JT): Thermal characterization parameter providing correlation between the semiconductor junction temperature and

the center of the top of the package for the thermal environment defined in Note 4.

FAN3100 • Rev. 1.0.2

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Pin Definitions

SOT23 MLP

Pin # Pin #

Name

VDD

Pin Description

Supply Voltage. Provides power to the IC.

1

3

2

AGND Analog ground for input signals (MLP only). Connect to PGND underneath the IC.

GND Ground (SOT-23 only). Common ground reference for input and output circuits.

2

3

4

1

6

IN+

IN-

Non-Inverting Input. Connect to VDD to enable output.

Inverting Input. Connect to AGND or PGND to enable output.

Gate Drive Output: Held low unless required inputs are present and V_DDis above

UVLO threshold.

5

4

Pad

5

OUT

P1

Thermal Pad (MLP only). Exposed metal on the bottom of the package which is

electrically connected to pin 5.

Power Ground (MLP only). For output drive circuit; separates switching noise from

inputs.

PGND

Output Logic

IN+

0⁽⁷⁾

1

IN−

OUT

0

1

0

1⁽⁷⁾

0

1⁽⁷⁾

1

Note:

7. Default input signal if no external connection is made.

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FAN3100 • Rev. 1.0.2

3

Block Diagrams

Figure 5. Simplified Block Diagram (SOT23 Pin-out)

Figure 6. Simplified Block Diagram (MLP Pin-out)

FAN3100 • Rev. 1.0.2

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Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device

reliability. The absolute maximum ratings are stress ratings only.

Symbol

V_DD

Parameter

Min.

Max.

Unit

V

VDD to PGND

-0.3

20.0

V_IN

Voltage on IN+ and IN- to GND, AGND, or PGND

Voltage on OUT to GND, AGND, or PGND

Lead Soldering Temperature (10 seconds)

Junction Temperature

GND - 0.3 V_DD+ 0.3

+260

V

V_OUT

T_L

V

ºC

kV

V

T_J

-55

-65

4

+150

T_STG

Storage Temperature

Human Body Model, JEDEC JESD22-A114

Charged Device Model, JEDEC JESD22-C101

Electrostatic Discharge

Protection Level

ESD

750

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol

V_DD

Parameter

Min.

4.5

0

Max.

18.0

V_DD

Unit

V

Supply Voltage Range

Input Voltage IN+, IN-

V_IN

V

T_A

Operating Ambient Temperature

-40

+125

ºC

FAN3100 • Rev. 1.0.2

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Electrical Characteristics

Unless otherwise noted, V_DD= 12V, T_J= -40°C to +125°C. Currents are defined as positive into the device and

negative out of the device.

Symbol

Supply

V_DD

Parameter

Conditions

Min. Typ. Max. Unit

Operating Range

4.5

18.0

0.35

0.8

V

mA

V

FAN3100C⁽⁸⁾

0.20

0.5

3.9

Supply Current

Inputs/EN Not Connected

I_DD

FAN3100T

V_ON

Turn-On Voltage

Turn-Off Voltage

3.5

3.3

4.3

V_OFF

3.7

4.1

V

Inputs (FAN3100T)

V_{INL_T}

V_{INH_T}

I_IN+

IN+, IN- Logic Low Voltage, Maximum

0.8

V

IN+, IN- Logic High Voltage, Minimum

Non-inverting Input

2.0

175

1

IN from 0 to V_DD

-1

µA

V

I_IN-

Inverting Input

-175

0.2

V_HYS

IN+, IN- Logic Hysteresis Voltage

0.4

0.8

Inputs (FAN3100C)

V_{INL_C}

V_{INH_C}

I_INL

IN+, IN- Logic Low Voltage

30

%V_DD

µA

IN+, IN- Logic High Voltage

IN Current, Low

70

175

1

IN from 0 to V_DD

-1

I_INH

IN Current, High

-175

µA

V_{HYS_C}

Output

IN+, IN- Logic Hysteresis Voltage

17

%V_DD

OUT at V_DD/2,

I_SINK

OUT Current, Mid-Voltage, Sinking⁽⁹⁾

2.5

A

C_LOAD= 0.1µF, f = 1kHz

OUT at V_DD/2,

I_SOURCE

I_{PK_SINK}

OUT Current, Mid-Voltage, Sourcing⁽⁹⁾

OUT Current, Peak, Sinking⁽⁹⁾

-1.8

C_LOAD= 0.1µF, f = 1kHz

C_LOAD= 1000pF

3

-3

A

I_{PK_SOURCE}OUT Current, Peak, Sourcing⁽⁹⁾

t_RISE

t_FALL

Output Rise Time⁽¹⁰⁾

Output Fall Time⁽¹⁰⁾

Output Prop. Delay, CMOS Inputs⁽¹⁰⁾

Output Prop. Delay, TTL Inputs⁽¹⁰⁾

Output Reverse Current Withstand⁽⁹⁾

13

9

20

14

28

30

ns

mA

C_LOAD= 1000pF

t_D1, t_D2

I_RVS

0 - 12V_IN; 1V/ns Slew Rate

0 - 5V_IN; 1V/ns Slew Rate

7

9

15

16

500

Note:

8. Lower supply current due to inactive TTL circuitry.

9. Not tested in production.

10. See Timing Diagrams of Figure 7 and Figure 8.

FAN3100 • Rev. 1.0.2

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Timing Diagrams

90%

Output

10%

V_INH

Input

V_INL

V_INH

V_INL

Input

t_D1

t_D2

t_D1

t_D2

t_FALL

t_RISE

Figure 7. Non-Inverting

t_RISE

t_FALL

Figure 8. Inverting

FAN3100 • Rev. 1.0.2

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Typical Performance Characteristics

Typical characteristics are provided at 25°C and V_DD=12V unless otherwise noted.

Figure 9. I_DD(Static) vs. Supply Voltage

Figure 11. I_DD(No-Load) vs. Frequency

Figure 13. I_DD(1nF Load) vs. Frequency

Figure 10. I_DD(Static) vs. Supply Voltage

Figure 12. I_DD(No-Load) vs. Frequency

Figure 14. I_DD(1nF Load) vs. Frequency

FAN3100 • Rev. 1.0.2

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Typical Performance Characteristics

Typical characteristics are provided at 25°C and V_DD=12V unless otherwise noted.

Figure 15. I_DD(Static) vs. Temperature

Figure 17. Input Thresholds vs. Supply Voltage

Figure 19. Input Thresholds % vs. Supply Voltage

Figure 16. I_DD(Static) vs. Temperature

Figure 18. Input Thresholds vs. Supply Voltage

FAN3100 • Rev. 1.0.2

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Typical Performance Characteristics

Typical characteristics are provided at 25°C and V_DD=12V unless otherwise noted.

Figure 20. CMOS Input Thresholds vs. Temperature

Figure 22. UVLO Thresholds vs. Temperature

Figure 24. Propagation Delay vs. Supply Voltage

Figure 21. TTL Input Thresholds vs. Temperature

Figure 23. UVLO Hysteresis vs. Temperature

Figure 25. Propagation Delay vs. Supply Voltage

FAN3100 • Rev. 1.0.2

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Typical Performance Characteristics

Typical characteristics are provided at 25°C and V_DD=12V unless otherwise noted.

Figure 26. Propagation Delay vs. Supply Voltage

Figure 28. Propagation Delay vs. Temperature

Figure 30. Propagation Delay vs. Temperature

Figure 27. Propagation Delay vs. Supply Voltage

Figure 29. Propagation Delay vs. Temperature

Figure 31. Propagation Delay vs. Temperature

FAN3100 • Rev. 1.0.2

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Typical Performance Characteristics

Typical characteristics are provided at 25°C and V_DD=12V unless otherwise noted.

Figure 32. Fall Time vs. Supply Voltage

Figure 33. Rise Time vs. Supply Voltage

Figure 34. Rise and Fall Time vs. Temperature

Figure 35. Rise / Fall Waveforms with 1nF Load

Figure 36. Rise / Fall Waveforms with 10nF Load

FAN3100 • Rev. 1.0.2

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Typical Performance Characteristics

Typical characteristics are provided at 25°C and V_DD=12V unless otherwise noted.

Figure 37. Quasi-Static Source Current with V_DD=12V

Figure 38. Quasi-Static Sink Current with V_DD=12V

Figure 39. Quasi-Static Source Current with V_DD=8V

Figure 40. Quasi-Static Sink Current with V_DD=8V

Figure 41. Quasi-Static I_OUT/ V_OUTTest Circuit

FAN3100 • Rev. 1.0.2

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Applications Information

Input Thresholds

because the body diode is generally conducting before

the MOSFET is switched on.

The FAN3100 offers TTL or CMOS input thresholds. In

the FAN3100T, the input thresholds meet industry-

standard TTL logic thresholds, independent of the V_DD

The output pin slew rate is determined by V_DDvoltage

and the load on the output. It is not user adjustable, but

if a slower rise or fall time at the MOSFET gate is

needed, a series resistor can be added.

voltage, and there is

a

hysteresis voltage of

approximately 0.4V. These levels permit the inputs to

be driven from a range of input logic signal levels for

which a voltage over 2V is considered logic high. The

driving signal for the TTL inputs should have fast rising

and falling edges with a slew rate of 6V/µs or faster, so

the rise time from 0 to 3.3V should be 550ns or less.

With reduced slew rate, circuit noise could cause the

driver input voltage to exceed the hysteresis voltage

and retrigger the driver input, causing erratic operation.

In the FAN3100C, the logic input thresholds are

dependent on the V_DDlevel and, with V_DDof 12V, the

logic rising edge threshold is approximately 55% of V_DD

and the input falling edge threshold is approximately

38% of V_DD. The CMOS input configuration offers a

hysteresis voltage of approximately 17% of V_DD. The

CMOS inputs can be used with relatively slow edges

(approaching DC) if good decoupling and bypass

techniques are incorporated in the system design to

prevent noise from violating the input voltage hysteresis

window. This allows setting precise timing intervals by

fitting an R-C circuit between the controlling signal and

the IN pin of the driver. The slow rising edge at the IN

pin of the driver introduces a delay between the

controlling signal and the OUT pin of the driver.

Figure 42. MillerDrive™ Output Architecture

Under-Voltage Lockout

The FAN3100 start-up logic is optimized to drive ground

referenced N-channel MOSFETs with a under-voltage

lockout (UVLO) function to ensure that the IC starts up

in an orderly fashion. When V_DDis rising, yet below the

3.9V operational level, this circuit holds the output low,

regardless of the status of the input pins. After the part

is active, the supply voltage must drop 0.2V before the

part shuts down. This hysteresis helps prevent chatter

when low V_DDsupply voltages have noise from the

power switching. This configuration is not suitable for

driving high-side P-channel MOSFETs because the low

output voltage of the driver would turn the P-channel

MOSFET on with V_DDbelow 3.9V.

Static Supply Current

In the I_DD(static) typical performance graphs (Figure 9 -

Figure 10 and Figure 15 - Figure 16), the curve is

produced with all inputs floating (OUT is low) and

indicates the lowest static I_DDcurrent for the tested

configuration. For other states, additional current flows

through the 100kΩ resistors on the inputs and outputs

shown in the block diagrams (see Figure 5 - Figure 6).

In these cases, the actual static I_DDcurrent is the value

obtained from the curves plus this additional current.

VDD Bypass Capacitor Guidelines

To enable this IC to turn a power device on quickly, a

local, high-frequency, bypass capacitor C_BYPwith low

ESR and ESL should be connected between the VDD

and GND pins with minimal trace length. This capacitor

is in addition to bulk electrolytic capacitance of 10µF to

47µF often found on driver and controller bias circuits.

MillerDrive™ Gate Drive Technology

FAN3100 drivers incorporate the MillerDrive™

architecture shown in Figure 42 for the output stage, a

combination of bipolar and MOS devices capable of

providing large currents over a wide range of supply

voltage and temperature variations. The bipolar devices

carry the bulk of the current as OUT swings between

1/3 to 2/3 V_DDand the MOS devices pull the output to

the high or low rail.

A typical criterion for choosing the value of C_BYPis to

keep the ripple voltage on the V_DDsupply ≤5%. Often

this is achieved with a value ≥ 20 times the equivalent

load capacitance C_EQV, defined here as Q_gate/V_DD

.

Ceramic capacitors of 0.1µF to 1µF or larger are

common choices, as are dielectrics, such as X5R and

X7R, which have good temperature characteristics and

high pulse current capability.

The purpose of the MillerDrive™ architecture is to

speed up switching by providing the highest current

during the Miller plateau region when the gate-drain

capacitance of the MOSFET is being charged or

discharged as part of the turn-on / turn-off process.

For applications that have zero voltage switching during

the MOSFET turn-on or turn-off interval, the driver

supplies high peak current for fast switching even

though the Miller plateau is not present. This situation

often occurs in synchronous rectifier applications

If circuit noise affects normal operation, the value of

C_BYPmay be increased to 50-100 times the C_EQV, or

C_BYPmay be split into two capacitors. One should be a

larger value, based on equivalent load capacitance, and

the other a smaller value, such as 1-10nF, mounted

closest to the VDD and GND pins to carry the higher-

frequency components of the current pulses.

FAN3100 • Rev. 1.0.2

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Figure 44 shows the current path when the gate driver

turns the MOSFET off. Ideally, the driver shunts the

current directly to the source of the MOSFET in a small

circuit loop. For fast turn-off times, the resistance and

inductance in this path should be minimized.

Layout and Connection Guidelines

The FAN3100 incorporates fast reacting input circuits,

short propagation delays, and powerful output stages

capable of delivering current peaks over 2A to facilitate

voltage transition times from under 10ns to over 100ns.

The following layout and connection guidelines are

strongly recommended:

Keep high-current output and power ground paths

separate from logic input signals and signal ground

paths. This is especially critical when dealing with

TTL-level logic thresholds.

Keep the driver as close to the load as possible to

minimize the length of high-current traces. This

reduces the series inductance to improve high-

speed switching, while reducing the loop area that

can radiate EMI to the driver inputs and other

surrounding circuitry.

Figure 44. Current Path for MOSFET Turn-Off

Truth Table of Logic Operation

The FAN3100 truth table indicates the operational

states using the dual-input configuration. In a non-

inverting driver configuration, the IN- pin should be a

logic low signal. If the IN- pin is connected to logic high,

a disable function is realized, and the driver output

remains low regardless of the state of the IN+ pin.

The FAN3100 is available in two packages with

slightly different pinouts, offering similar

performance. In the 6-pin MLP package, Pin 2 is

internally connected to the input analog ground and

should be connected to power ground, Pin 5,

through a short direct path underneath the IC. In

the 5-pin SOT23, the internal analog and power

ground connections are made through separate,

individual bond wires to Pin 2, which should be

used as the common ground point for power and

control signals.

IN+

0

IN-

0

OUT

0

1

0

1

0

1

Many high-speed power circuits can be susceptible

to noise injected from their own output or other

external sources, possibly causing output re-

triggering. These effects can be especially obvious

if the circuit is tested in breadboard or non-optimal

circuit layouts with long input, enable, or output

leads. For best results, make connections to all

pins as short and direct as possible.

In the non-inverting driver configuration in Figure 45,

the IN- pin is tied to ground and the input signal (PWM)

is applied to IN+ pin. The IN- pin can be connected to

logic high to disable the driver and the output remains

low, regardless of the state of the IN+ pin.

The turn-on and turn-off current paths should be

minimized as discussed in the following sections.

Figure 43 shows the pulsed gate drive current path

when the gate driver is supplying gate charge to turn

the MOSFET on. The current is supplied from the local

bypass capacitor, C_BYP, and flows through the driver to

the MOSFET gate and to ground. To reach the high

peak currents possible, the resistance and inductance

in the path should be minimized. The localized C_BYP

acts to contain the high peak current pulses within this

driver-MOSFET circuit, preventing them from disturbing

the sensitive analog circuitry in the PWM controller.

Figure 45. Dual-Input Driver Enabled,

Non-Inverting Configuration

In the inverting driver application shown in Figure 46, the

IN+ pin is tied high. Pulling the IN+ pin to GND forces the

output low, regardless of the state of the IN- pin.

Figure 46. Dual-Input Driver Enabled,

Inverting Configuration

Figure 43. Current Path for MOSFET Turn-On

FAN3100 • Rev. 1.0.2

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source voltage, V_GS, with gate charge, Q_G, at

switching frequency, f_SW, is determined by:

Operational Waveforms

At power up, the driver output remains low until the V_DD

voltage reaches the turn-on threshold. The magnitude

of the OUT pulses rises with V_DDuntil steady-state V_DD

is reached. The non-inverting operation illustrated in

Figure 47 shows that the output remains low until the

UVLO threshold is reached, then the output is in-phase

with the input.

P_GATE= Q_G• V_GS• F_SW

(2)

Dynamic Pre-drive / Shoot-through Current: A power

loss resulting from internal current consumption

under dynamic operating conditions, including pin

pull-up / pull-down resistors, can be obtained using

the I_DD(no-Load) vs. Frequency graphs in Typical

Performance Characteristics to determine the

current I_DYNAMICdrawn from V_DDunder actual

operating conditions:

P_DYNAMIC= I_DYNAMIC• V_DD

(3)

Once the power dissipated in the driver is determined,

the driver junction rise with respect to circuit board can

be evaluated using the following thermal equation,

ψ_JB

assuming

was determined for a similar thermal

design (heat sinking and air flow):

ψ

T_J= P_TOTAL

where:

•

_JB+ T_B

(4)

T_J

ψ_JB

= driver junction temperature

= (psi) thermal characterization parameter relating

temperature rise to total power dissipation

Figure 47. Non-Inverting Start-Up Waveforms

For the inverting configuration of Figure 46, start-up

waveforms are shown in Figure 48. With IN+ tied to

VDD and the input signal applied to IN–, the OUT

pulses are inverted with respect to the input. At power

up, the inverted output remains low until the V_DDvoltage

reaches the turn-on threshold, then it follows the input

with inverted phase.

T_B= board temperature in location defined in the

Thermal Characteristics table.

In a typical forward converter application with 48V input,

as shown in Figure 49, the FDS2672 would be a

potential MOSFET selection. The typical gate charge

would be 32nC with V_GS= V_DD= 10V. Using a TTL input

driver at a switching frequency of 500kHz, the total

power dissipation can be calculated as:

P

_GATE= 32nC • 10V • 500kHz = 0.160W

P_DYNAMIC= 8mA • 10V = 0.080W

_TOTAL= 0.24W

The 5-pin SOT23 has

(5)

(6)

(7)

P

a

junction-to-lead thermal

ψ

characterization parameter _JB= 51°C/W.

In a system application, the localized temperature

around the device is a function of the layout and

construction of the PCB along with airflow across the

surfaces. To ensure reliable operation, the maximum

junction temperature of the device must be prevented

from exceeding the maximum rating of 150°C; with 80%

derating, T_Jwould be limited to 120°C. Rearranging

Equation 4 determines the board temperature required

to maintain the junction temperature below 120°C:

Figure 48. Inverting Start-Up Waveforms

Thermal Guidelines

Gate drivers used to switch MOSFETs and IGBTs at

high frequencies can dissipate significant amounts of

power. It is important to determine the driver power

dissipation and the resulting junction temperature in the

application to ensure that the part is operating within

acceptable temperature limits.

ψ

T

_B,MAX= T_J- P_TOTAL

•

(8)

(9)

JB

T_B,MAX= 120°C – 0.24W • 51°C/W = 108°C

For comparison purposes, replace the 5-pin SOT23

used in the previous example with the 6-pin MLP

ψ_JB

package with

= 2.8°C/W. The 6-pin MLP package

The total power dissipation in a gate driver is the sum of

can operate at a PCB temperature of 119°C, while

maintaining the junction temperature below 120°C. This

illustrates that the physically smaller MLP package with

thermal pad offers a more conductive path to remove

the heat from the driver. Consider the tradeoffs between

reducing overall circuit size with junction temperature

reduction for increased reliability.

two components; P_GATEand P_DYNAMIC

:

P_TOTAL= P_GATE+ P_DYNAMIC

(1)

Gate Driving Loss: The most significant power loss

results from supplying gate current (charge per unit

time) to switch the load MOSFET on and off at the

switching frequency. The power dissipation that

results from driving a MOSFET at a specified gate-

FAN3100 • Rev. 1.0.2

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Typical Application Diagrams

Figure 49. Forward Converter, Primary-Side Gate Drive (MLP Package Shown)

Figure 50. Driver for Two-Transistor Forward Converter Gate Transformer

Figure 51. Secondary Synchronous Rectifier Driver

V_DD

R

FAN3100C

OUT

IN

C

Delay

IN

OUT

Figure 52. Programmable Time Delay Using CMOS Input

FAN3100 • Rev. 1.0.2

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17

Table 1. Related Products

Gate

Part

Number

Input

Threshold

Type

Drive⁽¹¹⁾

Logic

Package

(Sink/Src)

FAN3100C Single 2A +2.5A / -1.8A CMOS

FAN3100T Single 2A +2.5A / -1.8A TTL

Single Channel of Two-Input/One-Output

Dual Inverting Channels + Dual Enable

SOT23-5, MLP6

SOIC8, MLP8

FAN3226C Dual 2A

FAN3226T Dual 2A

FAN3227C Dual 2A

FAN3227T Dual 2A

FAN3228C Dual 2A

FAN3228T Dual 2A

FAN3229C Dual 2A

FAN3229T Dual 2A

FAN3223C Dual 4A

FAN3223T Dual 4A

FAN3224C Dual 4A

FAN3224T Dual 4A

FAN3225C Dual 4A

+2.4A / -1.6A CMOS

+2.4A / -1.6A TTL

+2.4A / -1.6A CMOS

+2.4A / -1.6A TTL

+2.4A / -1.6A CMOS

+2.4A / -1.6A TTL

+2.4A / -1.6A CMOS

+2.4A / -1.6A TTL

+4.3A / -2.8A CMOS

+4.3A / -2.8A TTL

+4.3A / -2.8A CMOS

+4.3A / -2.8A TTL

+4.3A / -2.8A CMOS

+4.3A / -2.8A TTL

Dual Inverting Channels + Dual Enable

Dual Non-Inverting Channels + Dual Enable

Dual Channels of Two-Input/One-Output, Pin Config.1

Dual Channels of Two-Input/One-Output, Pin Config.2

Dual Inverting Channels + Dual Enable

Dual Non-Inverting Channels + Dual Enable

Dual Channels of Two-Input/One-Output

FAN3225T Dual 4A

Dual Channels of Two-Input/One-Output

Note:

11. Typical currents with OUT at 6V and V_DD= 12V.

FAN3100 • Rev. 1.0.2

www.fairchildsemi.com

18

Physical Dimensions

Figure 53. 2x2mm, 6-Lead Molded Leadless Package (MLP)

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify

or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,

specifically the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

FAN3100 • Rev. 1.0.2

www.fairchildsemi.com

19

Physical Dimensions (Continued)

SYMM

C

L

3.00

2.80

0.95

A

5

4

B

3.00

2.60

1.70

1.50

2.60

1

2

3

(0.30)

1.00

0.50

0.30

0.95

0.20

C A B

1.90

0.70

TOP VIEW

LAND PATTERN RECOMMENDATION

SEE DETAIL A

1.30

0.90

1.45 MAX

C

0.15

0.05

0.22

0.08

0.10 C

NOTES: UNLESS OTHEWISE SPECIFIED

A) THIS PACKAGE CONFORMS TO JEDEC

MO-178, ISSUE B, VARIATION AA,

B) ALL DIMENSIONS ARE IN MILLIMETERS.

GAGE PLANE

0.25

C) MA05Brev5

8°

0°

0.55

0.35

SEATING PLANE

0.60 REF

Figure 54. 5-Lead SOT-23

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify

or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,

specifically the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

FAN3100 • Rev. 1.0.2

www.fairchildsemi.com

20

FAN3100 • Rev. 1.0.2

www.fairchildsemi.com

21


型号：	FAN3100CSX
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	Single 2A High-Speed, Low-Side Gate Driver 单2A高速，低侧栅极驱动器驱动器 MOSFET驱动器栅极驱动程序和接口接口集成电路光电二极管栅极驱动 PC
文件：	总21页 (文件大小：1446K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

FAN3100CSX [FAIRCHILD]

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