FAN3229CMX_12_技术文档

March 2012

FAN3226 / FAN3227 / FAN3228 / FAN3229_F085

Dual 2A High-Speed, Low-Side Gate Drivers

Description

Features

The FAN3226-29 family of dual 2A gate drivers is

designed to drive N-channel enhancement-mode

MOSFETs in low-side switching applications by

providing high peak current pulses during the short

switching intervals. The driver is available with either

TTL or CMOS input thresholds. Internal circuitry

provides an under-voltage lockout function by holding

the output low until the supply voltage is within the

operating range. In addition, the drivers feature matched

internal propagation delays between A and B channels

for applications requiring dual gate drives with critical

timing, such as synchronous rectifiers. This enables

connecting two drivers in parallel to effectively double

the current capability driving a single MOSFET.

.

Qualified to AEC Q-100

4.5 to 18V Operating Range

3A Peak Sink/Source at V_DD= 12V

2.4A Sink / 1.6A Source at V_OUT= 6V

Choice of TTL or CMOS Input Thresholds

Four Versions of Dual Independent Drivers:

-

Dual Inverting + Enable (FAN3226)

Dual Non-Inverting + Enable (FAN3227)

Dual Inputs in Two Pin-Out Configurations:

o

Compatible with FAN3225x (FAN3228)

Compatible with TPS2814D (FAN3229)

The FAN322X drivers incorporate MillerDrive™

architecture for the final output stage. This bipolar-

MOSFET combination provides high current during the

Miller plateau stage of the MOSFET turn-on / turn-off

process to minimize switching loss, while providing rail-

to-rail voltage swing and reverse current capability.

.

Internal Resistors Turn Driver Off If No Inputs

MillerDrive™ Technology

12ns / 9ns Typical Rise/Fall Times with 1nF Load

Typical Propagation Delay Under 20ns Matched

within 1ns to the Other Channel

The FAN3226 offers two inverting drivers and the

FAN3227 offers two non-inverting drivers. Each device

has dual independent enable pins that default to ON if

not connected. In the FAN3228 and FAN3229, each

channel has dual inputs of opposite polarity, which

allows configuration as non-inverting or inverting with an

optional enable function using the second input. If one

or both inputs are left unconnected, internal resistors

bias the inputs such that the output is pulled low to hold

the power MOSFET off.

.

Double Current Capability by Paralleling Channels

8-Lead SOIC Package

Rated from –40°C to +125°C Ambient

Applications

.

Switch-Mode Power Supplies

High-Efficiency MOSFET Switching

Synchronous Rectifier Circuits

DC-to-DC Converters

Related Resources

.

AN-6069: Application Review and Comparative

Evaluation of Low-Side Gate Drivers

Motor Control

FAN3226

FAN3227

FAN3228

FAN3229

Figure 1.

Pin Configurations

FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 • Rev. 1.0.0

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Ordering Information

Input

Threshold

Packing

Method

Quantity

per Reel

Eco

Status

Part Number

Logic

Package

FAN3226CMX_F085

CMOS

TTL

SOIC-8

Tape & Reel

2,500

RoHS

Dual Inverting Channels +

Dual Enable

FAN3226TMX_F085

FAN3227CMX_F085

FAN3227TMX_F085

CMOS

TTL

Dual Non-Inverting Channels

+ Dual Enable

Dual Channels of Two-Input

/ One-Output Drivers, Pin

Configuration 1

FAN3228CMX_F085

FAN3228TMX_F085

FAN3229CMX_F085

FAN3229TMX_F085

CMOS

TTL

SOIC-8

Tape & Reel

2,500

.

RoHS

Dual Channels of Two-Input

/ One-Output Drivers, Pin

Configuration 2

CMOS

TTL

For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html

Package Outline

Figure 2. SOIC-8 (Top View)

Thermal Characteristics⁽¹⁾

(2)

(3)

(4)

(5)

(6)

Package

8-Pin Small Outline Integrated Circuit (SOIC)

Notes:

Units

_JL

_JT

_JA

_JB

_JT

40

31

89

43

3.0

°C/W

1. Estimates derived from thermal simulation; actual values depend on the application.

2. Theta_JL ( _JL): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any

thermal pad) that are typically soldered to a PCB.



3. Theta_JT (



_JT): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is

held at a uniform temperature by a top-side heatsink.

4. Theta_JA (Θ_JA): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airflow.

The value given is for natural convection with no heatsink, as specified in JEDEC standards JESD51-2, JESD51-5, and

JESD51-7, as appropriate.

5. Psi_JB (_JB): Thermal characterization parameter providing correlation between semiconductor junction temperature and an

application circuit board reference point for the thermal environment defined in Note 4. For the SOIC-8 package, the board

reference is defined as the PCB copper adjacent to pin 6.

6. Psi_JT (

_JT): Thermal characterization parameter providing correlation between the semiconductor junction temperature and

the center of the top of the package for the thermal environment defined in Note 4.

FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 • Rev. 1.0.0

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2

FAN3226

FAN3227

FAN3228

FAN3229

Figure 3. Pin Configurations (Repeated)

Pin Definitions

Name

Pin Description

Enable Input for Channel A. Pull pin low to inhibit driver A. ENA has TTL thresholds for both TTL and

CMOS INx threshold.

ENA

ENB

Enable Input for Channel B. Pull pin low to inhibit driver B. ENB has TTL thresholds for both TTL and

CMOS INx threshold.

GND Ground. Common ground reference for input and output circuits.

INA

Input to Channel A.

INA+ Non-Inverting Input to Channel A. Connect to VDD to enable output.

INA-

INB

Inverting Input to Channel A. Connect to GND to enable output.

Input to Channel B.

INB+ Non-Inverting Input to Channel B. Connect to VDD to enable output.

INB-

Inverting Input to Channel B. Connect to GND to enable output.

OUTA Gate Drive Output A: Held low unless required input(s) are present and V_DDis above UVLO threshold.

OUTB Gate Drive Output B: Held low unless required input(s) are present and V_DDis above UVLO threshold.

Gate Drive Output A (inverted from the input): Held low unless required input is present and V_DDis

OUTA

above UVLO threshold.

Gate Drive Output B (inverted from the input): Held low unless required input is present and V_DDis

above UVLO threshold.

OUTB

VDD

Supply Voltage. Provides power to the IC.

Output Logic

FAN3228 and FAN3229

FAN3226 (x=A or B)

FAN3227 (x=A or B)

(x=A or B)

ENx

INx

ENx

INx

OUTx

INx+

INx−

OUTx

0

1⁽⁷⁾

0

1

0

0⁽⁷⁾

0

1

0⁽⁷⁾

1

0

1⁽⁷⁾

0

1

0

1

1⁽⁷⁾

0

1⁽⁷⁾

0⁽⁷⁾

1

0

1⁽⁷⁾

1

Note:

7. Default input signal if no external connection is made.

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FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 • Rev. 1.0.0

3

Block Diagrams

V_DD

100k

ENA

1

8

ENB

V_DD

INA

2

3

OUTA

VDD

7

6

100k

GND

UVLO

V_{DD_OK}

V_DD

100k

OUTB

5

INB

4

100k

Figure 4. FAN3226 Block Diagram

Figure 5. FAN3227 Block Diagram

FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 • Rev. 1.0.0

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4

Block Diagrams

Figure 6. FAN3228 Block Diagram

Figure 7. FAN3229 Block Diagram

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FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 • Rev. 1.0.0

5

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only.

Symbol

V_DD

Parameter

Min.

Max.

Unit

V

VDD to PGND

-0.3

20.0

V_EN

ENA and ENB to GND

GND - 0.3 V_DD+ 0.3

+260

V

V_IN

INA, INA+, INA–, INB, INB+ and INB– to GND

OUTA and OUTB to GND

V

V_OUT

T_L

V

Lead Soldering Temperature (10 Seconds)

Junction Temperature

ºC

T_J

-55

-65

+150

T_STG

ESD

Storage Temperature

ºC

kV

Human Body Model, JEDEC JESD22-A114

3

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol

V_DD

Parameter

Min.

4.5

0

Max.

18.0

V_DD

Unit

V

Supply Voltage Range

V_EN

Enable Voltage ENA and ENB

V

V_IN

Input Voltage INA, INA+, INA–, INB, INB+ and INB–

Operating Ambient Temperature

0

V_DD

V

T_A

-40

+125

ºC

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FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 • Rev. 1.0.0

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Electrical Characteristics

Unless otherwise noted, V_DD=12V, T_J=-40°C to +125°C. Currents are defined as positive into the device and negative

out of the device.

Symbol

Supply

V_DD

Parameter

Conditions

Min. Typ. Max. Unit

Operating Range

4.5

18.0

1.20

1.05

4.5

V

mA

V

TTL

CMOS⁽⁸⁾

0.75

0.65

3.9

Supply Current Inputs / EN

Not Connected

I_DD

V_ON

Turn-On Voltage

Turn-Off Voltage

INA=ENA=V_DD, INB=ENB=0V

3.4

3.2

V_OFF

3.7

4.3

V

Inputs (FAN322xT)⁽⁹⁾

V_{INL_T}

V_{INH_T}

I_{INx_T}

INx Logic Low Threshold

0.8

1.2

1.6

V

INx Logic High Threshold

Non-inverting Input Current

Inverting Input Current

2.0

1.5

IN = 0V

IN = V_DD

IN = 0V

IN = V_DD

-1.5

90

µA

V

I_{INx_T}

120 175.0

I_{INx_T}

-175.0 -120

-1.5

-90

1.5

0.8

I_{INx_T}

Inverting Input Current

V_{HYS_T}

TTL Logic Hysteresis Voltage

0.2

0.4

Inputs (FAN322xC)⁽⁹⁾

V_{INL_C}

V_{INH_C}

I_{INx_C}

INx Logic Low Threshold

30

38

55

%V_DD

µA

INx Logic High Threshold

Non-Inverting Input Current

Inverting Input Current

70

1.5

175

-90

1.5

IN = 0V

IN = V_DD

IN = 0V

IN = V_DD

-1.5

90

120

µA

-175

-1.5

-120

µA

Inverting Input Current

µA

V_{HYS_C}CMOS Logic Hysteresis Voltage

ENABLE (FAN3226C, FAN3226T, FAN3227C, FAN3227T)

17

%V_DD

V_ENL

V_ENH

V_{HYS_T}

R_PU

Enable Logic Low Threshold

Enable Logic High Threshold

TTL Logic Hysteresis Voltage⁽¹⁰⁾

Enable Pull-up Resistance⁽¹⁰⁾

EN from 5V to 0V

EN from 0V to 5V

0.8

1.2

1.6

0.4

100

19

V

2.0

V

kΩ

ns

t_D3

0V to 5V EN, 1V/ns Slew Rate

5V to 0V EN, 1V/ns Slew Rate

8.5

9

34

32

EN to Output Propagation Delay⁽¹²⁾

t_D4

18

Continued on the following page…

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FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 • Rev. 1.0.0

7

Electrical Characteristics (Continued)

Unless otherwise noted, V_DD=12V, T_J=-40°C to +125°C. Currents are defined as positive into the device and negative

out of the device.

Symbol

Output

Parameter

Conditions

Min. Typ. Max. Unit

OUT at V_DD/2,

_LOAD=0.1µF, f=1kHz

I_SINK

OUT Current, Mid-Voltage, Sinking⁽¹⁰⁾

2.4

A

C

OUT at V_DD/2,

_LOAD=0.1µF, f=1kHz

I_SOURCE

I_{PK_SINK}

OUT Current, Mid-Voltage, Sourcing⁽¹⁰⁾

OUT Current, Peak, Sinking⁽¹⁰⁾

-1.6

C

C_LOAD=0.1µF, f=1kHz

3

A

I_{PK_SOURCE}OUT Current, Peak, Sourcing⁽¹⁰⁾

-3

V_OH

High Level Output Voltage

15

35

mV

V^OH= VDD – VOUT, IOUT = –1mA

V_OL

t_RISE

t_FALL

t_D1

Low Level Output Voltage

Output Rise Time⁽¹²⁾

Output Fall Time⁽¹²⁾

IOUT = 1mA

C_LOAD=1000pF

CMOS Input

TTL Input

10

12

9

25

22

mV

ns

17

ns

7

6

9

15

19

18

33

Output Propagation Delay, CMOS

Inputs⁽¹²⁾

ns

t_D2

37.5

34

t_D1

Output Propagation Delay, TTL

Inputs⁽¹²⁾

t_D2

TTL Input

32

Propagation Matching Between

Channels

INA=INB, OUTA and OUTB

at 50% point

t_DEL.MATCH

2

4

ns

I_RVS

Output Reverse Current Withstand⁽¹⁰⁾

500

mA

Notes:

8. Lower supply current due to inactive TTL circuitry.

9. EN inputs have TTL thresholds; refer to the ENABLE section.

10. Not tested in production.

11. See Timing Diagrams of Figure 10 and Figure 11.

12. See Timing Diagrams of Figure 8 and Figure 9.

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FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 • Rev. 1.0.0

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Timing Diagrams

Figure 8. Non-Inverting (EN HIGH or Floating)

Figure 9. Inverting (EN HIGH or Floating)

Figure 10. Non-Inverting (IN HIGH)

Figure 11. Inverting (IN LOW)

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FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 • Rev. 1.0.0

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Typical Performance Characteristics

Typical characteristics are provided at 25°C and V_DD=12V unless otherwise noted.

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

TTL Input

FAN3226C, 27C

Inputs and Enables

Floating, Outputs

Inputs and Enables

Floating, Outputs Low

4

6

8

10

12

14

16

18

4

6

8

10

12

14

16

18

Supply Voltage (V)

Figure 12. I_DD(Static) vs. Supply Voltage⁽¹³⁾

Figure 13. I_DD(Static) vs. Supply Voltage⁽¹³⁾

1.6

1.4

FAN3228C, 29C

1.2

1.0

0.8

0.6

0.4

0.2

0.0

All Inputs Floating,

Outputs Low

4

6

8

10

12

14

16

18

V

_DD- Supply Voltage (V)

Figure 14. I_DD(Static) vs. Supply Voltage⁽¹³⁾

Figure 15. I_DD(No-Load) vs. Frequency

Figure 16. I_DD(No-Load) vs. Frequency

FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 • Rev. 1.0.0

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10

Typical Performance Characteristics

Typical characteristics are provided at 25°C and V_DD=12V unless otherwise noted.

Figure 17. I_DD(1nF Load) vs. Frequency

Figure 18. I_DD(1nF Load) vs. Frequency

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

1.6

FAN3226C, 27C

TTL Input

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

Inputs and Enables

Floating, Outputs

Inputs and Enables

Floating, Outputs

-50 -25

0

25

50

75 100 125

-50

-25

0

25

50

75

100

125

Temperature (°C)

Figure 19. I_DD(Static) vs. Temperature⁽¹³⁾

Figure 20. I_DD(Static) vs. Temperature⁽¹³⁾

1.6

FAN3228C, 29C

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

All Inputs Floating,

Outputs Low

-50 -25

0

25

50

75 100 125

Temperature (°C)

Figure 21. I_DD(Static) vs. Temperature⁽¹³⁾

FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 • Rev. 1.0.0

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11

Typical Performance Characteristics

Typical characteristics are provided at 25°C and V_DD=12V unless otherwise noted.

Figure 22. Input Thresholds vs. Supply Voltage

Figure 23. Input Thresholds vs. Supply Voltage

Figure 24. Input Threshold % vs. Supply Voltage

Figure 25. Input Thresholds vs. Temperature

Figure 26. Input Thresholds vs. Temperature

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FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 • Rev. 1.0.0

12

Typical Performance Characteristics

Typical characteristics are provided at 25°C and V_DD=12V unless otherwise noted.

Figure 27. UVLO Thresholds vs. Temperature

Figure 28. UVLO Threshold vs. Temperature

Figure 29. Propagation Delays vs. Supply Voltage

Figure 30. Propagation Delays vs. Supply Voltage

Figure 31. Propagation Delays vs. Supply Voltage

Figure 32. Propagation Delays vs. Supply Voltage

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FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 • Rev. 1.0.0

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Typical Performance Characteristics

Typical characteristics are provided at 25°C and V_DD=12V unless otherwise noted.

Figure 33. Propagation Delays vs. Temperature

Figure 35. Propagation Delays vs. Temperature

Figure 37. Fall Time vs. Supply Voltage

Figure 34. Propagation Delays vs. Temperature

Figure 36. Propagation Delays vs. Temperature

Figure 38. Rise Time vs. Supply Voltage

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FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 • Rev. 1.0.0

14

Typical Performance Characteristics

Typical characteristics are provided at 25°C and V_DD=12V unless otherwise noted.

Figure 39. Rise and Fall Times vs. Temperature

Figure 40. Rise/Fall Waveforms with 1nF Load

Figure 41. Rise/Fall Waveforms with 10nF Load

Figure 42. Quasi-Static Source Current with

V_DD=12V

Figure 43. Quasi-Static Sink Current with V_DD=12V

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FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 • Rev. 1.0.0

15

Typical Performance Characteristics

Typical characteristics are provided at 25°C and V_DD=12V unless otherwise noted.

Figure 44. Quasi-Static Source Current with

Figure 45. Quasi-Static Sink Current with V_DD=8V

V_DD=8V

Note:

13. For any inverting inputs pulled low, non-inverting inputs pulled high, or outputs driven high, static I_DDincreases by

the current flowing through the corresponding pull-up/down resistor shown in the block diagram.

Test Circuit

Figure 46. Quasi-Static I_OUT/ V_OUTTest Circuit

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FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 • Rev. 1.0.0

16

Applications Information

Input Thresholds

MillerDrive™ Gate Drive Technology

FAN322x gate drivers incorporate the MillerDrive™

architecture shown in Figure 47. For the output stage, a

combination of bipolar and MOS devices provide large

currents over a wide range of supply voltage and

temperature variations. The bipolar devices carry the

bulk of the current as OUT swings between 1/3 to 2/3

V_DDand the MOS devices pull the output to the high or

low rail.

Each member of the FAN322x driver family consists of

two identical channels that may be used independently

at rated current or connected in parallel to double the

individual current capacity. In the FAN3226 and

FAN3227, channels A and B can be enabled or disabled

independently using ENA or ENB, respectively. The EN

pin has TTL thresholds for parts with either CMOS or

TTL input thresholds. If ENA and ENB are not

connected, an internal pull-up resistor enables the driver

channels by default. If the channel A and channel B

inputs and outputs are connected in parallel to increase

the driver current capacity, ENA and ENB should be

connected and driven together.

The purpose of the MillerDrive™ architecture is to

speed up switching by providing high current during the

Miller plateau region when the gate-drain capacitance of

the MOSFET is being charged or discharged as part of

the turn-on / turn-off process.

The FAN322x family offers versions in either TTL or

CMOS input thresholds. In the FAN322xT, the input

thresholds meet industry-standard TTL-logic thresholds

For applications that have zero voltage switching during

the MOSFET turn-on or turn-off interval, the driver

supplies high peak current for fast switching even

though the Miller plateau is not present. This situation

often occurs in synchronous rectifier applications

because the body diode is generally conducting before

the MOSFET is switched on.

independent of the V_DDvoltage, and there is

a

hysteresis voltage of approximately 0.4V. These levels

permit the inputs to be driven from a range of input logic

signal levels for which a voltage over 2V is considered

logic high. The driving signal for the TTL inputs should

have fast rising and falling edges with a slew rate of

6V/µs or faster, so a rise time from 0 to 3.3V should be

550ns or less. With reduced slew rate, circuit noise

could cause the driver input voltage to exceed the

hysteresis voltage and retrigger the driver input, causing

erratic operation.

The output pin slew rate is determined by V_DDvoltage

and the load on the output. It is not user adjustable, but

a series resistor can be added if a slower rise or fall time

at the MOSFET gate is needed.

V_DD

In the FAN322xC, the logic input thresholds are

dependent on the V_DDlevel and, with V_DDof 12V, the

logic rising edge threshold is approximately 55% of V_DD

and the input falling edge threshold is approximately

38% of V_DD. The CMOS input configuration offers a

hysteresis voltage of approximately 17% of V_DD. The

CMOS inputs can be used with relatively slow edges

(approaching DC) if good decoupling and bypass

techniques are incorporated in the system design to

prevent noise from violating the input voltage hysteresis

window. This allows setting precise timing intervals by

fitting an R-C circuit between the controlling signal and

the IN pin of the driver. The slow rising edge at the IN

pin of the driver introduces a delay between the

controlling signal and the OUT pin of the driver.

Input

stage

V_OUT

Figure 47. MillerDrive™ Output Architecture

Under-Voltage Lockout

Static Supply Current

The FAN322x startup logic is optimized to drive ground-

referenced N-channel MOSFETs with an under-voltage

lockout (UVLO) function to ensure that the IC starts up

in an orderly fashion. When V_DDis rising, yet below the

3.9V operational level, this circuit holds the output low,

regardless of the status of the input pins. After the part

is active, the supply voltage must drop 0.2V before the

part shuts down. This hysteresis helps prevent chatter

when low V_DDsupply voltages have noise from the

power switching. This configuration is not suitable for

driving high-side P-channel MOSFETs because the low

output voltage of the driver would turn the P-channel

MOSFET on with V_DDbelow 3.9V.

In the I_DD(static) typical performance characteristics

(see Figure 12 - Figure 14 and Figure 19 - Figure 21),

the curve is produced with all inputs / enables floating

(OUT is low) and indicates the lowest static I_DDcurrent

for the tested configuration. For other states, additional

current flows through the 100k resistors on the inputs

and outputs shown in the block diagram of each part

(see Figure 4 - Figure 7). In these cases, the actual

static I_DDcurrent is the value obtained from the curves

plus this additional current.

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FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 • Rev. 1.0.0

17

V_DDBypass Capacitor Guidelines

To enable this IC to turn a device on quickly, a local

high-frequency bypass capacitor C_BYPwith low ESR and

ESL should be connected between the VDD and GND

pins with minimal trace length. This capacitor is in

addition to bulk electrolytic capacitance of 10µF to 47µF

commonly found on driver and controller bias circuits.

.

The FAN322x is compatible with many other

industry-standard drivers. In single input parts with

enable pins, there is an internal 100k resistor tied

to V_DDto enable the driver by default; this should be

considered in the PCB layout.

The turn-on and turn-off current paths should be

minimized, as discussed in the following section.

A typical criterion for choosing the value of C_BYPis to

keep the ripple voltage on the V_DDsupply to ≤5%. This

is often achieved with a value ≥20 times the equivalent

Figure 48 shows the pulsed gate drive current path

when the gate driver is supplying gate charge to turn the

MOSFET on. The current is supplied from the local

bypass capacitor, C_BYP, and flows through the driver to

the MOSFET gate and to ground. To reach the high

peak currents possible, the resistance and inductance in

the path should be minimized. The localized C_BYPacts

to contain the high peak current pulses within this driver-

MOSFET circuit, preventing them from disturbing the

sensitive analog circuitry in the PWM controller.

load capacitance C_EQV, defined here as Q_GATE/V_DD

.

Ceramic capacitors of 0.1µF to 1µF or larger are

common choices, as are dielectrics, such as X5R and

X7R with good temperature characteristics and high

pulse current capability.

If circuit noise affects normal operation, the value of

C_BYPmay be increased to 50-100 times the C_EQV, or

C_BYPmay be split into two capacitors. One should be a

larger value, based on equivalent load capacitance, and

the other a smaller value, such as 1-10nF mounted

closest to the VDD and GND pins to carry the higher

frequency components of the current pulses. The

bypass capacitor must provide the pulsed current from

both of the driver channels and, if the drivers are

switching simultaneously, the combined peak current

sourced from the C_BYPwould be twice as large as when

a single channel is switching.

V_DD

V_DS

C_BYP

FAN322x

Layout and Connection Guidelines

PWM

The FAN3226-26 family of gate drivers incorporates

fast-reacting input circuits, short propagation delays,

and powerful output stages capable of delivering current

peaks over 2A to facilitate voltage transition times from

under 10ns to over 150ns. The following layout and

connection guidelines are strongly recommended:

Figure 48. Current Path for MOSFET Turn-on

.

Keep high-current output and power ground paths

separate logic and enable input signals and signal

ground paths. This is especially critical when

dealing with TTL-level logic thresholds at driver

inputs and enable pins.

Figure 49 shows the current path when the gate driver

turns the MOSFET off. Ideally, the driver shunts the

current directly to the source of the MOSFET in a small

circuit loop. For fast turn-off times, the resistance and

inductance in this path should be minimized.

.

Keep the driver as close to the load as possible to

minimize the length of high-current traces. This

reduces the series inductance to improve high-

speed switching, while reducing the loop area that

can radiate EMI to the driver inputs and

surrounding circuitry.

V_DD

V_DS

C_BYP

FAN322x

.

If the inputs to a channel are not externally

connected, the internal 100k resistors indicated

on block diagrams command a low output. In noisy

environments, it may be necessary to tie inputs of

an unused channel to VDD or GND using short

traces to prevent noise from causing spurious

output switching.

PWM

Many high-speed power circuits can be susceptible

to noise injected from their own output or other

external sources, possibly causing output re-

triggering. These effects can be obvious if the

circuit is tested in breadboard or non-optimal circuit

layouts with long input, enable, or output leads. For

best results, make connections to all pins as short

and direct as possible.

Figure 49. Current Path for MOSFET Turn-off

www.fairchildsemi.com

FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 • Rev. 1.0.0

18

Truth Table of Logic Operation

Operational Waveforms

The FAN3228/FAN3229 truth table indicates the

operational states using the dual-input configuration. In

a non-inverting driver configuration, the IN- pin should

be a logic low signal. If the IN- pin is connected to logic

high, a disable function is realized, and the driver output

remains low regardless of the state of the IN+ pin.

At power-up, the driver output remains low until the V_DD

voltage reaches the turn-on threshold. The magnitude of

the OUT pulses rises with V_DDuntil steady-state V_DDis

reached. The non-inverting operation illustrated in

Figure 52 shows that the output remains low until the

UVLO threshold is reached, the output is in-phase with

the input.

IN+

0

IN-

0

OUT

0

1

0

1

0

1

In the non-inverting driver configuration in Figure 50, the

IN- pin is tied to ground and the input signal (PWM) is

applied to IN+ pin. The IN- pin can be connected to logic

high to disable the driver and the output remains low,

regardless of the state of the IN+ pin.

Figure 52. Non-Inverting Startup Waveforms

For the inverting configuration of Figure 51, startup

waveforms are shown in Figure 53. With IN+ tied to V_DD

and the input signal applied to IN–, the OUT pulses are

inverted with respect to the input. At power-up, the

inverted output remains low until the V_DDvoltage

reaches the turn-on threshold, then it follows the input

with inverted phase.

Figure 50. Dual-Input Driver Enabled,

Non-Inverting Configuration

In the inverting driver application in Figure 51, the IN+

pin is tied high. Pulling the IN+ pin to GND forces the

output low, regardless of the state of the IN- pin.

Figure 51. Dual-Input Driver Enabled,

Inverting Configuration

Figure 53. Inverting Startup Waveforms

www.fairchildsemi.com

FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 • Rev. 1.0.0

19

Thermal Guidelines

Gate drivers used to switch MOSFETs and IGBTs at

high frequencies can dissipate significant amounts of

power. It is important to determine the driver power

dissipation and the resulting junction temperature in the

application to ensure that the part is operating within

acceptable temperature limits.

In the forward converter with synchronous rectifier

shown in the typical application diagrams, the

FDMS8660S is a reasonable MOSFET selection. The

gate charge for each SR MOSFET would be 60nC with

V_GS= V_DD= 7V. At a switching frequency of 500kHz, the

total power dissipation is:

The total power dissipation in a gate driver is the sum of

P

_GATE= 60nC • 7V • 500kHz • 2 = 0.42W

P_DYNAMIC= 3mA • 7V • 2 = 0.042W

_TOTAL= 0.462W

The SOIC-8 has

(5)

two components, P_GATEand P_DYNAMIC

:

(6)

(7)

P

_TOTAL= P_GATE+ P_DYNAMIC

(1)

P

Gate Driving Loss: The most significant power loss

results from supplying gate current (charge per unit

time) to switch the load MOSFET on and off at the

switching frequency. The power dissipation that

results from driving a MOSFET at a specified gate-

source voltage, V_GS, with gate charge, Q_G, at

switching frequency, F_SW, is determined by:

a

junction-to-board thermal

_JB

characterization parameter of

= 43°C/W. In a

system application, the localized temperature around

the device is a function of the layout and construction of

the PCB along with airflow across the surfaces. To

ensure reliable operation, the maximum junction

temperature of the device must be prevented from

exceeding the maximum rating of 150°C; with 80%

derating, T_Jwould be limited to 120°C. Rearranging

Equation 4 determines the board temperature required

to maintain the junction temperature below 120°C:

P

_GATE= Q_G• V_GS• F_SW• n

n is the number of driver channels in use (1 or 2).

Dynamic Pre-drive Shoot-through Current:

(2)

/

A

power loss resulting from internal current

consumption under dynamic operating conditions,

including pin pull-up / pull-down resistors, can be

obtained using the “I_DD(No-Load) vs. Frequency”

graphs in Typical Performance Characteristics to

determine the current I_DYNAMICdrawn from V_DD

under actual operating conditions:



T_B= T_J- P_TOTAL

•

(8)

(9)

JB

T_B= 120°C – 0.462W • 43°C/W = 100°C

P

_DYNAMIC= I_DYNAMIC• V_DD• n

(3)

Once the power dissipated in the driver is determined,

the driver junction rise with respect to circuit board can

be evaluated using the following thermal equation,

_JB

assuming

was determined for a similar thermal

design (heat sinking and air flow):



T_J= P_TOTAL

where:

•

_JB+ T_B

(4)

T_J

= driver junction temperature

_JB

= (psi) thermal characterization parameter

relating temperature rise to total power

dissipation

T_B= board temperature in location defined in Note

1 under Thermal Resistance table.

www.fairchildsemi.com

FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 • Rev. 1.0.0

20

Typical Application Diagrams

Figure 54. Forward Converter

with Synchronous Rectification

Figure 55.

Primary-Side Dual Driver

in a Push-Pull Converter

V_IN

FAN3227

8

7

6

5

1

2

3

4

ENA

ENB

PWM-A

A

B

GND

VDD

PWM-B

Vbias

FAN3227

8

7

6

5

1

2

3

4

ENA

ENB

PWM-C

PWM-D

A

B

Phase Shift

Controller

Vbias

GND

VDD

Figure 56. Phase-Shifted Full-Bridge with Two Gate Drive Transformers (Simplified)

FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 • Rev. 1.0.0

www.fairchildsemi.com

21

Table 1.


型号：	FAN3229CMX_12
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	Dual 2A High-Speed, Low-Side Gate Drivers 双路2A高速，低侧栅极驱动器驱动器栅极栅极驱动
文件：	总24页 (文件大小：1522K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

FAN3229CMX_12 [FAIRCHILD]

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