FAN4800ASNY [FAIRCHILD]
PFC/PWM Controller Combination; PFC / PWM控制器组合
| 型号： | FAN4800ASNY |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | PFC/PWM Controller Combination |
| 文件： | 总19页 (文件大小：577K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
December 2010
FAN4800AS/CS/01S/2S
PFC/PWM Controller Combination
Features
Description
The highly integrated FAN4800AS/CS/01S/02S parts
are specially designed for power supplies that consist of
boost PFC and PWM. They require very few external
Pin-to-Pin Compatible with ML4800 and FAN4800
and CM6800 and CM6800A
PWM Configurable for Current Mode or
Feedforward Voltage-Mode Operation
components to achieve versatile protections
/
compensation. They are available in 16-pin DIP and
SOP packages.
Internally Synchronized Leading-Edge PFC and
Trailing-Edge PWM in One IC
The PWM can be used in either current or voltage
mode. In voltage mode, feed-forward from the PFC
output bus can reduce the secondary output ripple.
Low Operating Current
Innovative Switching-Charge Multiplier Divider
Average-Current Mode for Input-Current Shaping
PFC Over-Voltage and Under-Voltage Protections
PFC Feedback Open-Loop Protection
Cycle-by-Cycle Current Limiting for PFC/PWM
Power-on Sequence Control and Soft-Start
Brownout Protection
Compared with older productions, ML4800 and
FAN4800,
FAN4800AS/CS/01S/02S
have
lower
operation current that saves power consumption in
external devices. FAN4800AS/CS/01S/02S have
accurate 49.9% maximum duty of PWM that makes the
hold-up time longer. Brownout protection and PFC soft-
start functions available in this series are not available
in ML4800 and FAN4800.
To evaluate FAN4800AS/CS/01S/02S for replacing
existing FAN4800 and ML4800 boards, five things must
be completed before the fine-tuning procedure:
Interleaved PFC/PWM Switching
Improved Efficiency at Light Load
1. Change RAC resister from the old value to a higher
fRTCT=4•fPFC=4•fPWM for FAN4800AS/01S
fRTCT=4•fPFC=2•fPWM for FAN4800CS/02S
resister: between 6MΩ to 8MΩ.
2. Change RT/CT pin from the existing values to
RT=6.8kΩ and CT=1000pF to have fPFC=64kHz and
f
PWM=64kHz.
Applications
3. The VRMS pin needs to be 1.224V at VIN=85 VAC
for universal input application from line input from
Desktop PC Power Supply
85VAC to 270VAC
.
Internet Server Power Supply
LCD TV, Monitor Power Supply
UPS
4. At full load, the average VVEA needs to be ~4.5V
and the ripple of VVEA needs to be less than
400mV.
Battery Charger
5. For the Soft-Start pin, the soft-start current has
been reduced to half the FAN4800 capacitor.
DC Motor Power Supply
Monitor Power Supply
Telecom System Power Supply
Distributed Power
There are two differences from FAN4800A/C/01/02 to
FAN4800AS/CS/01S/02S:
1. Under-voltage protection debounce time is
extended to one second.
2. PWM gate clamp voltage is raised to 19V.
Related Resources
AN-8027 - FAN480X PFC+PWM Combination
Controller Application
© 2010 Fairchild Semiconductor Corporation
FAN4800AS/CS/01S/02S • Rev. 1.0.1
www.fairchildsemi.com
Ordering Information
Part Number Operating Temperature Range
Package
Packing Method
Tube
FAN4800ASNY
FAN4800ASMY
FAN4800CSNY
FAN4800CSMY
FAN4801SNY
FAN4801SMY
FAN4802SNY
FAN4802SMY
-40°C to +105°C
-40°C to +105°C
-40°C to +105°C
-40°C to +105°C
-40°C to +105°C
-40°C to +105°C
-40°C to +105°C
-40°C to +105°C
16-Pin Dual Inline Package (DIP)
16-Pin Small Outline Package (SOP)
16-Pin Dual Inline Package (DIP)
16-Pin Small Outline Package (SOP)
16-Pin Dual Inline Package (DIP)
16-Pin Small Outline Package (SOP)
16-Pin Dual Inline Package (DIP)
16-Pin Small Outline Package (SOP)
Tape & Reel
Tube
Tape & Reel
Tube
Tape & Reel
Tube
Tape & Reel
Application Diagram
Figure 1. Typical Application, Current Mode
© 2010 Fairchild Semiconductor Corporation
FAN4800AS/CS/01S/02S • Rev. 1.0.1
www.fairchildsemi.com
2
Application Diagram
VEA
FBPFC
VREF
IEA
IAC
ISENSE
VRMS
SS
VDD
VDD
OPFC
OPWM
GND
FBPWM
RT/CT
RAMP
ILIMIT
VREF
VREF
Figure 2. Typical Application, Voltage Mode
© 2010 Fairchild Semiconductor Corporation
FAN4800AS/CS/01S/02S • Rev. 1.0.1
www.fairchildsemi.com
3
Block Diagram
Figure 3.
FAN4800AS/CS Function Block Diagram
Figure 4.
FAN4801S/02S Function Block Diagram
© 2010 Fairchild Semiconductor Corporation
FAN4800AS/CS/01S/02S • Rev. 1.0.1
www.fairchildsemi.com
4
Marking Information
F – Fairchild Logo
Z – Plant Code
X – 1-Digit Year Code
YY – 2-Digit Week Code
TT – 2-Digit Die-Run Code
T – Package Type (N:DIP)
P – Y: Green Package
M – Manufacture Flow Code
Figure 5.
DIP Top Mark
F – Fairchild Logo
Z – Plant Code
X – 1-Digit Year Code
Y – 1-Digit Week Code
TT – 2-Digit Die-Run Code
T – Package Type (M:SOP)
P – Y: Green Package
M – Manufacture Flow Code
Figure 6.
SOP Top Mark
© 2010 Fairchild Semiconductor Corporation
FAN4800AS/CS/01S/02S • Rev. 1.0.1
www.fairchildsemi.com
5
Pin Configuration
Figure 7.
Pin Configuration (Top View)
Pin Definitions
Pin #
Name Description
Output of PFC Current Amplifier. The signal from this pin is compared with an internal
sawtooth to determine the pulse width for PFC gate drive.
1
IEA
IAC
Input AC Current. For normal operation, this input provides current reference for the multiplier.
The suggested maximum IAC is 100µA.
2
PFC Current Sense. The non-inverting input of the PFC current amplifier and the output of
multiplier and PFC ILIMIT comparator.
3
4
ISENSE
VRMS
Line-Voltage Detection. The pin is used for the PFC multiplier.
PWM Soft-Start. During startup, the SS pin charges an external capacitor with a 10µA
constant current source. The voltage on FBPWM is clamped by SS during startup. If a
protection condition occurs and/or PWM is disabled, the SS pin is quickly discharged.
5
SS
6
7
FBPWM PWM Feedback Input. The control input for voltage-loop feedback of PWM stage.
RT/CT
Oscillator RC Timing Connection. Oscillator timing node; timing set by RT and CT.
PWM RAMP Input. In current mode, this pin functions as the current-sense input; when in
voltage mode, it is the feedforward sense input from PFC output 380V (feedforward ramp).
8
RAMP
9
ILIMIT
GND
Peak Current Limit Setting for PWM. The peak current limits setting for PWM.
Ground.
10
PWM Gate Drive. The totem-pole output drive for PWM MOSFET. This pin is internally
clamped under 19V to protect the MOSFET.
11
12
OPWM
OPFC
PFC Gate Drive. The totem-pole output drive for PFC MOSFET. This pin is internally clamped
under 15V to protect the MOSFET.
Supply. The power supply pin. The threshold voltages for startup and turn-off are 11V and
9.3V, respectively. The operating current is lower than 10mA.
13
14
15
VDD
VREF
FBPFC
Reference Voltage. Buffered output for the internal 7.5V reference.
Voltage Feedback Input for PFC. The feedback input for PFC voltage loop. The inverting
input of PFC error amplifier. This pin is connected to the PFC output through a divider network.
Output of PFC Voltage Amplifier. The error amplifier output for PFC voltage feedback loop.
A compensation network is connected between this pin and ground.
16
VEA
© 2010 Fairchild Semiconductor Corporation
FAN4800AS/CS/01S/02S • Rev. 1.0.1
www.fairchildsemi.com
6
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only.
Symbol
VDD
Parameter
Min.
Max.
30
Unit
V
DC Supply Voltage
SS, FBPWM, RAMP, OPWM, OPFC, VREF
IAC, VRMS, RT/CT, ILIMIT, FBPFC, VEA
IEA
VH
-0.3
-0.3
0
30.0
7.0
V
VL
V
VIEA
VN
VVREF+0.3
0.7
V
ISENSE
-5.0
V
IAC
Input AC Current
1
mA
mA
A
IREF
VREF Output Current
5
IPFC-OUT
Peak PFC OUT Current, Source or Sink
0.5
IPWM-OUT Peak PWM OUT Current, Source or Sink
0.5
A
PD
Power Dissipation TA < 50°C
800
mW
DIP
80.80
104.10
35.38
40.41
+125
+150
+260
5.0
ΘJA
Thermal Resistance (Junction to Air)
°C/W
°C/W
SOP
DIP
ΘJC
Thermal Resistance (Junction to Case)
SOP
TJ
TSTG
TL
Operating Junction Temperature
Storage Temperature Range
Lead Temperature(Soldering)
-40
-55
°C
°C
°C
Human Body Model
ESD
Electrostatic Discharge Capability
kV
Charged Device Model
1.5
Notes:
1. All voltage values, except differential voltage, are given with respect to GND pin.
2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Min.
Typ.
Max.
Unit
TA
Operating Ambient Temperature
-40
+105
°C
© 2010 Fairchild Semiconductor Corporation
FAN4800AS/CS/01S/02S • Rev. 1.0.1
www.fairchildsemi.com
7
Electrical Characteristics
Unless otherwise noted, VDD=15V, TA= 25°C, TA=TJ, RT=6.8kΩ, and CT=1000pF.
Symbol
Parameter
Conditions
Min. Typ. Max. Unit
VDD Section
VDD-OP
Continuously Operating Voltage
Startup Current
26
80
V
VDD=VTH-ON-0.1V; OPFC OPWM
Open
IDD ST
30
µA
IDD-OP
VTH-ON
Operating Current
Turn-on Threshold Voltage
Hysteresis
VDD=13V; OPFC OPWM Open
2.0
10
2.6
11
5.0
12
mA
V
1.3
27
1.9
29
V
ΔVTH
VDD-OVP
ΔVDD-OVP
Oscillator
fOSC-RT/CT
fOSC
VDD OVP
28
1
V
VDD OVP Hysteresis
V
RT/CT Frequency
RT=6.8kΩ, CT=1000pF
RT=6.8kΩ, CT=1000pF
240
60
256
64
268
67
134
2
kHz
kHz
PFC & PWM Frequency
PWM Frequency
Voltage Stability(3)
120
128
11V ≦ VDD ≦ 22V
fDV
fDT
%
%
Temperature Stability(3)
-40°C ~ +105°C
2
fTV
Total Variation (PFC & PWM)(3) Line, Temperature
58
70
kHz
V
fRV
Ramp Voltage
Valley to Peak
2.8
IOSC-DIS
fRANGE
tPFC-DEAD
VREF
Discharge Current
Frequency Range
PFC Dead Time
VRAMP=0V, VRT/CT=2.5V
6.5
50
15.0
75
mA
kHz
ns
RT = 6.8kΩ, CT = 1000pF
400
600
800
VVREF
Reference Voltage
IREF=0mA, CREF=0.1µF
7.4
7.5
30
7.6
50
V
Load Regulation of Reference
Voltage
CREF=0.1µF, IREF=0mA to 3.5mA
mV
ΔVVREF1
ΔVVREF2
VVDD=14V, Rise/Fall Time > 20µs
Line Regulation of Reference
Voltage
CREF=0.1µF, VVDD=11V to 22V
25
mV
Temperature Stability(3)
Total Variation(3)
Long-Term Stability(3)
-40°C ~ +105°C
0.4
0.5
7.65
25
%
V
ΔVVREF-DT
ΔVVREF-TV
ΔVVREF-LS
IREF-MAX
Line, Load, Temp
TJ=125°C, 0 ~ 1000HRs
VVREF > 7.35V
7.35
5
mV
mA
Maximum Current
5
PFC OVP Comparator
VPFC-OVP
Over-Voltage Protection
PFC OVP Hysteresis
2.70
200
2.75
250
2.80
300
V
mV
ΔVPFC-OVP
Low-Power Detect Comparator
VVEAOFF
VEA Voltage OFF OPFC
0.2
0.3
0.4
V
VIN OK Comparator
Voltage Level on FBPFC to
Enable OPWM During Startup
VRD-FBPFC
2.3
2.4
2.5
V
V
Hysteresis
1.15
1.25
1.35
ΔVRD-FBPFC
Continued on the following page…
© 2010 Fairchild Semiconductor Corporation
FAN4800AS/CS/01S/02S • Rev. 1.0.1
www.fairchildsemi.com
8
Electrical Characteristics (Continued)
Unless otherwise noted, VDD=15V, TA= 25°C, TA=TJ, RT=6.8kΩ, and CT=1000pF.
Symbol
Parameter
Conditions
Min. Typ. Max. Unit
Voltage Error Amplifier
VREF
AV
Reference Voltage
Open-Loop Gain(3)
2.45
35
2.50
42
2.55
90
V
dB
umho
µA
µA
µA
V
Gmv
Transconductance
VNONINV=VINV, VVEA=3.75V
VFBPFC=2V, VVEA=1.5V
VFBPFC=3V, VVEA=6V
50
70
IFBPFC-L
IFBPFC-H
IBS
Maximum Source Current
Maximum Sink Current
Input Bias Current
40
50
-50
-40
1
-1
VVEA-H
VVEA-L
Output High Voltage on VVEA
Output Low Voltage on VVEA
5.8
6.0
0.1
0.4
V
Current Error Amplifier
GmI
VOFFSET
VIEA-H
VIEA-L
IL
Transconductance
VNONINV=VINV, VIEA=3.75V
VVEA=0V, IAC Open
78
-10
6.8
88
100
10
umho
mV
V
Input Offset Voltage
Output High Voltage
Output Low Voltage
Source Current
7.4
0.1
50
8.0
0.4
V
VISENSE=-0.6V, VIEA=1.5V
VISENSE=+0.6V, VIEA=4.0V
35
40
µA
µA
dB
IH
AI(3)
Sink Current
-50
50
-35
Open-Loop Gain
TriFault Detect™
VFBPFC=VPFC-UVP to FBPFC OPEN,
470pF from FBPFC to GND
tFBPFC_OPEN Time to FBPFC Open
2
4
ms
V
PFC Feedback Under-Voltage
Protection
VPFC-UVP
0.4
0
0.5
0.6
Gain Modulator
IAC
Input for AC Current(3)
Multiplier Linear Range
100
µA
I
V
AC=17.67µA, VRMS=1.080V
FBPFC=2.25V
7.500 9.000 10.500
6.367 7.004 7.704
3.801 4.182 4.600
0.950 1.045 1.149
IAC=20.00µA, VRMS=1.224V
FBPFC=2.25V
V
IAC=25.69µA, VRMS=1.585V
FBPFC=2.25V
GAIN
GAIN Modulator(4)
V
IAC=51.62µA, VRMS=3.169V
FBPFC=2.25V
V
IAC=62.23µA, VRMS=3.803V
FBPFC=2.25V
0.660 0.726 0.798
2
V
BW
Bandwidth(3)
IAC=40µA
kHz
V
Output Voltage=5.7kΩ × (ISENSE
-
IAC=20µA, VRMS=1.224V
VFBPFC=2.25V
VO(gm)
0.710 0.798 0.885
IOFFSET
)
PFC ILIMIT Comparator
Peak Current Limit Threshold
Voltage, Cycle-by-Cycle Limit
VPFC-ILIMIT
-1.35 -1.20 -1.05
200
V
IAC=17.67µA, VRMS=1.08V
PFC ILIMIT-Gain Modulator Output
mV
ΔVPK
VFBPFC=2.25V
Continued on the following page…
© 2010 Fairchild Semiconductor Corporation
FAN4800AS/CS/01S/02S • Rev. 1.0.1
www.fairchildsemi.com
9
Electrical Characteristics (Continued)
Unless otherwise noted, VDD=15V, TA= 25°C, TA=TJ, RT=6.8kΩ, and CT=1000pF.
Symbol
Parameter
Conditions
Min. Typ. Max. Unit
PFC Output Driver
VGATE-CLAMP Gate Output Clamping Voltage
VDD=22V
13
15
17
V
V
V
VGATE-L
VGATE-H
Gate Low Voltage
Gate High Voltage
VDD=15V, IO = 100mA
VDD=13V, IO = 100mA
1.5
8
VDD=15V, CL=4.7nF,
O/P= 2V to 9V
tR
tF
Gate Rising Time
Gate Falling Time
40
70
120
110
ns
ns
VDD=15V; CL=4.7nF,
O/P= 9V to 2V
40
94
60
97
DPFC-MAX
DPFC-MIN
Maximum Duty Cycle
Minimum Duty Cycle
VIEA<1.2V
VIEA>4.5V
%
%
0
Brownout
VRMS-UVL
VRMS Threshold Low
VRMS Threshold High
When VRMS=1.05V at 75VRMS
When VRMS=1.9V at 85•1.414
1.03
1.88
750
1.05
1.90
850
1.08
1.94
950
V
V
VRMS-UVH
VRMS-UVP Hysteresis
mV
Under Voltage Protection
Debounce Time
tUVP
850
1000
1150
ms
Soft Start
VSS-MAX
ISS
Maximum Voltage
Soft-Start Current
VDD=15V
9.5
10.0
10
10.5
V
µA
PWM ILIMIT Comparator
VPWM-ILIMIT Threshold Voltage
0.95
170
1.00
250
250
1.05
350
V
tPD
Propagation Delay to Output
Leading-Edge Blanking Time
ns
ns
tPWM-BNK
Range (FAN4801S/02S)
VVRMS-L RMS AC Voltage Low
VVRMS-H
When VVRMS =1.95V at 132VRMS
When VVRMS =2.45V at 150VRMS
V
V
1.90
2.40
1.95
2.45
2.00
2.50
RMS AC Voltage High
VEA LOW
When VVEA= 1.95V at 30%
Loading
VVEA-L
V
1.90
1.95
2.00
When VVEA= 2.45V at 40%
Loading
VVEA-H
ITC
V
VEA HIGH
2.40
18
2.45
20
2.50
22
µA
Source Current from FBPFC
PWM Output Driver
VGATE-CLAMP Gate Output Clamping Voltage
VDD=22V
18
19
20
V
V
VGATE-L
VGATE-H
tR
Gate Low Voltage
VDD=15V, IO=100mA
VDD=13V, IO=100mA
VDD=15V, CL=4.7nF
VDD=15V, CL=4.7nF
1.5
Gate High Voltage
8
30
V
Gate Rising Time
60
50
120
110
50.0
1.8
ns
ns
%
V
tF
Gate Falling Time
30
DPWM-MAX
VPWM-LS
Notes:
3. This parameter, although guaranteed by design, is not 100% production tested.
4. This GAIN is the maximum gain of modulation with a given VRMS voltage when VVEA is saturated to HIGH.
Maximum Duty Cycle
49.0
49.5
PWM Comparator Level Shift
1.3
1.5
© 2010 Fairchild Semiconductor Corporation
FAN4800AS/CS/01S/02S • Rev. 1.0.1
www.fairchildsemi.com
10
Typical Characteristics
20.0
18.0
16.0
14.0
12.0
10.0
8.0
28.04
28.02
28.00
27.98
27.96
27.94
27.92
27.90
27.88
27.86
6.0
4.0
2.0
0.0
-40℃ -25℃ -10℃ 5℃
20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
-40℃ -25℃ -10℃ 5℃
20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
Figure 8.
IDD-ST vs. Temperature
Figure 9.
VDD-OVP vs. Temperature
65.0
7.520
7.515
7.510
7.505
7.500
7.495
7.490
7.485
7.480
7.475
64.9
64.8
64.7
64.6
64.5
64.4
64.3
64.2
-40℃ -25℃ -10℃ 5℃
20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
-40℃ -25℃ -10℃ 5℃
20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
Figure 10. fOSC vs. Temperature
Figure 11. VVREF vs. Temperature
2.742
2.740
2.738
2.736
2.734
2.732
2.730
2.502
2.500
2.498
2.496
2.494
2.492
2.490
2.488
-40℃ -25℃ -10℃ 5℃
20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
-40℃ -25℃ -10℃ 5℃
20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
Figure 12. VPFC-OVP vs. Temperature
Figure 13. VREF vs. Temperature
74
73
73
72
72
71
94
92
90
88
86
84
82
80
78
-40℃ -25℃ -10℃
5℃
20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
-40℃ -25℃ -10℃ 5℃
20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
Figure 14. GmV vs. Temperature
Figure 15. GmI vs. Temperature
-1.177
-1.178
-1.179
-1.180
-1.181
-1.182
-1.183
1.010
1.009
1.008
1.007
1.006
1.005
1.004
1.003
1.002
-40℃ -25℃ -10℃ 5℃
20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
-40
-25
-10
5
20
35
50
65
80
95
110
125
Figure 16. VPFC-ILIMIT vs. Temperature
Figure 17. VPWM-ILIMIT vs. Temperature
© 2010 Fairchild Semiconductor Corporation
FAN4800AS/CS/01S/02S • Rev. 1.0.1
www.fairchildsemi.com
11
Typical Characteristics
1.048
1.047
1.046
1.045
1.044
1.043
1.042
1.041
1.040
1.039
1.038
867.5
867.0
866.5
866.0
865.5
865.0
864.5
864.0
863.5
863.0
862.5
862.0
-40℃ -25℃ -10℃ 5℃
20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
Figure 18. VRMS-UVP vs. Temperature
Figure 19. ΔVRMS-UVP vs. Temperature
14.7
19.00
18.95
18.90
18.85
18.80
18.75
18.70
18.65
18.60
18.55
18.50
14.6
14.5
14.4
14.3
14.2
14.1
14.0
13.9
-40℃ -25℃ -10℃ 5℃
20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
Figure 20. VGATE-CLAMP-PFC vs. Temperature
Figure 21. VGATE-CLAMP-PWM vs. Temperature
96.06
49.80
96.04
96.02
96.00
95.98
95.96
95.94
95.92
95.90
95.88
49.75
49.70
49.65
49.60
49.55
49.50
-40℃ -25℃ -10℃ 5℃
20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
-40℃ -25℃ -10℃ 5℃
20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
Figure 22. DPFC-MAX vs. Temperature
Figure 23. DPWM-MAX vs. Temperature
10.1
10.0
9.9
9.8
9.7
9.6
9.5
9.4
9.3
9.2
9.1
21.0
20.8
20.6
20.4
20.2
20.0
19.8
19.6
19.4
-40℃ -25℃ -10℃
5℃
20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
-40℃ -25℃ -10℃ 5℃
20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
Figure 24. ISS vs. Temperature
Figure 25. ITC vs. Temperature
© 2010 Fairchild Semiconductor Corporation
FAN4800AS/CS/01S/02S • Rev. 1.0.1
www.fairchildsemi.com
12
Functional Description
The FAN4800AS/CS/01S/02S consist of an average
current controlled, continuous-boost, Power Factor
Correction (PFC) front-end and a synchronized Pulse
Width Modulator (PWM) back-end. The PWM can be
used in current or voltage mode. In voltage mode,
feedforward from the PFC output bus can help improve
the line regulation of PWM. In either mode, the PWM
stage uses conventional trailing-edge, duty-cycle
modulation. This proprietary leading / trailing edge
modulation results in a higher usable PFC error amplifier
bandwidth and can significantly reduce the size of the
PFC DC bus capacitor.
IAC
×
VEA − 0.7
)
× K
IGAINMOD
=
(1)
VRMS2
Note that the output current of the gain modulator is
limited around 159μA and the maximum output voltage
of the gain modulator is limited to 159μA x 5.7k=0.906V.
This 0.906V also determines the maximum input power.
However, IGAINMOD cannot be measured directly from
ISENSE. ISENSE=IGAINMOD – IOFFSET and IOFFSET can only
be measured when VVEA is less than 0.5V and IGAINMOD
is 0A. Typical IOFFSET is around 31μA ~ 48μA.
Selecting RAC for the IAC Pin
The synchronization of the PWM with the PFC simplifies
the PWM compensation due to the controlled ripple on
the PFC output capacitor (the PWM input capacitor).
The IAC pin is the input of the gain modulator and also
a current mirror input that requires current input.
Selecting a proper resistor, RAC, provides a good sine
wave current derived from the line voltage and helps
program the maximum input power and minimum input
line voltage. RAC=VIN peak x 56kΩ. For example, if the
minimum line voltage is 75VAC, the RAC=75 x 1.414 x
56kΩ=6MΩ.
In addition to power factor correction, a number of
protection features are built into this series. They
include soft-start, PFC over-voltage protection, peak
current limiting, brownout protection, duty cycle limiting,
and under-voltage lockout (UVLO).
Gain Modulator
Current Amplifier Error, IEA
The gain modulator is the heart of the PFC, as the
circuit block controls the response of the current loop to
line voltage waveform and frequency, RMS line voltage,
and PFC output voltages. There are three inputs to the
gain modulator:
The current error amplifier’s output controls the PFC
duty cycle to keep the average current through the
boost inductor a linear function of the line voltage. At
the inverting input to the current error amplifier, the
output current of the gain modulator is summed with a
current, which results in a negative voltage being
impressed upon the ISENSE pin.
1. A current representing the instantaneous input
voltage (amplitude and wave shape) to the PFC. The
rectified AC input sine wave is converted to a
proportional current via a resistor and is fed into the
gain modulator at IAC. Sampling current in this way
minimizes ground noise, required in high-power,
switching-power conversion environments. The gain
modulator responds linearly to this current.
The negative voltage on ISENSE represents the sum of
all currents flowing in the PFC circuit and is typically
derived from a current-sense resistor in series with the
negative terminal of the input bridge rectifier.
The inverting input of the current error amplifier is a
virtual ground. Given this fact, and the arrangement of
the duty cycle modulator polarities internal to the PFC,
an increase in positive current from the gain modulator
causes the output stage to increase its duty cycle until
the voltage on ISENSE is adequately negative to cancel
this increased current. Similarly, if the gain modulator’s
output decreases, the output duty cycle decreases to
achieve a less negative voltage on the ISENSE pin.
2. A voltage proportional to the long-term RMS AC line
voltage, derived from the rectified line voltage after
scaling and filtering. This signal is presented to the
gain modulator at VRMS. The output of the gain
modulator is inversely proportional to VRMS (except at
unusually low values of VRMS, where special gain
contouring takes over to limit power dissipation of the
circuit components under brownout conditions).
PFC Cycle-By-Cycle Current Limiter
3. The output of the voltage error amplifier, VEA. The
gain modulator responds linearly to variations in VVEA
.
In addition to being a part of the current feedback loop,
the ISENSE pin is a direct input to the cycle-by-cycle
current limiter for the PFC section. If the input voltage at
this pin is less than -1.15V, the output of the PFC is
disabled until the protection flip-flop is reset by the clock
pulse at the start of the next PFC power cycle.
The output of the gain modulator is a current signal, in
the form of a full wave rectified sinusoid at twice the line
frequency. This current is applied to the virtual ground
(negative) input of the current error amplifier. In this way,
the gain modulator forms the reference for the current
error loop and ultimately controls the instantaneous
current draw of the PFC from the power line. The
general form of the output of the gain modulator is:
© 2010 Fairchild Semiconductor Corporation
FAN4800AS/CS/01S/02S • Rev. 1.0.1
www.fairchildsemi.com
13
TriFault Detect™
Error Amplifier Compensation
To improve power supply reliability, reduce system The PWM loading of the PFC can be modeled as a
component count, and simplify compliance to UL1950 negative resistor because an increase in the input
safety standards; the FAN4800AS/CS/01S/02S includes voltage to the PWM causes a decrease in the input
TriFault Detect™ technology. This feature monitors current. This response dictates the proper compensation
FBPFC for certain PFC fault conditions.
of the two transconductance error amplifiers. Figure 26
shows the types of compensation networks most
commonly used for the voltage and current error
amplifiers, along with their respective return points. The
current-loop compensation is returned to VREF to
produce a soft-start characteristic on the PFC. As the
reference voltage increases from 0V, it creates a
differentiated voltage on IEA, which prevents the PFC
from immediately demanding a full duty cycle on its
boost converter. Complete design is discussed in
application note AN-6078SC.
In a feedback path failure, the output of the PFC could
exceed safe operating limits. With such a failure, FBPFC
exceeds its normal operating area. Should FBPFC go too
low, too high, or open; TriFault Detect™ senses the error
and terminates the PFC output drive.
TriFault Detect is an entirely internal circuit. It requires no
external components to serve its protective function.
PFC Over-Voltage Protection
There is an RC filter between Rsense and ISENSE pin.
There are two reasons to add a filter at the ISENSE pin:
In the FAN4800AS/CS/01S/02S, the PFC OVP
comparator serves to protect the power circuit from being
subjected to excessive voltages if the load changes
suddenly. A resistor divider from the high-voltage DC
output of the PFC is fed to FBPFC. When the voltage on
FBPFC exceeds 2.75V, the PFC output driver is shut
down. The PWM section continues to operate. The OVP
comparator has 250mV of hysteresis and the PFC does
not restart until the voltage at FBPFC drops below 2.5V.
VDD OVP can also serve as a redundant PFC OVP
protection. VDD OVP threshold is 28V with 1V hysteresis.
1. Protection: During startup or inrush current conditions,
there is a large voltage across Rsense, the sensing
resistor of the PFC boost converter. It requires the
I
SENSE filter to attenuate the energy.
2. To reduce inductance, L, the boost inductor. The
ISENSE filter also can reduce the boost inductor value
since the ISENSE filter behaves like an integrator before
the ISENSE pin, which is the input of the current error
amplifier, IEA.
Selecting PFC Rsense
The ISENSE filter is an RC filter. The resistor value of the
ISENSE filter is between 100Ω and 50Ω because IOFFSET
x
Rsense is the sensing resistor of the PFC boost converter.
During the steady state, line input current x Rsense equals
RFILTER can generate a negative offset voltage of IEA.
Selecting an RFILTER equal to 50Ω keeps the offset of the
IEA less than 3mV. Design the pole of the ISENSE filter at
I
GAINMOD x 5.7kΩ.
At full load, the average VVEA needs to around 4.5V and
ripple on the VEA pin needs to be less than 400mV.
Choose the resistance of the sensing resistor:
f
PFC/6, one sixth of the PFC switching frequency, so the
boost inductor can be reduced six times without
disturbing the stability. The capacitor of the ISENSE filter,
CFILTER, is approximately 100nF.
4.5 − 0.7 × 5.7KΩ × IAC ×Gain ×V
× 2
(
=
IN
R
(2)
SENSE
2× 5.6 − 0.7 × Line _Input _Power
(
)
where 5.6 is VVEA maximum output voltage.
PFC Soft-Start
PFC startup is controlled by VVEA level. Before the
FBPFC voltage reaches 2.4V, the VVEA level is around
2.8V. At 90VAC, the PFC soft-start time is 90ms.
PFC Brownout
The AC UVP comparator monitors the AC input voltage.
The PFC is disabled as AC input lowers, causing VRMS to
be less than 1.05V.
Figure 26. Compensation Network Connection for
the Voltage and Current Error Amplifiers
© 2010 Fairchild Semiconductor Corporation
FAN4800AS/CS/01S/02S • Rev. 1.0.1
www.fairchildsemi.com
14
Two-Level PFC Function
Pulse Width Modulator (PWM)
To improve the efficiency, the system can reduce PFC
switching loss at low line and light load by reducing the
PFC output voltage. The two-level PFC output of the
FAN4801S/02S can be programmable.
The operation of the PWM section is straightforward,
but there are several points that should be noted.
Foremost among these is the inherent synchronization
of PWM with the PFC section of the device, from which
it also derives its basic timing. The PWM is capable of
current-mode or voltage-mode operation. In current-
mode applications, the PWM ramp (RAMP) is usually
derived directly from a current-sensing resistor or
current transformer in the primary side of the output
stage. It is thereby representative of the current flowing
in the converter’s output stage. ILIMIT, which provides
cycle-by-cycle current limiting, is typically connected to
RAMP in such applications. For voltage-mode
operation and certain specialized applications, RAMP
can be connected to a separate RC timing network to
generate a voltage ramp against which FBPWM is
compared. Under these conditions, the use of voltage
feedforward from the PFC bus can assist in line
regulation accuracy and response. As in current-mode
operation, the ILIMIT input is used for output stage over-
current protection. No voltage error amplifier is included
in the PWM stage, as this function is generally
performed on the output side of the PWM’s isolation
boundary. To facilitate the design of opto-coupler
feedback circuitry, an offset has been built into the
PWM’s RAMP input that allows FBPWM to command a
0% duty cycle for input voltages below typical 1.5V.
As Figure 27 shows, FAN4801S/02S detect the voltage
of VEA and VRMS pins to determine if the system
operates low line and light load. At the second-level
PFC, there is a current of 20µA through RF2 from the
FBPFC pin. The second-level PFC output voltage can
be calculated as.
R
+ R
F2
F1
Output ≅
× 2.5V − 20μA × R
(
F2
)
(3)
R
F2
For example, if the second-level PFC output voltage is
expected as 300V and normal voltage is 387V,
according to the equation, RF2 is 28kΩ RF1 is 4.3MΩ.
The programmable range of second level PFC output
voltage is 340V ~ 300V.
PWM Cycle-by-Cycle Current Limiter
The ILIMIT pin is a direct input to the cycle-by-cycle
current limiter for the PWM section. Should the input
voltage at this pin exceed 1V, the output flip-flop is reset
by the clock pulse at the start of the next PWM power
cycle. When the ILIMIT triggers the cycle-by-cycle bi-cycle
current, it limits the PWM duty cycle mode and the power
dissipation is reduced during the dead-short condition.
Figure 27. Two-Level PFC Scheme
Oscillator (RT/CT)
The oscillator frequency is determined by the values of
RT and CT, which determine the ramp and off-time of
the oscillator output clock:
VIN OK Comparator
The VIN OK comparator monitors the DC output of the
PFC and inhibits the PWM if the voltage on FBPFC is
less than its nominal 2.4V. Once the voltage reaches
2.4V, which corresponds to the PFC output capacitor
being charged to its rated boost voltage, soft-start begins.
1
fRT /CT
=
(4)
tRT /CT + tDEAD
The dead time of the oscillator is derived from the
following equation:
VREF −1
VREF − 3.8
⎛
⎞
tRT /CT = CT ×RT ×ln
(5)
⎜
⎟
PWM Soft-Start (SS)
⎝
⎠
at VREF=7.5V and tRT/CT=CT x RT x 0.56.
PWM startup is controlled by selection of the external
capacitor at soft-start. A current source of 10µA
supplies the charging current for the capacitor and
startup of the PWM begins at 1.5V.
The dead time of the oscillator is determined using:
2.8V
tDEAD
=
×CT = 360×CT
(6)
7.78mA
The dead time is so small (tRT/CT>>tDEAD) that the
operating frequency can typically be approximated by:
1
fRT /CT
=
(7)
tRT /CT
© 2010 Fairchild Semiconductor Corporation
FAN4800AS/CS/01S/02S • Rev. 1.0.1
www.fairchildsemi.com
15
PWM Control (RAMP)
Leading/Trailing Edge Modulation
When the PWM section is used in current mode, RAMP
is generally used as the sampling point for a voltage,
representing the current in the primary of the PWM’s
output transformer. The voltage is derived either from a
current-sensing resistor or a current transformer. In
voltage mode, RAMP is the input for a ramp voltage
generated by a second set of timing components
(RRAMP, CRAMP) that have a minimum value of 0V and a
peak value of approximately 6V. In voltage mode,
feedforward from the PFC output bus is an excellent
way to derive the timing ramp for the PWM stage.
Conventional PWM techniques employ trailing-edge
modulation, in which the switch turns on right after the
trailing edge of the system clock. The error amplifier
output is then compared with the modulating ramp up.
The effective duty cycle of the trailing-edge modulation
is determined during the on-time of the switch.
In the case of leading-edge modulation, the switch is
turned off exactly at the leading edge of the system
clock. When the modulating ramp reaches the level of
the error amplifier output voltage, the switch is turned
on. The effective duty-cycle of the leading-edge
modulation is determined during off-time of the switch.
Generating VDD
After turning on the FAN4800AS/CS/01S/02S at 11V,
the operating voltage can vary from 9.3V to 28V. The
threshold voltage of the VDD OVP comparator is 28V
and its hysteresis is 1V. When VDD reaches 28V, OPFC
is LOW and the PWM section is not disturbed. There
are two ways to generate VDD: use auxiliary power
supply around 15V or use bootstrap winding to self-bias
the FAN4800AS/CS/01S/02S system. The bootstrap
winding can be taped from the PFC boost choke or the
transformer of the DC-to-DC stage.
© 2010 Fairchild Semiconductor Corporation
FAN4800AS/CS/01S/02S • Rev. 1.0.1
www.fairchildsemi.com
16
Physical Dimensions
A
19.68
18.66
9
8
16
6.60
6.09
1
(0.40)
TOP VIEW
0.38 MIN
5.33 MAX
8.13
7.62
3.42
3.17
3.81
2.92
15
0
0.35
0.20
2.54
0.58
0.35
A
1.78
1.14
8.69
17.78
SIDE VIEW
NOTES: UNLESS OTHERWISE SPECIFIED
A
THIS PACKAGE CONFORMS TO
JEDEC MS-001 VARIATION BB
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR PROTRUSIONS
D) CONFORMS TO ASME Y14.5M-1994
E) DRAWING FILE NAME: N16EREV1
Figure 28. 16-Pin, Dual In-Line Package (DIP), JEDEC MS-001, .300" Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2010 Fairchild Semiconductor Corporation
FAN4800AS/CS/01S/02S • Rev. 1.0.1
www.fairchildsemi.com
17
Physical Dimensions
Figure 29. 16-Pin Small Outline Package (SOIC), JEDEC MS-012, .150", Narrow Body
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2010 Fairchild Semiconductor Corporation
FAN4800AS/CS/01S/02S • Rev. 1.0.1
www.fairchildsemi.com
18
© 2010 Fairchild Semiconductor Corporation
FAN4800AS/CS/01S/02S • Rev. 1.0.1
www.fairchildsemi.com
19
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