FAN4822 [FAIRCHILD]
ZVS Average Current PFC Controller; ZVS平均电流PFC控制器
| 型号： | FAN4822 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | ZVS Average Current PFC Controller |
| 文件： | 总10页 (文件大小：74K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
www.fairchildsemi.com
FAN4 8 2 2
ZVS Ave ra g e Cu rre n t P FC Co n t ro lle r
Features
General Description
• Average current sensing, continuous boost, leading edge
PFC for low total harmonic distortion and near unity
power factor
• Built-in ZVS switch control with fast response for high
efficiency at high power levels
• Average line voltage compensation with brownout control
• Current fed gain modulator improves noise immunity and
provides universal input operation
• Overvoltage comparator eliminates output “runaway” due
to load removal
The FAN4822 is a PFC controller designed specifically for
high power applications. The controller contains all of the
functions necessary to implement an average current boost
PFC converter, along with a Zero Voltage Switch (ZVS) con-
troller to reduce diode recovery and MOSFET turn-on
losses.
The average current boost PFC circuit provides high power
factor (>98%) and low Total Harmonic Distortion (THD).
Built-in safety features include undervoltage lockout, over-
voltage protection, peak current limiting, and input voltage
brownout protection.
• UVLO, current limit, and soft-start
• Precision 1.3% reference
The ZVS control section drives an external ZVS MOSFET
which, combined with a diode and inductor, soft switches the
boost regulator. This technique reduces diode reverse recov-
ery and MOSFET switching losses to reduce EMI and maxi-
mize efficiency.
Block Diagram
1
8
2
VEAO
VEA
GND
IEAO
FB
VCC
–
14
OVP
VCCZ
13.5V
12
+
FB
+
2.5V
IAC
R+
IEA
2.7V
–
+
+
GAIN
–
4
5
3
MODULATOR
–
S
R
Q
VRMS
I LIMIT
R–
+
–1V
ISENSE
–
PFC OUT
11
RTCT
REF
6
OSC
S
R
Q
VCCZ
REF
ZVS OUT
10
13
7
S
R
+
ZV SENSE
––
PWR GND
Q
9
REV. 1.0.1 8/10/01
FAN4822
PRODUCT SPECIFICATION
Pin Configuration
FAN4822
14-Pin DIP (P14)
FAN4822
16-Pin SOIC (S16W)
VEAO
IEAO
1
2
3
4
5
6
7
14
13
12
11
10
9
FB
VEAO
IEAO
ISENSE
IAC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
FB
REF
REF
ISENSE
IAC
VCC
VCC
PFC OUT
ZVS OUT
PWR GND
GND
PFC OUT
ZVS OUT
PWR GND
GND
VRMS
VRMS
RTCT
RTC
T
ZV SENSE
8
ZV SENSE
N/C
N/C
TOP VIEW
TOP VIEW
Pin Description (Pin numbers is parentheses are for 16-pin package)
Pin
1 (1)
Name
VEAO
IEAO
Function
Transconductance voltage error amplifier output.
Transconductance current error amplifier output.
Current sense input to the PFC current limit comparator.
PFC gain modulator reference input.
2 (2)
3 (3)
I
SENSE
4 (4)
I
AC
5 (5)
V
RMS
Input for RMS line voltage compensation.
6 (6)
R C
T T
Connection for oscillator frequency setting components.
7 (7)
ZV SENSE
GND
Input to the high speed zero voltage crossing comparator.
Analog signal ground.
8 (10)
9 (11)
10 (12)
11 (13)
12 (14)
13 (15)
14 (16)
PWR GND
ZVS OUT
PFC OUT
Return for the PFC and ZVS driver outputs.
ZVS MOSFET driver output.
PFC MOSFET driver output.
V
CC
Shunt-regulated supply voltage.
REF
FB
Buffered output for the internal 7.5V reference.
Transconductance voltage error amplifier input.
Absolute Maximum Ratings
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum rat-
ings are stress ratings only and functional device operation is not implied.
Parameter
Min
Max
55
Unit
mA
mA
V
Shunt Regulator Current (ICC
Peak Driver Output Current
Analog Inputs
)
±500
7
–0.3
–65
Junction Temperature
Storage Temperature Range
150
150
150
°C
°C
Lead Temperature (Soldering, 10 sec)
°C
Thermal Resistance (θJA)
Plastic DIP
Plastic SOIC
80
110
°C/W
°C/W
2
REV. 1.0.1 8/10/01
PRODUCT SPECIFICATION
FAN4822
Operating Conditions
Temperature Range
Min.
Max.
Units
°C
FAN4822IX
–40
85
Electrical Characteristics
Unless otherwise specified, R = 52.3kΩ, C = 470pF, T = Operating Temperature Range (Note 1)
T
T
A
Parameter
Voltage Error Amplifier
Input Voltage Range
Transconductance
Conditions
Min.
Typ.
Max.
Units
0
7
V
Ω
V
= V , VEAO = 3.75V
INV
50
2.4
60
60
70
2.5
75
120
2.6
µ
NON-INV
Feedback Reference Voltage V
= V
FB
V
EAO
Open Loop Gain
dB
dB
V
PSRR
V
– 3V < V
CC
< V
CCZ
– 0.5V
75
CCZ
Output Low
0.65
6.7
–80
80
1
Output High
6.0
–40
40
V
Source Current
Sink Current
∆V = ±0.5V, V
IN
= 6V
µA
OUT
∆V = ±0.5V, V
IN
= 1.5V
mA
OUT
Current Error Amplifier
Input Voltage Range
Transconductance
Input Offset Voltage
Open Loop Gain
PSRR
–1.5
2
V
Ω
V
V
= V , IEAO = 3.75V
INV
130
195
±3
310
±15
µ
NON-INV
mV
dB
dB
V
60
60
75
– 3V < V
CC
< V
CCZ
– 0.5V
75
CCZ
Output Low
0.65
6.7
–80
80
1
Output High
6.0
–30
40
V
Source Current
Sink Current
∆V = ±0.5V, V
IN
= 6V
µA
µA
OUT
∆V = ±0.5V, V
IN
= 1.5V
OUT
OVP Comparator
Threshold Voltage
Hysteresis
2.6
80
2.7
2.8
V
120
150
mV
I
Comparator
SENSE
Threshold Voltage
Delay to Output
–0.8
–1.0
–1.15
V
150
300
ns
ZV Sense Comparator
Propagation Delay
Threshold Voltage
Input Capacitance
100mV Overdrive
50
ns
V
7.35
7.5
6
7.65
pF
REV. 1.0.1 8/10/01
3
FAN4822
PRODUCT SPECIFICATION
Electrical Characteristics (Continued)
Unless otherwise specified, R = 52.3kΩ, C = 470pF, T = Operating Temperature Range (Note 1)
T
T
A
Parameter
Gain Modulator
Conditions
Min.
Typ.
Max.
Units
Gain (Note 2)
I
V
= 100mA, V
= 0V
= 0V,
VRMS
0.36
1.20
0.55
0.14
0.51
1.72
0.78
0.20
0.66
2.24
1.01
0.26
IAC
FB
I
= 50mA, V
= 0V
= 1.2V,
= 1.8V,
= 3.3V,
IAC
VRMS
V
FB
I
= 100µA, V
IAC
VRMS
V
= 0V
FB
I
= 100µA, V
IAC
VRMS
V
= 0V
FB
Bandwidth
I
= 250µA
10
MHz
V
IAC
Output Voltage
V
= 0V, V
VRMS
= 1.15V, I
IAC
=
0.72
74
0.8
0.9
87
FB
250µA
Oscillator
Initial Accuracy
Voltage Stability
Temperature Stability
Total Variation
T = 25°C
80
1
kHz
%
A
V
– 3V < V
CC
< V – 0.5V
CCZ
CCZ
2
%
Line, temperature
72
89
kHz
V
Ramp Valley to Peak Voltage
Dead Time
2.5
300
7.5
100
4.5
450
9.5
ns
CT Discharge Current
Reference
mA
Output Voltage
T = 25°C, I
REF
= 1mA
< V
7.4
7.5
2
7.6
10
15
V
mV
mV
%
A
Line Regulation
V
CCZ
– 3V < V
CC
– 0.5V
CCZ
Load Regulation
1mA < I
, < 20mA
2
REF
Temperature Stability
Total Variation
0.4
Line, load, and temperature
T = 125°C, 1000 hours
7.35
7.65
25
V
Long Term Stability
Short Circuit Current
PFC Comparator
Minimum Duty Cycle
Maximum Duty Cycle
MOSFET Driver Outputs
Output Low Voltage
5
mV
mA
j
V
CC
< V
CCZ
– 0.5V, V
= 0V
–15
–40
–100
REF
V
V
> 6.7V
< 1.2V
0
%
%
IEAO
90
95
IEAO
I
I
I
I
I
= –20mA
= –100mA
= –10mA, V
= 20mA
0.4
1.5
1.0
3.5
1.5
V
V
OUT
OUT
OUT
OUT
OUT
= 8V
0.8
V
CC
Output High Voltage
9.5
9
10.3
10.3
40
V
= 100mA
V
Output Rise/Fall Time
Undervoltage Lockout
Threshold Voltage
C = 1000pF
L
ns
V
–
V
–
V
–
V
V
CCZ
0.9
CCZ
0.6
CCZ
0.2
Hysteresis
2.4
2.9
3.45
4
REV. 1.0.1 8/10/01
PRODUCT SPECIFICATION
FAN4822
Electrical Characteristics (Continued)
Unless otherwise specified, R = 52.3kΩ, C = 470pF, T = Operating Temperature Range (Note 1)
T
T
A
Parameter
Conditions
Min.
12.8
12.4
Typ.
Max.
Units
Supply
Shunt Voltage (VCCZ
Load Regulation
Total Variation
Start-up Current
Operating Current
Notes
)
I
=25mA
13.5
14.2
±300
14.6
1.1
V
CC
25mA < I
CC
< 55mA
±150
mV
V
Load and temperature
V
V
< 12.3V
0.7
22
mA
mA
CC
CC
= V
CCZ
– 0.5V
28
1. Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
1
2. Gain = K x 5.3 V; K = (I
GAINMOD
– I ) x I
OFFSET AC
x (V
EAO
– 1.5)– .
REV. 1.0.1 8/10/01
5
FAN4822
PRODUCT SPECIFICATION
bined parasitic capacitance of D1 and Q1 (or optional ZVS
capacitor CZVS). At t , the voltage across Q1 is sufficiently
3
Functional Description
Switching losses of wide input voltage range PFC boost con-
verters increase dramatically as power levels increase above
200 watts. The use of zero-voltage switching (ZVS) tech-
niques improves the efficiency of high power PFCs by sig-
nificantly reducing the turn-on losses of the boost MOSFET.
ZVS is accomplished by using a second, smaller MOSFET,
together with a storage element (inductor) to convert the
turn-on losses of the boost MOSFET into useful output
power.
low that the controller turns Q2 off and Q1 on. Q1 then
behaves as an ordinary PFC switch, storing energy in the
boost inductor L1. The energy stored in L2 is completely dis-
charged into the boost capacitor via D2 during the Q1 off-
time and the value of L2 must be selected for discontinuous-
mode operation.
Component Selection
Q1 Turn-Off
Because the FAN4822 uses leading edge modulation, the
PFC MOSFET (Q1) is always turned off at the end of each
oscillator ramp cycle. For proper operation, the internal ZVS
flip-flop must be reset every cycle during the oscillator dis-
charge time. This is done by automatically resetting the ZVS
comparator a short time after the drain voltage of the main Q
has reached zero (refer to Figure 1 sense circuit). This sense
circuit terminates the ZVS on time by sensing the main Q
drain voltage reaching zero. It is then reset by way of a resis-
tor pull-up to VCC (R6). The advantage of this circuit is that
the ZVS comparator is not reset at the main Q turn off which
occurs at the end of the clock cycle. This avoids the potential
for improper reset of the internal ZVS flip-flop.
The basic function of the FAN4822 is to provide a power
factor corrected, regulated DC bus voltage using continuous,
average current-mode control. Like Micro Linear’s family of
PFC/PWM controllers, the FAN4822 employs leading-edge
pulse width modulation to reduce system noise and permit
frequency synchronization to a trailing edge PWM stage for
the highest possible DC bus voltage bandwidth. For minimi-
zation of switching losses, circuitry has been incorporated to
control the switching of the ZVS FET.
Theory of Operation
Figure 1 shows a simplified schematic of the output and con-
trol sections of a high power PFC circuit. Figure 2 shows the
relationship of various waveforms in the circuit. Q1 func-
tions as the main switching FET and Q2 provides the ZVS
action. During each cycle, Q2 turns on before Q1, diverting
the current in L1 away from D1 into L2. The current in L2
increases linearly until at t it equals the current through L1.
2
When these currents are equal, L1 ceases discharging current
and is now charged through L2 and Q2. At time t , the drain
2
voltage of Q1 begins to fall. The shape of the voltage wave-
form is sinusoidal due to the interaction of L2 and the com-
Another concern is the proper operation of the ZVS compar-
ator during discontinuous mode operation (DCM), which
will occur at the cusps of the rectified AC waveform and at
light loads. Due to the nature of the voltage seen at the drain
of the main boost Q during DCM operation, the ZVS com-
parator can be fooled into forcing the ZVS Q on for the
entire period. By adding a circuit which limits the maximum
on time of the ZVS Q, this problem can be avoided. Q3 in
Figure 1 provides this function.
L1
D1
+
C1
VREF
13
12
VREF
L2
FAN4822
CZVS(OPT)
VC
C
D2
Q1
R1
C2
R5
R3
R6
PFC OUT
11
220
22k
22k
Q2
ZVS OUT
10
9
7
8
ZV SENSE
GND
C3
33pF
PWR GND
C4
330pF
MAX ZVS
ON TIME LIMIT
R2
R4
51k
Q3
C5
Figure 1. Simplified PFC/ZVS Schematic.
6
REV. 1.0.1 8/10/01
PRODUCT SPECIFICATION
FAN4822
Q1 Turn-On
The turn-on event consists of the time it takes for the current
through L2 to ramp to the L1 current plus the resonant event
of L2 and the ZVS capacitor. The total event should occur in
a minimum of 350–450ns, but can be longer at the risk of
increasing the total harmonic distortion. Setting these times
equal should minimize conducted and radiated emissions.
A. SYSTEM
CLOCK
(INTERNAL)
tQ1(OFF) = tIL2 + tRES = 400ns
(1)
B. RTCT
Where IL2 is equal to IL1.
The value of L2 is calculated to remain in discontinuous-
mode:
C. ZVS GATE (Q2)
V
BUS × VRMS(MIN) × tIL2
L2 = ----------------------------------------------------------------
2 × POUT
(2)
The resonant event occurs in 1/4 of a full sinusoidal cycle.
For example, when a 1/4 cycle occurs in 200ns, the fre-
quency is 1.25MHz.
D. VDS (Q2)
1
1
fRES = ----------------------------------- = ---------------------
4 × tRES
2π
(3)
L2 × CZVS
Rearranging and solving for L2:
4 × tRES2
π2 × CZVS
L2 = --------------------------
E. PFC GATE (Q1)
(4)
The resonant capacitor (CZVS) value is found by setting
equations 2 and 4 equal to each other and solving for CZVS
.
4 × tRES2
× 2 × POUT
CZVS = ----------------------------------------------------------------------------
π2 × VBUS × VRMS(MIN) × tIL2
F. VDS (Q1)
(5)
Application
Figure 3 displays a typical application circuit for a 500W
ZVS PFC supply. Full design details are covered in applica-
tion note 33, FAN4822 Power Factor Correction With Zero
Voltage Resonant Switching.
G. IL2
t1
t3
t2
Figure 2. Timing Diagrams
REV. 1.0.1 8/10/01
7
FAN4822
PRODUCT SPECIFICATION
Figure 3. FAN4822 Schematic.
8
REV. 1.0.1 8/10/01
PRODUCT SPECIFICATION
FAN4822
Mechanical Dimensions inches (millimeters)
Package: P14
14-Pin PDIP
0.740 - 0.760
(18.79 - 19.31)
14
0.240 - 0.2600.295 - 0.325
(6.09 - 6.61) (7.49 - 8.25)
PIN 1 ID
1
0.070 MIN
(1.77 MIN)
(4 PLACES)
0.050 - 0.065 0.100 BSC
(1.27 - 1.65) (2.54 BSC)
0.015 MIN
(0.38 MIN)
0.170 MAX
(4.32 MAX)
SEATING PLANE
0.008 - 0.012
(0.20 - 0.31)
0.016 - 0.022
(0.40 - 0.56)
0º - 15º
0.125 MIN
(3.18 MIN)
Package: S16W
16-Pin Wide SOIC
0.400 - 0.414
(10.16 - 10.52)
16
0.291 - 0.301 0.398 - 0.412
(7.39 - 7.65) (10.11 - 10.47)
PIN 1 ID
1
0.024 - 0.034
(0.61 - 0.86)
(4 PLACES)
0.050 BSC
(1.27 BSC)
0.095 - 0.107
(2.41 - 2.72)
0º - 8º
0.012 - 0.020
(0.30 - 0.51)
0.022 - 0.042
(0.56 - 1.07)
0.009 - 0.013
(0.22 - 0.33)
0.090 - 0.094
(2.28 - 2.39)
0.005 - 0.013
(0.13 - 0.33)
SEATING PLANE
REV. 1.0.1 8/10/01
9
FAN4822
PRODUCT SPECIFICATION
Ordering Information
Part Number
PFC/PWM Frequency
Package
FAN4822IN
FAN4822IM
-40°C to 85°C
-40°C to 85°C
14-Pin PDIP (P14)
16-Pin Wide SOIC (S16W)
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO
ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME
ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
8/10/01 0.0m 003
Stock#DS30004803
2001 Fairchild Semiconductor Corporation
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