FAN4860 [FAIRCHILD]

3MHz, 5V Output Synchronous TinyBoostâ¢ Regulator; 3MHz的， 5V输出同步TinyBoostâ ?? ¢稳压器


型号：	FAN4860
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	3MHz, 5V Output Synchronous TinyBoostâ¢ Regulator 3MHz的， 5V输出同步TinyBoostâ ?? ¢稳压器稳压器
文件：	总15页 (文件大小：808K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

April 2010

FAN4860

3MHz, 5V Output Synchronous TinyBoost™ Regulator

Features

Description

Operates with Very Small External Components:

1μH Inductor and 0402 Case Size Input and Output

Capacitors

The FAN4860 is a low-power boost regulator designed to

provide a regulated 5V output from a single cell Li-Ion

battery. The output voltage is fixed at 5.0V with a guaranteed

maximum load current of 200mA at V_IN=2.3V and 300mA at

V_IN=3.3V. Input current in shut-down mode is less than 1µA,

which maximizes battery life.

Input Voltage Range from 2.3V to 4.5V

Fixed 5.0V Output Voltage

Maximum Load Current 200mA at V_IN=2.3V

Maximum Load Current 300mA at V_IN=3.3V

Up to 92% Efficient

Light-load PFM operation is automatic and “glitch-free”. The

regulator maintains output regulation at no-load with 37µA

quiescent current.

The combination of built-in power transistors, synchronous

rectification, and low supply current make the FAN4860 ideal

for battery powered applications.

Low Operating Quiescent Current

True Load Disconnect During Shutdown

The FAN4860 is available in 6-bump 0.4mm pitch Wafer-

Level Chip Scale Package (WLCSP) and a 6-lead 2x2mm

ultra-thin MLP package.

Variable On-time Pulse Frequency Modulation (PFM) with

Light-Load Power-Saving Mode

Internal Synchronous Rectifier

(No External Diode Needed)

Thermal Shutdown and Overload Protection

6-Pin 2 x 2mm UMLP

6-Bump WLCSP, 0.4mm Pitch

Applications

USB “On the Go” 5V Supply

HDMI 5V Supply

5V Supply for H-Bridge Motor Drivers

Powering 5V Peripherals

Figure 1. Typical Application

Supply Source for WLED Torch and Flash Lighting

PDAs, Portable Media Players

Cell Phones, Smart Phones, Portable Instruments

Ordering Information

Part Number

Operating Temperature Range

Package

Packing Method

FAN4860UC5X

-40°C to 85°C

WLCSP, 0.4mm Pitch

UMLP-6, 2 x 2mm

Tape and Reel

FAN4860UMP5X

Please refer to tape and reel specifications at http://www.fairchildsemi.com/packaging.

FAN4860 • Rev. 1.0.3

www.fairchildsemi.com

Block Diagrams

Figure 2. IC Block Diagram

Pin Configuration

Figure 3. WLCSP (Top View)

Figure 4. WLCSP (Bottom View)

Figure 5. 2X2mm UMLP (Top View)

Pin Definitions

Pin #

Name Description

WLCSP UMLP

Input Voltage. Connect to Li-Ion battery input power source and input capacitor (C_IN).

Switching Node. Connect to inductor.

VIN

Enable. When this pin is HIGH, the circuit is enabled. This pin should not be left floating.

Feedback. Output voltage sense point for V_OUT. Connect to output capacitor (C_OUT).

Output Voltage. This pin is both the output voltage terminal as well as an IC bias supply.

VOUT

Ground. Power and signal ground reference for the IC. All voltages are measured with

respect to this pin.

1, P1

GND

FAN4860 • Rev. 1.0.3

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Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above

the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended

exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum

ratings are stress ratings only.

Symbol

V_IN

Parameter

Min.

Max.

Units

VIN Pin

VOUT Pin

FB Pin

-0.3

–2

5.5

V_OUT

V_FB

–2

5.5

6.5

5.5

-0.3

-1.0

-0.3

V_SW

V_EN

SW Node

EN Pin

Transient: 10ns, 3MHz

Human Body Model per JESD22-A114

Charged Device Model per JESD22-C101

2.0

1.0

Electrostatic Discharge

Protection Level

ESD

T_J

T_STG

T_L

Junction Temperature

Storage Temperature

–40

–65

+150

+260

°C

Lead Soldering Temperature, 10 Seconds

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating

conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend

exceeding them or designing to absolute maximum ratings.

Symbol

Parameter

Min.

Max.

Units

V_IN

I_OUT

T_A

Supply Voltage

2.3

4.5

200

Output Current

Ambient Temperature

Junction Temperature

–40

+85

°C

T_J

+125

Thermal Properties

Junction-to-ambient thermal resistance is a function of application and board layout. This data is measured with four-layer

2s2p boards in accordance to JEDEC standard JESD51. Special attention must be paid not to exceed junction temperature

T_J(max)at a given ambient temperate T_A.

Symbol Parameter

Typical

130

Units

°C/W

WLCSP

UMLP

Junction-to-Ambient Thermal Resistance

θ_JA

FAN4860 • Rev. 1.0.3

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Electrical Specifications

Minimum and maximum values are at V_IN=V_EN=2.3V to 4.5V, T_A=-40°C to +85°C; circuit of Figure 1, unless otherwise noted.

Typical values are at T_A=25°C, V_IN=V_EN=3.6V.

Symbol

I_IN

Parameter

V_INInput Current

Conditions

Quiescent: V_IN=3.6V, I_OUT=0, EN=V_IN

Shutdown: EN=0, V_IN=3.6V

V_OUT=0, EN=0, V_IN=4.2V

V_OUT=5V, V_IN=3.6V, EN=0

V_INRising

Min.

Typ. Max. Units

0.5

μA

1.5

I_{LK_OUT}

V_OUTLeakage Current

μA

I_{LK_RVSR}V_OUTto V_INReverse Leakage

2.5

2.3

V_UVLO

Under-Voltage Lockout

2.2

V_{UVLO_HYS}Under-Voltage Lockout Hysteresis

190

V_ENH

V_ENL

Enable HIGH Voltage

1.05

Enable LOW Voltage

0.4

I_{LK_EN}

Enable Input Leakage Current

0.01

5.05

μA

V_INfrom 2.3V to 4.5V, I_OUT≤200mA

V_INfrom 2.7V to 4.5V, I_OUT≤200mA

V_INfrom 3.3V to 4.5V, I_OUT≤300mA

Referred to V_OUT

4.80

4.85

5.15

V_OUT

V_OUTOutput Voltage Accuracy⁽¹⁾

V_REF

t_OFF

Reference Accuracy

Off Time

4.975 5.050 5.125

V_IN=3.6V, I_OUT=200mA

V_IN=2.3V, V_OUT=5V

195

200

300

240

265

I_OUT

Maximum Output Current⁽²⁾

SW Peak Current Limit

V_IN=3.3V, V_OUT=5V

V_IN=3.6V, V_OUT=5V

400

1100

850

I_SW

I_SS

V_IN=3.6V, V_OUT>V_IN

930

1320

300

Soft-Start Input Peak Current Limit⁽²⁾V_IN=3.6V, V_OUT< V_IN

V_IN=3.6V, I_OUT=200mA

Soft-Start Time

t_SS

100

μs

Time=Rising EN until Regulated V_OUT

N-Channel Boost Switch

P-Channel Sync Rectifier

Thermal Shutdown

V_IN=3.6V

300

400

150

R_DS(ON)

mΩ

V_IN=3.6V

T_TSD

I_LOAD=10mA

°C

T_{TSD_HYS}Thermal Shutdown Hysteresis

Notes:

1. I_LOADfrom 0 to I_OUT; also includes load transient response. V_OUTmeasured from mid-point of output voltage ripple.

Effective capacitance of C_OUT> 1.5μF.

2. Guaranteed by design and characterization; not tested in production.

FAN4860 • Rev. 1.0.3

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Typical Characteristics

Unless otherwise specified, circuit per Figure 1, 3.6V_IN, T_A=25°C.

100

-40C

+25C

+85C

2.5 Vin

3.3 Vin

3.6 Vin

4.5 Vin

100

150

200

250

300

100

150

200

250

300

Load Current (mA)

Figure 6 Efficiency vs. V_IN

Figure 7 Efficiency vs. Temperature, 3.6V_IN

2.5 Vin

3.3 Vin

3.6 Vin

4.5 Vin

-40C

+25C

+85C

-25

-50

-75

-100

-25

-50

-75

-100

100

150

200

250

300

100

150

200

250

300

Load Current (mA)

Figure 8 Line and Load Regulation

Figure 9 Load Regulation vs. Temperature, 3.6V_IN

4000

3200

2400

1600

800

2.5 Vin

3.6 Vin

4.5 Vin

100

150

200

250

300

Load Current (mA)

Figure 10 Switching Frequency

Figure 11 Quiescent Current

FAN4860 • Rev. 1.0.3

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Typical Characteristics

Unless otherwise specified, circuit per Figure 1, 3.6V_IN, T_A=25°C.

Figure 12 Maximum DC Load Current

Figure 13 Peak Inductor Current

Figure 15 Output Ripple, 200mA PWM Load

Figure 17 50-200mA Load Transient, 100ns Step

Figure 14 Output Ripple, 10mA PFM Load

Figure 16 0-50mA Load Transient, 100ns Step

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FAN4860 • Rev. 1.0.3

Typical Characteristics

Unless otherwise specified, circuit per Figure 1, 3.6V_IN, T_A=25°C.

Figure 18 Line Transient, 5mA Load, 10µs Step

Figure 19 Line Transient, 200mA Load, 10µs Step

Figure 20 Startup, No Load

Figure 21 Startup, 33Ω Load

Figure 22 Shutdown, 1KΩ Load

Figure 23 Shutdown, 33Ω Load

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FAN4860 • Rev. 1.0.3

Typical Characteristics

Unless otherwise specified, circuit per Figure 1, 3.6V_IN, T_A=25°C.

Figure 24 Overload Protection

Figure 25 Short-Circuit Response

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FAN4860 • Rev. 1.0.3

Functional Description

Circuit Description

PFM Mode

FAN4860 is a synchronous boost regulator, typically operating

at 3MHz in continuous conduction mode (CCM), which occurs

at moderate to heavy load current and low V_INvoltages.

If V_OUT> V_REFwhen the minimum off-time has ended, the

regulator enters PFM mode. Boost pulses are inhibited until

V_OUT< V_REF. The minimum on-time is increased to enable

the output to pump up sufficiently with each PFM boost

pulse. Therefore, the regulator behaves like a constant on-

time regulator, with the bottom of its output voltage ripple at

5.05V in PFM mode.

At light-load currents, the converter switches automatically to

power-saving PFM mode. The regulator automatically and

smoothly

transitions

between

quasi-fixed-frequency

continuous conduction PWM mode and variable-frequency

PFM mode to maintain the highest possible efficiency over

the full range of load current and input voltage.

Table 1. Operating States

Mode

Description

Invoked When:

PWM Mode Regulation

LIN

Linear Startup

Boost Soft-Start

V_IN> V_OUT

V_OUT< V_REG

V_OUT=V_REG

The FAN4860 uses a minimum on-time and computed

minimum off-time to regulate V_OUT. The regulator achieves

excellent transient response by employing current mode

modulation. This technique causes the regulator output to

exhibit a load line. During PWM mode, the output voltage

drops slightly as the input current rises. With a constant V_IN,

this appears as a constant output resistance.

BST

Boost Operating Mode

Shutdown and Startup

If EN is LOW, all bias circuits are off and the regulator is in

shutdown mode. During shutdown, true load disconnect

between battery and load prevents current flow from V_INto

V_OUT, as well as reverse flow from V_OUTto V_IN.

The “droop” caused by the output resistance when a load is

applied allows the regulator to respond smoothly to load

transients with negligible overshoot.

LIN State

When EN rises, if V_IN> UVLO, the regulator first attempts to

bring V_OUTwithin about 1V of V_INby using the internal fixed

current source from V_IN(I_LIN1). The current is limited to about

630mA during LIN1 mode.

If V_OUTreaches V_IN-1V during LIN1 mode, the SS state is

initiated. Otherwise, LIN1 times out after 16 CLK counts and

the LIN2 mode is entered.

In LIN2 mode, the current source is incremented to 850mA.

If V_OUTfails to reach V_IN-1V after 64 CLK counts, a fault

condition is declared.

SS State

Upon the successful completion of the LIN state (V_OUT>V_IN-

1V), the regulator begins switching with boost pulses current

limited to about 50% of nominal level, incrementing to full

scale over a period of 32 CLK counts.

Figure 26 Output Resistance (R_OUT

)

If the output fails to achieve 90% of its setpoint within 96 CLK

counts at full-scale current limit, a fault condition is declared.

V_OUTas a function of I_LOADcan be computed when the

regulator is in PWM mode (continuous conduction) as:

BST State

V_OUT= 5.05 − R_OUT•I_LOAD

EQ. 1

This is the normal operating mode of the regulator. The

regulator uses a minimum t_OFF-minimum t_ONmodulation

For example, at V_IN=3.3V, and I_LOAD=200mA, V_OUTwould

drop to:

OUT

scheme. Minimum t_OFFis proportional to

, which keeps

the regulator’s switching frequency reasonably constant in

CCM. t_ON(MIN)is proportional to V_INand is higher if the inductor

current reaches 0 before t_OFF(MIN)during the prior cycle.

V_OUT= 5.05 − 0.38 • 0.2 = 4.974V

EQ. 1A

At V_IN=2.3V, and I_LOAD=200mA, V_OUTwould drop to:

V_OUT= 5.05 − 0.68 • 0.2 = 4.914V

EQ. 1B

FAN4860 • Rev. 1.0.3

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To ensure that V_OUTdoes not pump significantly above the

regulation point, the boost switch remains off as long as

The fault clock period as a function of V_INis shown in Figure 28.

FB > V_REF

Fault State

The regulator enters the FAULT state under any of the

following conditions:

V_OUTfails to achieve the voltage required to advance from

LIN state to SS state.

V_OUTfails to achieve the voltage required to advance from

SS state to BST state.

Sustained (32 CLK counts) pulse-by-pulse current limit

during the BST state.

The regulator moves from BST to LIN state due to a short

circuit or output overload (V_OUT< V_IN-1V).

Figure 28. Fault Clock Period vs. V_IN

Once a fault is triggered, the regulator stops switching and

presents a high-impedance path between V_INand V_OUT. After

waiting 480 CLK counts, a re-start is attempted.

The V_IN-dependent LIN mode charging current is illustrated

in Figure 29.

Soft-Start and Fault Timing

The soft-start timing for each state, and the fault times, are

determined by the fault clock, whose period is inversely

proportional to V_IN. This allows the regulator more time to

charge larger values of C_OUTwhen V_INis lower. With higher

V_IN, this also reduces power delivered to V_OUTduring each

cycle in current limit.

The number of clock counts for each state is illustrated in

Figure 27.

Figure 29. LIN Mode Current vs. V_IN

Over-Temperature Protection (OTP)

The regulator shuts down when the thermal shutdown

threshold is reached. Restart, with soft-start, occurs when

the IC has cooled by about 30°C.

Figure 27. Fault Response into Short Circuit

Over-Current Protection (OCP)

During boost-mode operation, the FAN4860 employs a

cycle-by-cycle peak current limit to protect switching

elements. Sustained current limit, for 32 consecutive fault

CLK counts, initiates a fault condition.

During an overload condition, as V_OUTcollapses to

approximately V_IN-1V, the synchronous rectifier is

immediately switched off and a fault condition is declared.

Automatic restart occurs once the overload/short is removed

and the fault timer completes counting.

FAN4860 • Rev. 1.0.3

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Application Information

External Component Selection

Table 3. Minimum C_EFFRequired for Stability

Operating Conditions

Table 2 shows the recommended external components for

the FAN4860:

C_EFF(MIN)(μF)

V_IN(V)

I_LOAD(mA)

Table 2. External Components

2.3 to 4.5

2.7 to 4.5

2.3 to 4.5

0 to 200

0 to 150

1.5

1.0

REF Description

Manufacturer

Murata LQM21PN1R0MC0,

or equivalent

1.0µH, 0.8A, 190mΩ,

0805

C_EFFvaries with manufacturer, dielectric material, case size,

and temperature. Some manufacturers may be able to

provide an X5R capacitor in 0402 case size that retains C_EFF

>1.5μF with 5V bias; others may not. If this C_EFFcannot be

economically obtained and 0402 case size is required, the IC

can work with the 0402 capacitor as long as the minimum V_IN

is restricted to >2.7V.

Murata GRM155R60J225M

TDK C1005X5R0J225M

Kemet C0603C475K8PAC

TDK C1608X5R1A475K

2.2µF, 6.3V, X5R,

0402

C_IN

4.7µF, 10V, X5R,

0603⁽³⁾

C_OUT

Note:

3. A 6.3V-rated 0603 capacitor may be used for C_OUT

such as Murata GRM188R60J225M. All datasheet

For best performance, a 10V-rated 0603 output capacitor is

recommended (Kemet C0603C475K8PAC, or equivalent).

Since it retains greater C_EFFunder bias and over

temperature, ouptut ripple can is reduced and transient

capability enhanced.

parameters are valid with the 6.3V-rated capacitor.

Due to DC bias effects, the 10V capacitor offers a

performance enhancement; particularly output ripple

and transient response, without any size increase.

Output Voltage Ripple

Output Capacitance (C_OUT

)

Output voltage ripple is inversely proportional to C_OUT

During t_ON, when the boost switch is on, all load current is

supplied by C_OUT

Stability

The effective capacitance (C_EFF

ceramic capacitors decrease as their bias voltage increases,

as shown in Figure 30.

) of small, high-value,

I_LOAD

V_{RIPPLE(P−P)}= t_ON

•

EQ. 2

C_OUT

and

⎛

⎞

⎟

⎠

V_IN

⎜

t_ON= t_SW•D = t_SW• 1−

⎜

EQ. 3

EQ. 4

V_OUT

⎝

Therefore:

⎛

⎜

⎝

⎞

V_IN

I_LOAD

⎜

⎟

⎠

V_{RIPPLE(P−P)}= t_SW• 1−

•

V_OUT

C_OUT

where:

t_SW

EQ. 5

f_SW

As can be seen from EQ. 4, the maximum V_RIPPLEoccurs

when V_INis minimum and I_LOADis maximum.

Startup

Figure 30. C_EFFfor 4.7μF, 0603, X5R, 6.3V

(Murata GRM188R60J475K)

Input current limiting is in effect during soft-start, which limits

the current available to charge C_OUT. If the output fails to

achieve regulation within the time period described in the

soft-start section above; a FAULT occurs, causing the circuit

to shut down, then restart after a significant time period. If

C_OUTis a very high value, the circuit may not start on the first

attempt, but eventually achieves regulation if no load is

present. If a high-current load and high capacitance are both

present during soft-start, the circuit may fail to achieve

FAN4860 is guaranteed for stable operation with the

minimum value of C_EFF(C_EFF(MIN)) outlined in Table 3.

FAN4860 • Rev. 1.0.3

www.fairchildsemi.com

regulation and continually attempt soft-start, only to have

C_OUTdischarged by the load when in the FAULT state.

C_OUT2may be necessary to preserve load transient response

when the Schottky is used. When a load is applied at the FB

pin, the forward voltage of the D1 rapidly increases before

the regulator can respond or the inductor current can

change. This causes an immediate drop of up to 300mV,

depending on D1’s characteristics if C_OUT2is absent. C_OUT2

supplies instantaneous current to the load while the regulator

adjusts the inductor current. A value of at least half of the

minimum value of C_OUTshould be used for C_OUT2. C_OUT2

needs to withstand the maximum voltage at the FB pin as

the TVS is clamping.

The circuit can start with higher values of C_OUTunder full

load if V_INis higher, since:

I_RIPPLE

⎛

⎞

⎟

I_OUT= I

−

•

⎜

EQ. 6

LIM(PK)

V_OUT

⎝

⎠

Generally, the limitation occurs in BST mode.

The FAN4860 starts on the first pass (without triggering a

FAULT) under the following conditions for C_EFF(MAX)

The maximum DC output current available is reduced with

this circuit, due to the additional dissipation of D1.

Table 4. Maximum C_EFFfor First-Pass Startup

Operating Conditions

_EFF(MAX)(μF)

V_IN(V)

R_LOAD(MIN)

Layout Guideline

2.3 to 4.5

2.7 to 4.5

25Ω

33Ω

C_EFFvalues shown in Table 4 typically apply to the lowest

V_IN. The presence of higher V_INenhances ability to start into

larger C_EFFat full load.

Transient Protection

To protect against external voltage transients caused by

ESD discharge events, or improper external connections,

some applications employ an external transient voltage

suppressor (TVS) and Schottky diode (D1 in Figure 31).

Figure 32 WLCSP Suggested Layout (Top View)

Figure 31 FAN4860 with External Transient Protection

The TVS is designed to clamp the FB line (system V_OUT) to

+10V or –2V during external transient events. The Schottky

diode protects the output devices from the positive

excursion. The FB pin can tolerate up to 14V of positive

excursion, while both the FB and VOUT pins can tolerate

negative voltages.

The FAN4860 includes a circuit to detect a missing or

defective D1 by comparing V_OUTto FB. If V_OUT– FB > about

0.7V, the IC shuts down. The IC remains shut down until

Figure 33 UMLP Suggested Layout (Top View)

V_OUT< UVLO and V_IN< UVLO+0.7 or EN is toggled.

FAN4860 • Rev. 1.0.3

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Physical Dimensions

0.03 C

0.40

BALL A1

INDEX AREA

(Ø0.20)

Cu Pad

0.40

(Ø0.30)

Solder Mask

Opening

0.03 C

TOP VIEW

RECOMMENDED LAND PATTERN

(NSMD PAD TYPE)

0.06 C

0.378±0.018

0.208±0.021

0.625

0.547

0.05 C

SEATING PLANE

SIDE VIEWS

Ø0.260±0.010

NOTES:

0.40

A. NO JEDEC REGISTRATION APPLIES.

B. DIMENSIONS ARE IN MILLIMETERS.

0.005

C A B

C. DIMENSIONS AND TOLERANCES PER

ASMEY14.5M, 1994.

(Y) +/-0.018

0.40

D. DATUM C, THE SEATING PLANE IS DEFINED

BY THE SPHERICAL CROWNS OF THE BALLS.

(X) +/-0.018

E. PACKAGE TYPICAL HEIGHT IS 586 MICRONS

±39 MICRONS (547-625 MICRONS).

BOTTOM VIEW

F. FOR DIMENSIONS D, E, X, AND Y SEE

PRODUCT DATASHEET.

G. DRAWING FILENAME: UC006ACrev4.

Figure 33. 6-Lead, 0.4mm Pitch, WLCSP Package

Product-Specific Dimensions

Product

FAN4860UC5X

1.230mm +/-0.030mm

0.880mm +/-0.030mm

0.240mm

0.215mm

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without

notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most

recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which

covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

FAN4860 • Rev. 1.0.3

www.fairchildsemi.com

Physical Dimensions

0.10 C

2.0

1.45

2.0

(0.25)

PIN1

IDENT

0.10 C

0.80 1.80

0.50

TOP VIEW

0.65

0.35

0.55 MAX

0.10 C

0.08 C

RECOMMENDED LAND PATTERN

(0.15)

0.05

0.00

SEATING

PLANE

SIDE VIEW

NOTES:

A. PACKAGE CONFORMS TO JEDEC MO-229

EXCEPT WHERE NOTED.

1.35

1.45

PIN1

IDENT

B. DIMENSIONS ARE IN MILLIMETERS.

C. DIMENSIONS AND TOLERANCES PER

ASME Y14.5M, 1994.

0.70

0.80

0.35

0.25

D. LANDPATTERN RECOMMENDATION IS BASED

ON FSC DESIGN ONLY.

0.10 C A B

0.05 C

E. DRAWING FILENAME: MKT-UMLP06Erev2.

0.65

0.35

0.25

BOTTOM VIEW

Figure 34. 6-Lead UMLP Package

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without

notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most

recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which

covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

FAN4860 • Rev. 1.0.3

www.fairchildsemi.com

FAN4860 • Rev. 1.0.3

www.fairchildsemi.com

FAN4860 [FAIRCHILD]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E