FAN5090MTCX [FAIRCHILD]
Two Phase Interleaved Synchronous Buck Converter for VRM 9.x Applications; 两相交错同步降压转换器，用于VRM 9.x中的应用
| 型号： | FAN5090MTCX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Two Phase Interleaved Synchronous Buck Converter for VRM 9.x Applications |
| 文件： | 总17页 (文件大小：184K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
www.fairchildsemi.com
FAN5090
Two Phase Interleaved Synchronous Buck Converter
for VRM 9.x Applications
Features
Description
• Programmable output from 1.10V to 1.85V in 25mV steps
using an integrated 5-bit DAC
• Two interleaved synchronous phases for maximum
performance
The FAN5090 is a synchronous two-phase DC-DC controller
IC which provides a highly accurate, programmable output
voltage for VRM 9.x processors. Two interleaved synchro-
nous buck regulator phases with built-in current sharing
operate 180° out of phase to provide the fast transient
response needed to satisfy high current applications while
minimizing external components.
• 100nsec transient response time
• Built-in current sharing between phases
• Remote sense
• Programmable Active Droop (Voltage Positioning)
• Programmable switching frequency from 100KHz to
300KHz per phase
The FAN5090 features Programmable Active Droop for
transient response with minimum output capacitance. It has
integrated high-current gate drivers, with adaptive delay gate
switching, eliminating the need for external drive devices.
The FAN5090 uses a 5-bit D/A converter to program the
output voltage from 1.10V to 1.85V in 25mV steps with an
accuracy of 1%. The FAN5090 uses a high level of integra-
tion to deliver load currents in excess of 50A from a 12V
source with minimal external circuitry.
• Adaptive delay gate switching
• Integrated high-current gate drivers
• Integrated Power Good, OV, UV, Enable/Soft Start
functions
• Drives N-channel MOSFETs
• Operation optimized for 12V operation
• Overcurrent protection using MOSFET sensing
• 24 pin TSSOP package
The FAN5090 also offers integrated functions including
Power Good, Output Enable/Soft Start, under-voltage lock-
out, over-voltage protection, and adjustable current limiting
with independent current sense on each phase. It is available
in a 24 pin TSSOP package.
Applications
• Power supply for Pentium IV
• Power supply for Athlon
• VRM for Pentium IV processor
• Programmable step-down power supply
Block Diagram
+12V
18
BYPASS
6
+12V
BOOT A
13
23
UVLO
5V Reg
OSC
14
15
RT
+
-
Digital
Control
+12V
17
16
-
+
-
+
Current
Limit
VO
BOOT B
-
+
12
+12V
GNDA
11
10
Digital
Control
-
+
+12V
8
9
Power
Good
5-Bit
DAC
1
2 3
4
5
19
PWRGD
7
22
20
ILIM
24
21
VID2 VID4
VID0
VID1
DROOP/E*
ENABLE/SS
AGND
VID3
Pentium is a registered trademark of Intel Corporation. Athlon is a registered trademark of AMD. Programmable Active Droop is a trademark of Fairchild Semiconductor.
REV. 1.0.1 9/16/03
FAN5090
PRODUCT SPECIFICATION
Pin Assignments
1
2
3
VID0
VID1
VID2
VID3
24
23
22
VFB
RT
ENABLE/SS
4
5
DROOP
ILIM
PWRGD
VCC
21
20
19
18
VID4
BYPASS
AGND
6
7
FAN5090
LDRVB
PGNDB
SWB
8
9
10
11
12
17
16
15
14
13
LDRVA
PGNDA
SWA
HDRVB
HDRVA
BOOTA
BOOTB
Pin Definitions
Pin Number Pin Name
Pin Function Description
1-5
VID0-4
Voltage Identification Code Inputs. Internally pulled-up open collector/TTL
compatible inputs program the output voltage over range specified in Table 1.
6
7
BYPASS
AGND
5V Rail. Bypass this pin with a 0.1µF ceramic capacitor to AGND.
Analog Ground. Return path for low power analog circuitry. This pin should be
connected to a low impedance system ground plane to minimize ground loops.
8
LDRVB
Low Side FET Driver for B. Connect this pin to the gate of an N-channel
MOSFET for synchronous operation. The trace from this pin to the MOSFET gate
should optimally be <0.5".
9
PGNDB
SWB
Power Ground B. Return pin for high currents flowing in low-side MOSFET.
Connect directly to low-side MOSFET source.
10
High Side Driver Source and Low Side Driver Drain Switching Node B. Gate
drive return for high side MOSFET, and negative input for low-side MOSFET
current sense.
11
HDRVB
High Side FET Driver B. Connect this pin to the gate of an N-channel MOSFET.
The trace from this pin to the MOSFET gate should optimally be <0.5".
12
13
14
BOOTB
BOOTA
HDRVA
Bootstrap B. Input supply for high-side MOSFET.
Bootstrap A. Input supply for high-side MOSFET.
High Side FET Driver A. Connect this pin to the gate of an N-channel MOSFET.
The trace from this pin to the MOSFET gate should optimally be <0.5".
15
SWA
High Side Driver Source and Low Side Driver Drain Switching Node A. Gate
drive return for high side MOSFET, and negative input for low-side MOSFET
current sense.
16
17
PGNDA
LDRVA
Power Ground A. Return pin for high currents flowing in low-side MOSFET.
Connect directly to low-side MOSFET source.
Low Side FET Driver for A. Connect this pin to the gate of an N-channel
MOSFET for synchronous operation. The trace from this pin to the MOSFET gate
should optimally be <0.5".
18
19
VCC
VCC. Internal IC supply. Connect to system 12V supply, and decouple with a 10Ω
resistor and 1µF ceramic capacitor.
PWRGD
Power Good Flag. An open collector output that will be logic LOW if the output
voltage is less than 350mV less than the nominal output voltage setpoint. Power
Good is prevented from going low until the output voltage is out of spec for
500µsec.
2
REV. 1.0.1 9/16/03
PRODUCT SPECIFICATION
FAN5090
Pin Number Pin Name
Pin Function Description
20
21
ILIM
Current Limit. A resistor from this pin to ground sets the over current trip level.
DROOP
Droop Control. A resistor from this pin to ground sets the amount of droop by
controlling the gain of the current sense amplifier.
22
ENABLE/SS
Output Enable/Softstart. A logic LOW on this pin will disable the output. An
10µA internal current source allows for open collector control. This pin also
doubles as soft start.
23
24
RT
Frequency Set. A resistor from this pin to ground sets the switching frequency.
VFB
Voltage Feedback. Connect to the desired regulation point at the output of the
converter.
Absolute Maximum Ratings (Absolute Maximum Ratings are the values beyond which the device
may be damaged or have it’s useful life impaired. Functional operation under these conditions is not implied.)
Parameter
Min.
Max.
15
24
24
6
Unit
V
Supply Voltage VCC
Supply Voltages BOOT to PGND
BOOT to SW
V
V
Voltage Identification Code Inputs, VID0-VID4
VFB, ENABLE/SS, PWRGD, DROOP
SWA, SWB to AGND (<1µs)
PGNDA, PGNDB to AGND
Gate Drive Current, peak pulse
Junction Temperature, TJ
Storage Temperature
V
6
V
-3
15
0.5
3
V
-0.5
V
A
-55
-65
150
150
°C
°C
Thermal Ratings
Parameter
Min.
Typ.
Max.
300
Unit
°C
Lead Soldering Temperature, 10 seconds
Power Dissipation, PD
650
mW
°C/W
°C/W
Thermal Resistance Junction-to-Case, ΘJC
Thremal Resistance Junction-to-Ambient, ΘJA
16
84
Recommended Operating Conditions (See Figure 2)
Parameter
Conditions
Min.
16
Max.
22
Units
V
Output Driver Supply, BOOTA, B
Ambient Operating Temperature
Supply Voltage VCC
0
70
°C
10.8
13.2
V
REV. 1.0.1 9/16/03
3
FAN5090
PRODUCT SPECIFICATION
Electrical Specifications
(VCC = 12V, VID = [01111] = 1.475V, and TA = +25°C using circuit in Figure 2, unless otherwise noted.)
The • denotes specifications which apply over the full operating temperature range.
Parameter
Conditions
Min.
Typ.
Max.
Units
Input Supply
UVLO Hysteresis
12V UVLO
1.0
9.5
15
V
V
Rising Edge
•
8.5
10.3
20
12V Supply Current
Internal Voltage Regulator
BYPASS Voltage
BYPASS Capacitor
VREF and DAC
PWM Output Open
mA
4.75
100
5
5.25
V
nF
Output Voltage
See Table 1
•
•
1.100
1.460
1.850
1.490
V
V
Initial Voltage Setpoint1
Output Temperature Drift
Line Regulation
ILOAD = 0A, VID = [01111]
TA = 0 to 70°C
1.475
5
mV
µV
VCC = 11.4V to 12.6V
ILOAD = 69A, RDROOP = 13.3kΩ
130
56
Droop2
mV
mΩ
nsec
%
Programmable Droop Range
Response Time
0
1.25
∆Vout = 10mV
RDS,on (A) = RDS,on (B),
100
5
Current Mismatch
ILOAD = 69A Droop = 1mΩ
VID Inputs
Input LOW current, VID pins
VID VIH
VVID = 0.4V
-60
2.0
µA
V
VID VIL
0.8
V
Oscillator
Oscillator Frequency
Oscillator Range
Maximum Duty Cycle
Minimum LDRV on-time
Gate Drive
RT = 54.9KΩ
RT = 137KΩ to 46.4KΩ
RT = 137KΩ
•
440
200
500
560
600
kHz
kHz
%
90
RT = 46.4KΩ
330
nsec
Gate Drive On-Resistance
HS Source
5
6.5
2
Ω
Ω
Ω
Ω
nsec
nsec
HS Sink
1.5
5
LS Source
6.5
2
LS Sink
1.5
50
25
Output Driver
Rise Time
Fall Time
See Figure 1, CL = 3000pF
Enable/Soft Start
Soft Start Current
Enable Threshold
10
µA
V
ON
OFF
1.0
85
0.4
Power Good
PWRGD Threshold
Logic LOW, VVID – VPWRGD
Isink = 4mA
•
88
92
%VOUT
V
PWRGD Output Voltage
PWRGD Delay
0.4
High → Low
500
µsec
4
REV. 1.0.1 9/16/03
PRODUCT SPECIFICATION
FAN5090
Electrical Specifications (continued)
(VCC = 12V, VID = [01111] = 1.475V, and TA = +25°C using circuit in Figure 2, unless otherwise noted.)
The • denotes specifications which apply over the full operating temperature range.
Parameter
Conditions
Min.
Typ.
Max.
Units
OVP and OTP
Output Overvoltage Detect
Over Temperature Shutdown
Over Temperature Hysteresis
•
2.1
2.2
140
40
2.3
V
130
150
°C
°C
Notes:
1. As measured at the VFB (pin 24) sense point. For motherboard applications, the PCB layout should exhibit no more than
0.5mΩ trace resistance between the converter’s output capacitors and the CPU. Remote sensing should be used for optimal
performance.
2. Using the VFB pin for remote sensing of the converter’s output at the load, the converter will be in compliance with VRM 9.x
specification.
Table 1. Output Voltage Programming Codes
VID4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VID3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
VID2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
VID1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
VID0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
VOUT to CPU
OFF
1.100V
1.125V
1.150V
1.175V
1.200V
1.225V
1.250V
1.275V
1.300V
1.325V
1.350V
1.375V
1.400V
1.425V
1.450V
1.475V
1.500V
1.525V
1.550V
1.575V
1.600V
1.625V
1.650V
1.675V
1.700V
1.725V
1.750V
1.775V
1.800V
1.825V
1.850V
Note:
1. 0 = VID pin is tied to GND.
1 = VID pin is pulled up internally to 5V.
REV. 1.0.1 9/16/03
5
FAN5090
PRODUCT SPECIFICATION
Gate Drive Test Circuit
t
t
R
F
90%
90%
HDRV
2.2V
2V
VOUT
3000pF
10%
t
10%
t
DT
DT
1.2V
2V
LDRV
Figure 1. Output Drive Timing Diagram
6
REV. 1.0.1 9/16/03
PRODUCT SPECIFICATION
FAN5090
Typical Operating Characteristics
(VCC = 12V, VOUT = 1.475V, and TA = +25°C using circuit in Figure 2, unless otherwise noted.)
ADAPTIVE GATE DELAY
CH1: HDRVB
EFFICIENCY VS. OUTPUT CURRENT
CH2: LDRVB
40A Load
90
E* Mode
2 Phase Mode
85
80
75
70
65
60
0
10
20
30 40
50
60 70
LOAD CURRENT (A)
HIGH-SIDE GATE DRIVES, NORMAL OPERATION
HIGH-SIDE GATE DRIVES, E*-MODE
CH1: HDRVB
CH2: HDRVA
10A Load
CH1: HDRVB
CH2: HDRVA
10A Load
HIGH-SIDE GATE DRIVES, RISE / FALL TIME
LOW-SIDE GATE DRIVES, RISE / FALL TIME
CH1: HDRVB
40A Load
CH1: LDRVB
40A Load
REV. 1.0.1 9/16/03
7
FAN5090
PRODUCT SPECIFICATION
Typical Operating Characteristics (Continued)
DYNAMIC VID CHANGE (1.475–1.575V)
CH1: V
(1.20V Offset)
OUT
CH2: VID2
40A Load
OUTPUT RIPPLE, 60A LOAD
CURRENT SHARING, 50A LOAD
CURRENT SHARING, 15A LOAD
CH1: I
CH2: I
CH1: I
CH2: I
LB
LA
LA
LB
CURRENT LIMIT
DROOP VS. R
DROOP
CH1: Iin
CH2: Vout
4.00
R
= 49.9K
d
3.50
3.00
2.50
2.00
1.50
1.00
0.50
R
d
= 56.2K
0.00
0
5
10 15 20 25 30 35 40 45 50
Rdroop (KΩ)
8
REV. 1.0.1 9/16/03
PRODUCT SPECIFICATION
FAN5090
Typical Operating Characteristics (Continued)
START-UP, 40A LOAD
POWER-DOWN, 40A LOAD
CH1: Vout
CH2: Vin
CH1: Vout
CH2: Vin
LOAD TRANSIENT, 0-40A
LOAD TRANSIENT, 12-52A
CH1: Iout (26mV/A)
CH2: Vout
CH1: Iout (26mV/A)
CH2: Vout (cursors placed at 50mV limits)
CLOSED LOOP RESPONSE
V
OUT
TEMPERATURE VARIATION
40
30
20
120
100
80
1.501
1.500
Phase Margin
1.499
1.498
1.497
1.496
60
10
0
Gain
40
20
0
-10
1.495
1.494
-20
1
10
100
0.1
0
25
50
75
100
FREQUENCY (HZ)
TEMPERATURE (°C)
REV. 1.0.1 9/16/03
9
FAN5090
PRODUCT SPECIFICATION
Application Circuit
Vin
L3
+12V
D3
C5
Cin
+
D1
D2
C2
C1
+5V
R1
Q1
Q3
C8
U1
FAN5090
R10
R11
Q2
Q4
R2
R4
12
11
10
L1
BOOTB
HDRVB
SWB
18
19
VCC
VCore
C6
R3
PWRGD
8
5
4
3
2
1
VID4
VID3
VID2
VID1
VID0
VID4
VID3
VID2
VID1
VID0
LDRVB
PGNDB
BOOTA
Vin
9
C3
C4
13
R5
Q5
Q7
23
22
21
20
6
RT
R6
Q6
Q8
14
15
HDRVA
SWA
L2
ENABLE/SS
DROOP/E*
ILIM
R7
Cout
+
R8
R13
17
16
24
R14
BYPASS
LDRVA
PGNDA
VFB
C10
C9
R9
7
R12
AGND
Figure 2. Application Circuit for 70A VRM 9.x Desktop Application
Table 2. FAN5090 Application Bill of Materials for Figure 2
Reference
U1
QTY
1
Description
Manufacturer / Number
Fairchild FAN5090
FAN5090
Q1-Q8
D1, 2, 3
L1, 2
8
MOSFET, Nch, 30V, 50A, 9mΩ
SCHOTTKY, 40V, 500mA
850nH, 30A, 0.9mΩ
630nH, 15A, 1.7mΩ
2.2Ω, 5%
Fairchild FDD6296
3
Fairchild MBR0540
2
Inter-Technical SCTA5022A-R86K
L3
1
Inter-Technical AK1418160052-R63M
R1, 2, 5, 6
R3, 4, 7, 8, 9
R10
4
5
4.7Ω, 5%
1
10Ω, 5%
R11
1
10K, 5%
R12
1
68.1K, 1%
R13
1
15.0K, 1%
R14
1
56.2K, 1%
C1-6
6
1.0µf, 25V, 10%, X7R
0.1µf, 16V, 10%, X7R
1500µf, 16V, 20%,12mΩ
2200µf, 6.3V, 20%, 12mΩ
C8-10
Cin
3
3
Rubycon 16MBZ1500M
Rubycon 6.3MBZ2200M
Cout
7
10
REV. 1.0.1 9/16/03
PRODUCT SPECIFICATION
FAN5090
Response Time
Application Information
The FAN5090 utilizes leading-edge, not trailing-edge
control. Conventional trailing-edge control turns on the
high-side MOSFET at a clock signal, and then turns it off
when the error amplifier output voltage is equal to the ramp
voltage. As a result, the response time of a trailing-edge
converter can be as long as the off-time of the high-side
driver, nearly an entire switching period. The FAN5090’s
leading-edge control turns the high-side MOSFET on when
the error amplifier output voltage is equal to the ramp volt-
age, and turns it off at the clock signal. As a result, when a
transient occurs, the FAN5090 responds immediately by
turning on the high-side MOSFET. Response time is set by
the internal propagation delays, typically 100nsec. In worst
case, the response time is set by the minimum on-time of the
low-side MOSFET, 330nsec.
Operation
The FAN5090 Controller
The FAN5090 is a programmable synchronous two-phase
DC-DC controller IC. When designed with the appropriate
external components, the FAN5090 can be configured to
deliver more than 50A of output current, for VRM 9.x
applications. The FAN5090 functions as a fixed frequency
PWM step down regulator.
Main Control Loop
Refer to the FAN5090 Block Diagram on page 1. The
FAN5090 consists of two interleaved synchronous buck con-
verters, implemented with summing-mode control. Each
phase has its own current feedback, and there is a common
voltage feedback.
Oscillator
The FAN5090 oscillator section runs at a frequency deter-
mined by a resistor from the RT pin to ground according to
the formula
The two buck converters controlled by the FAN5090 are
interleaved, that is, they run 180° out-of-phase. This mini-
mizes the RMS input ripple current, minimizing the number
of input capacitors required. It also doubles the effective
switching frequency, improving transient response.
27.5 • 109
RT(Ω) = --------------------------
f(Hz)
The FAN5090 implements “summing mode control”, which
is different from both classical voltage-mode and current-
mode control. It provides superior performance to either by
allowing a large converter bandwidth over a wide range of
output loads and external components. No external compen-
sation is required.
The oscillator generates two internal sawtooth ramps, each at
one-half the oscillator frequency, and running 180° out of
phase with each other. These ramps cause the turn-on time of
the two phases to be phased apart. The oscillator frequency
of the FAN5090 can be programmed from 200kHz to
600kHz with each phase running at 100kHz to 300kHz,
respectively. Frequency selection depends on various system
performance criteria, with higher frequency resulting in
smaller components but lower efficiency.
The regulator’s control loop contains two main sections:
the analog control block and the digital control block. The
analog section consists of signal conditioning amplifiers
feeding into a comparator which provides the input to the
digital control block. The signal conditioning section accepts
inputs from a current sensor and a voltage sensor, with the
voltage sensor being common to both phases, and the current
sensor separate for each. The voltage sensor amplifies the
difference between the VFB signal and the reference voltage
from the DAC and presents the output to each of the two
comparators. The current control path for each phase takes
the difference between its PGND and SW pins when the
low-side MOSFET is on, reproducing the voltage across the
MOSFET and thus the input current; It presents the resulting
signal to the same input of its summing amplifier, adding its
signal to the voltage amplifier’s with a certain gain. These
two signals are thus summed together. This sum is then pre-
sented to a comparator looking at the oscillator ramp, which
provides the main PWM control signal to the digital control
block. The oscillator ramps are 180° out-of-phase with each
other, so that the two phases are on alternately.
Quiescent current (Icc) of the FAN5090 is also frequency
dependent:
Icc = 12.7 + 0.006 [(f/2) – 100] mA
Where f is the oscillator frequency in KHz
Remote Voltage Sense
The FAN5090 has true remote voltage sense capability, elim-
inating errors due to trace resistance. To utilize remote sense,
the VFB and AGND pins should be connected as a Kelvin
trace pair to the point of regulation, such as the processor
pins. The converter will maintain the voltage in regulation at
that point. Care is required in layout of these grounds; see
the layout guidelines in this datasheet.
High Current Output Drivers
The FAN5090 contains four high current output drivers that
utilize MOSFETs in a push-pull configuration. The drivers
for the high-side MOSFETs use the BOOT pin for input
power and the SW pin for return. The drivers for the low-side
MOSFETs use the VCC pin for input power and the PGND
The digital control block takes the analog comparator input
to provide the appropriate pulses to the HDRV and LDRV
output pins for each phase. These outputs control the exter-
nal power MOSFETs.
REV. 1.0.1 9/16/03
11
FAN5090
PRODUCT SPECIFICATION
pin for return. Typically, the BOOT pin will use a charge
pump as shown in Figure 2. Note that the BOOT and VCC
pins are separated from the chip’s internal power and ground,
BYPASS and AGND, for switching noise immunity.
with ISC the desired output current limit, RT the oscillator
resistor and RDSon one phase’s low-side MOSFET’s on resis-
tance. Remember to make the RS large enough to include the
effects of initial tolerance and temperature variation on the
MOSFETs’ RDSon
.
Adaptive Delay Gate Drive
Important Note! The oscillator frequency must be selected
before selecting the current limit resistor, because the value
of RT is used in the calculation of RS.
The FAN5090 embodies an advanced design that ensures
minimum MOSFET transition times while eliminating
shoot-through current. It senses the state of the MOSFETs
and adjusts the gate drive adaptively to ensure that they are
never on simultaneously. When the high-side MOSFET turns
off, the voltage on its source begins to fall. When the voltage
there reaches approximately 2.2V, the low-side MOSFETs
gate drive is applied. When the low-side MOSFET turns off,
the voltage at the LDRV pin is sensed. When it drops below
approximately 1.2V, the high-side MOSFET’s gate drive is
applied with 50ns delay.
When an overcurrent is detected, the high-side MOSFETs
are turned off, and the low-side MOSFETs are turned on,
and they remain in this state until the measured current
through the low-side MOSFET has returned to zero amps.
After reaching zero, the FAN5090 soft-starts, ensuring that it
can also safely turn on into a faulted load.
A limitation on the current sense circuit is that ISC • RDS,on
must be less that 375mV. To ensure correct operation, use
ISC • RDS,on ≤ 300mV; between 300mV and 375mV. There
will be some non-linearity in the short-circuit current that is
not accounted for in the equation.
Maximum Duty Cycle
In order to ensure that the current-sensing and charge-
pumping work, the FAN5090 guarantees that the low-side
MOSFET will be on a certain portion of each period. For low
frequencies, this occurs as a maximum duty cycle of approxi-
mately 90%. Thus at 250KHz, with a period of 4µsec, the
low-side will be on at least 4µsec • 10% = 400nsec. At higher
frequencies, this time might fall so low as to be ineffective.
The FAN5090 provides a minimum low-side on-time of
approximately 330nsec, regardless of duty cycle.
As an example, consider the typical characteristics of the
circuit using two FDD6696 low-side MOSFETs (8mΩ @
25°C, 10.4mΩ @ 95°C, each), RT = 56.2K, and RS = 75K:
The converter maintains a normal load regulation character-
istic until the voltage across the MOSFETs exceeds the
internal short circuit threshold of 75K / (3.33 x 56.2K x
5.2mΩ) = 77A. At this point, the internal comparator trips
and signals the controller to leave on the low-side MOSFETs
and keep off the high-side MOSFETs. The inductor current
decreases, and power is not applied again until inductor
current reaches 0A and the converter attempts a new
soft-start cycle.
Current Sensing
The FAN5090 has two independent current sensors, one for
each phase. Current sensing is accomplished by measuring
the source-to-drain voltage of the low-side MOSFET during
its on-time. Each phase has its own power ground pin, to per-
mit the phases to be placed in different locations without
affecting measurement accuracy. For best results, it is impor-
tant to connect the PGND and SW pins for each phase as a
Kelvin trace pair directly to the source and drain, respec-
tively, of the appropriate low-side MOSFET. Care is required
in the layout of these grounds; see the layout guidelines in
this datasheet.
Internal Voltage Reference
The reference included in the FAN5090 is a precision band-
gap voltage reference. Its internal resistors are precisely
trimmed to provide a near zero temperature coefficient (TC).
Based on the reference is the output from an integrated 5-bit
DAC. The DAC monitors the 5 voltage identification pins,
VID0-4, and scales the reference voltage from 1.100V to
1.850V in 25mV steps.
Current Sharing
The two independent current sensors of the FAN5090 operate
with their independent current control loops to guarantee that
the two phases each deliver half of the total output current.
Mismatch between the two phases occurs only if there is a
mismatch between the RDSon of the low-side MOSFETs.
BYPASS Reference
The internal logic of the FAN5090 runs on 5V. To permit the
IC to run with 12V only, it produces 5V internally with a
linear regulator, whose output is present on the BYPASS pin.
This pin should be bypassed with a 100nF capacitor for noise
suppression. The BYPASS pin should not have any external
load attached to it.
Short Circuit Current Characteristics (ILIM pin)
The FAN5090 short circuit current characteristic includes a
function that protects the DC-DC converter from damage in
the event of a short circuit. The short circuit limit is set with
the RS resistor, as given by the formula
Dynamic Voltage Adjustment
The FAN5090 can have its output voltage dynamically
adjusted to accommodate low power modes. The designer
must ensure that the transitions on the VID lines all occur
RS(Ω) = ISC • RDS, on • RT • 3.33
12
REV. 1.0.1 9/16/03
PRODUCT SPECIFICATION
FAN5090
simultaneously (within less than 500nsec) to avoid false codes
generating undesired output voltages. The Power Good flag
tracks the VID codes, but has a 500µsec delay transitioning
from high to low; long enough to ensure that there will not
be any glitches during dynamic voltage adjustment.
VDroop • RT
RDroop(Ω) = ------------------------------------
Imax • RDS, on
with VDroop the desired droop voltage, RT the oscillator
resistor, Imax the output current at which the droop is desired,
and RDSon the on-state resistance of one phase’s low-side
MOSFET.
Power Good (PWRGD)
The FAN5090 Power Good function is designed in accor-
dance with the Pentium IV DC-DC converter specifications
and provides a continuous voltage monitor on the VFB pin.
The circuit compares the VFB signal to the VREF voltage
and outputs an active-low interrupt signal to the CPU should
the power supply voltage deviate more than -12% of its
nominal setpoint. The Power Good flag provides no control
functions to the FAN5090.
Important Note! The oscillator frequency must be selected
before selecting the droop resistor, because the value of RT is
used in the calculation of RDroop
.
Over-Voltage Protection
The FAN5090 constantly monitors the output voltage for
protection against over-voltage conditions. If the voltage at
the VFB pin exceeds 2.2V, an over-voltage condition is
assumed and the FAN5090 latches on the external low-side
MOSFET and latches off the high-side MOSFET. The
DC-DC converter returns to normal operation only after VCC
has been recycled.
Output Enable/Soft Start (ENABLE/SS)
The FAN5090 will accept an open collector/TTL signal for
controlling the output voltage. The low state disables the
output voltage. When disabled, the PWRGD output is in the
low state.
Over Temperature Protection
Even if an enable is not required in the circuit, this pin
should have an attached capacitor (typically 100nF) to soft-
start the switching. A softstart capacitor may be chosen by
the formula:
If the FAN5090 die temperature exceeds approximately
150°C, the IC shuts itself off. It remains off until the temper-
ature has dropped approximately 25°C, before it resumes
normal operation.
CSS (1.7 + 0.9074 • VOUT
)
-------------- ---------------------------------------------------------
tD
=
•
10µA
2.5
E* Mode
Further enhancements in light-load efficiency can be
obtained by operating the FAN5090 in E* mode. When the
DROOP pin is pulled to the 5V BYPASS voltage, the “A”
phase of the FAN5090 is completely turned off, reducing the
consumed gate charge power by half. E* mode can be
implemented using the circuit shown in figure 3.
where: tD is the delay time before the output starts to ramp
CSS VOUT • 0.9
-------------- ----------------------------
tR
=
•
10µA
VIN
tR is the ramp time of the output
CSS = softstart cap
VOUT = nominal output voltage
B
YPASS
(pin 6)
However, C must be ≥ 100nF.
FJV4105R
FJV3102R
E* Mode
(HIGH)
D
ROOP
(pin 21)
Programmable Active Droop™
The FAN5090 features Programmable Active Droop™: As
the output current increases, the output voltage drops propor-
tionately an amount programmed by an external resistor.
This feature allows maximum headroom for transient
response of the converter. The current is sensed losslessly by
measuring the voltage across the low-side MOSFET during
its on time. Consult the section on current sensing for details.
The droop is adjusted by the droop resistor changing the gain
of the current loop. Note that this method makes the droop
dependent on the temperature and initial tolerance of the
MOSFET, and the droop must be calculated taking account
of these tolerances. Given a maximum output current, the
amount of droop can be programmed with a resistor to
ground on the droop pin, according to the formula:
R
DROOP
Figure 3. Implementing E* Mode Control
Note: The HDRV charge pump should be connected to
“Phase B” of the FAN5093 circuit.
REV. 1.0.1 9/16/03
13
FAN5090
PRODUCT SPECIFICATION
Component Selection
E • f • Rgate
•
PRgate = ------------------------------------------------ = 482nJ • 300KHz
(Rgate + Rinternal
4.7Ω
)
MOSFET Selection
This application requires N-channel Enhancement Mode Field
Effect Transistors. Desired characteristics are as follows:
-------------------------------- = 131mW
4.7Ω + 0.5Ω
and each gate resistor thus requires a 1/4W resistor to ensure
worst case power dissipation.
• Low Drain-Source On-Resistance,
• RDS,ON < 10mΩ (lower is better);
• Power package with low Thermal Resistance;
• Drain-Source voltage rating > 15V;
• Low gate charge, especially for higher frequency
operation.
Inductor Selection
Choosing the value of the inductor is a tradeoff between
allowable ripple voltage and required transient response.
A smaller inductor produces greater ripple while producing
better transient response. In any case, the minimum induc-
tance is determined by the allowable ripple. The first order
equation (close approximation) for minimum inductance for
a two-phase converter is:
For the low-side MOSFET, the on-resistance (RDS,ON) is the
primary parameter for selection. Because of the small duty
cycle of the high-side, the on-resistance determines the
power dissipation in the low-side MOSFET and therefore
significantly affects the efficiency of the DC-DC converter.
For high current applications, it may be necessary to use two
MOSFETs in parallel for the low-side for each phase.
V
in – 2 • Vout Vout
ESR
---------------------------------- ----------- -----------------
Lmin
where:
=
•
•
f
Vin Vripple
For the high-side MOSFET, the gate charge is as important as
the on-resistance, especially with a 12V input and with higher
switching frequencies. This is because the speed of the transi-
tion greatly affects the power dissipation. It may be a good
trade-off to select a MOSFET with a somewhat higher RDS,on
if by so doing a much smaller gate charge is available. For
high current applications, it may be necessary to use two
MOSFETs in parallel for the high-side for each phase.
Vin = Input Power Supply
Vout = Output Voltage
f = DC/DC converter switching frequency
ESR = Equivalent series resistance of all output capacitors in
parallel
,
Vripple = Maximum peak to peak output ripple voltage
budget.
At the FAN5090’s highest operating frequencies, it may be
Output Filter Capacitors
necessary to limit the total gate charge of both the high-side
and low-side MOSFETs together, to avert excess power dis-
sipation in the IC.
The output bulk capacitors of a converter help determine its
output ripple voltage and its transient response. It has
already been seen in the section on selecting an inductor that
the ESR helps set the minimum inductance. For most con-
verters, the transient response and the output ripple voltage
determines the number of capacitors. Selection is typically
dominated by the ESR and not the capacitance value. That is,
in order to achieve the necessary ESR to meet the transient
and ripple requirements, the capacitance value required is
already very large.
Gate Resistors
Use of a gate resistor on some MOSFETs may be required.
The gate resistor prevents high-frequency oscillations caused
by the trace inductance ringing with the MOSFET gate
capacitance. The gate resistors should be located physically
as close to the MOSFET gate as possible.
The gate resistor also limits the power dissipation inside the
IC, which could otherwise be a limiting factor on the switch-
ing frequency. It may thus carry significant power, especially
at higher frequencies. As an example: The FDB7045L has a
maximum gate charge of 70nC at 5V, and an input capaci-
tance of 5.4nF. The total energy used in powering the gate
during one cycle is the energy needed to get it up to 5V, plus
the energy to get it up to 12V:
For higher frequency applications, particularly those running
the FAN5090 oscillator at >1MHz, Oscon or ceramic capaci-
tors may be considered. They have much smaller ESR than
comparable electrolytics, but also much smaller capacitance.
The output capacitance should also include a number of
small value ceramic capacitors placed as close as possible to
the processor; 0.1µF and 0.01µF are recommended values.
2
1
2
1
2
2
--
E = QV + C • ∆V = 70nC • 5V + --5.4nF • (12V – 5V)
Input Filter
= 482nJ
The DC-DC converter design may include an input inductor
between the system main supply and the converter input as
shown in Figure 2. This inductor serves to isolate the main
supply from the noise in the switching portion of the DC-DC
converter, and to limit the inrush current into the input capac-
itors during power up.
This power is dissipated every cycle, and is divided between
the internal resistance of the FAN5090 gate driver and the
gate resistor. Thus,
14
REV. 1.0.1 9/16/03
PRODUCT SPECIFICATION
FAN5090
It is necessary to have some low ESR capacitors at the input
to the converter. These capacitors deliver current when the
high side MOSFET switches on. Because of the interleaving,
the number of such capacitors required is greatly reduced
from that required for a single-phase buck converter. Figure
2 shows 3 x 1500µF, but the exact number required will vary
with the output voltage and current, according to the formula
PC Motherboard Sample Layout and Gerber File
A reference design for motherboard implementation of the
FAN5090 along with the PCAD layout Gerber file and silk
screen can be obtained through your local Fairchild repre-
sentative.
FAN5090 Evaluation Board
Fairchild provides an evaluation board to verify the system
level performance of the FAN5090. It serves as a guide to
performance expectations when using the supplied external
components and PCB layout. Please contact your local
Fairchild representative for an evaluation board.
Iout
Irms
=
2D – 4D2
--------
2
for the two phase FAN5090, where D is the duty cycle
(Vout / Vin). Capacitor ripple current rating is a function of
temperature, and so the manufacturer should be contacted to
find out the ripple current rating at the expected operational
temperature.
Additional Information
For additional information contact your local Fairchild
representative.
PCB Layout Guidelines
• Placement of the MOSFETs relative to the FAN5090 is
critical. Place the MOSFETs so that the trace length of the
HDRV and LDRV pins of the FAN5090 to the FET gates
is minimized. A long lead length on these pins will cause
high amounts of ringing due to the inductance of the trace
and the gate capacitance of the FET. This noise radiates
throughout the board, and, because it is switching at such
a high voltage and frequency, it is very difficult to
suppress.
• In general, all of the noisy switching lines should be kept
away from the quiet analog section of the FAN5090. That
is, traces that connect to pins LDRV, HDRV, SW, BOOT,
and PGND should be kept far away from the traces that
connect to pins 1 through 7, and pins 18-24.
• Place the decoupling capacitors as close to the FAN5090
pins as possible. Extra lead length on these reduces their
ability to suppress noise.
• Each power and ground pin should have its own via to the
appropriate plane. This helps provide isolation between
pins.
• Place the MOSFETs, inductor, and Schottky of a given
phase as close together as possible for the same reasons as
in the first bullet above. Place the input bulk capacitors as
close to the drains of the high side MOSFETs as possible.
Placing a 1.0µF decoupling cap directly on the drain of
each high side MOSFET helps to suppress some of the
high frequency switching noise on the input of the DC-
DC converter.
• Place the output bulk capacitors as close to the CPU as
possible to optimize their ability to supply instantaneous
current to the load in the event of a current transient.
Additional space between the output capacitors and the
CPU will allow the parasitic resistance of the board traces
to degrade the DC-DC converter’s performance under
severe load transient conditions, causing higher voltage
deviation.
REV. 1.0.1 9/16/03
15
FAN5090
PRODUCT SPECIFICATION
Mechanical Dimensions – 24 Lead TSSOP
Notes:
Inches
Millimeters
Min. Max.
Symbol
Notes
1. Dimensioning and tolerancing per ANSI Y14.5M-1982.
Min.
Max.
2. "D" and "E" do not include mold flash. Mold flash or
protrusions shall not exceed .006 inch (0.15mm).
A
—
.047
.006
.012
.008
.316
.177
—
1.20
0.15
0.30
0.20
7.90
4.50
A1
B
.002
.007
.004
.303
.169
0.05
0.19
0.09
7.70
4.30
3. "L" is the length of terminal for soldering to a substrate.
4. Terminal numbers are shown for reference only.
5. Symbol "N" is the maximum number of terminals.
C
D
E
2
2
e
.026 BSC
.252 BSC
.018 .030
0.65 BSC
6.40 BSC
0.45 0.75
H
L
3
5
N
α
24
24
0°
8°
0°
8°
ccc
—
.004
—
0.10
D
E
H
C
A1
A
α
SEATING
PLANE
– C –
L
B
LEAD COPLANARITY
ccc C
e
16
REV. 1.0.1 9/16/03
FAN5090
PRODUCT SPECIFICATION
Ordering Information
Product Number
Description
Package
FAN5090MTC
VRM 9.x DC-DC Controller
VRM 9.x DC-DC Controller
24 pin TSSOP
FAN5090MTCX
24 pin TSSOP in Tape and Reel
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO
ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME
ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
9/16/03 0.0m 005
Stock#DS30005090
2003 Fairchild Semiconductor Corporation
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