FAN5094MTC [ROCHESTER]
3 A SWITCHING CONTROLLER, 2000 kHz SWITCHING FREQ-MAX, PDSO28, TSSOP-28;
| 型号： | FAN5094MTC |
| 厂家： | 
Rochester Electronics |
| 描述： | 3 A SWITCHING CONTROLLER, 2000 kHz SWITCHING FREQ-MAX, PDSO28, TSSOP-28 开关 光电二极管 |
| 文件： | 总23页 (文件大小：865K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
www.fairchildsemi.com
FAN5094
Multi-Phase Interleaved Buck Converter
Features
Description
• Programmable output from 1.100V to 1.850V in 25mV
steps using an integrated 5-bit DAC
The FAN5094 is a synchronous multi-phase DC-DC
controller IC which provides a highly accurate,
• Two interleaved synchronous phases per IC for maximum
performance
• Up to 4 phase power system
• Built-in current sharing between phases and between ICs
• Frequency and phase synchronization between ICs
• Remote sense and Programmable Active Droop™
• High precision voltage reference
• High speed transient response
• Programmable frequency from 200KHz to 2MHz
• Adaptive delay gate switching
• Integrated high-current gate drivers
• Integrated Power Good, OV, UV, Enable/Soft Start
functions
programmable output voltage for all high-performance
processors. Two interleaved synchronous buck regulator
phases with built-in current sharing operate 180° out of
phase to provide the fast transient response needed to satisfy
high current applications while minimizing external
components. FAN5094s can be paralleled while maintaining
both frequency and phase synchronization and ensuring
current sharing in a high-power system. The FAN5094
features remote voltage sensing, Programmable Active
Droop and advanced response for optimal converter
transient response with minimum output capacitance. It has
integrated high-current gate drivers with adaptive delay gate
switching, eliminating the need for external drive devices.
These make it possible to create power supplies running at a
switching frequency as high as 4MHz, for ultra-high density.
The FAN5094 uses a 5-bit D/A converter to program the
output voltage from 1.100V to 1.850V in 25mV steps with
an accuracy of 0.5%. The FAN5094 uses a high level of
integration to deliver load currents in excess of 150A from a
12V source with minimal external circuitry. The FAN5094
also offers integrated functions including Power Good,
Output Enable/Soft Start, under-voltage lockout, over-
voltage protection, and current limiting with independent
current sense on each phase. It is available in a 28-pin
TSSOP package.
• Drives N-channel MOSFETs
• Operation optimized for 12V operation
• High efficiency mode at light load
• Overcurrent protection using MOSFET sensing
• 28 pin TSSOP package
Applications
• Power supply for Pentium®IV
• Power supply for Athlon®
• Power supply for Ultrasparc™
• VRM for Pentium IV processor
• Programmable step-down power supply
Block Diagram
+12V
VFB
FAN5094
+12V
+
PHASE
VFB
CLK
ISHR
ISHR
Processor
+
+12V
CLK
PHASE
+12V
FAN5094
VFB
Pentium is a registered trademark of Intel Corporation. Athlon is a registered trademark of AMD. Programmable Active Droop is a trademark of Fairchild Semiconductor.
REV. 1.0.2 5/13/02
FAN5094
PRODUCT SPECIFICATION
Pin Assignments
1
28
VFB
RT
ENABLE/SS
VID0
VID1
VID2
2
3
27
26
DROOP/E*
ISHR
PHASE
PWRGD
VCC
LDRVA
GNDA
ISNSA
SWA
4
5
6
7
25
24
23
22
VID3
VID4
CLK
BYPASS
AGND
LDRVB
FAN5094
8
9
21
20
19
18
17
16
15
GNDB
ISNSB
10
11
12
13
14
SWB
HDRVB
HDRVA
BOOTA
BOOTB
Pin Definitions
Pin Number
Pin Name
Pin Function Description
1-5
VID0-4
Voltage Identification Code Inputs. These open collector/TTL compatible
inputs will program the output voltage over the ranges specified in Table 1.
6
CLK
Clock. When PHASE is high, this pin puts out a clock signal synchronized
180° out of phase with the internal master clock. When PHASE is low, this pin
is an input for a synchronizing clock signal.
7
8
BYPASS
AGND
5V Rail. Bypass this pin with a 0.1µF ceramic capacitor to AGND.
Analog Ground. Return path for low power analog circuitry. This pin should
be connected to a low impedance system ground plane to minimize ground
loops.
9
LDRVB
Low Side FET Driver for B. Connect this pin to the gate of an N-channel
MOSFET for synchronous operation. The trace from this pin to the MOSFET
gate should be <0.5”.
10
11
12
GNDB
ISNSB
SWB
Ground B. Ground-side current sense pin. Connect directly to low-side
MOSFET source, or to sense resistor ground.
Current Sense B. Sensor side of current sense. Attach to low-side MOSFET
drain, or to source side of sense resistor.
High side driver source and low side driver drain switching node B. Gate
drive return for high side MOSFET, and negative input for low-side MOSFET
current sense.
13
HDRVB
High Side FET Driver B. Connect this pin to the gate of an N-channel
MOSFET. The trace from this pin to the MOSFET gate should be <0.5”.
14
15
16
BOOTB
BOOTA
HDRVA
Bootstrap B. Input supply for high-side MOSFET.
Bootstrap A. Input supply for high-side MOSFET.
High Side FET Driver A. Connect this pin to the gate of an N-channel
MOSFET. The trace from this pin to the MOSFET gate should be <0.5”.
17
18
SWA
High side driver source and low side driver drain switching node A. Gate
drive return for high side MOSFET, and negative input for low-side MOSFET
current sense.
ISNSA
Current Sense A. Sensor side of current sense. Attach to low-side MOSFET
drain, or to source side of sense resistor.
2
REV. 1.0.2 5/13/02
PRODUCT SPECIFICATION
FAN5094
Pin Definitions (continued)
Pin Number
Pin Name
GNDA
Pin Function Description
19
Ground A. Ground-side current sense pin. Connect directly to low-side
MOSFET source, or to sense resistor ground.
20
LDRVA
Low Side FET Driver for A. Connect this pin to the gate of an N-channel
MOSFET for synchronous operation. The trace from this pin to the MOSFET
gate should be <0.5”.
21
22
23
VCC
VCC. Internal IC supply. Connect to system 12V supply, and decouple with a
0.1µF ceramic capacitor.
PWRGD
PHASE
Power Good Flag. An open collector output that will be logic LOW if the
output voltage is not within +/-5% of the nominal output voltage setpoint.
Phase Control. Connecting this pin to bypass causes a synchronized clock
signal to appear on CLK. Connecting this pin to ground allows the CLK pin to
accept a clock signal for synchronization.
24
25
ISHR
Current Share. Connecting this pin to the ISHR pin of another FAN5094
enables current sharing.
DROOP/E*
Droop Control/E*-mode Control. A resistor from this pin to ground sets the
amount of droop by controlling the gain of the current sense amplifier.
Connecting this pin to bypass turns off Phase A.
26
ENABLE/SS
Output Enable. A logic LOW on this pin will disable the output. An internal
current source allows for open collector control. This pin also doubles as soft
start.
27
28
RT
Frequency Set. A resistor from this pin to ground sets the switching
frequency. See Apps section.
VFB
Voltage Feedback. Connect to the desired regulation point at the output of
the converter.
Absolute Maximum Ratings
Parameter
Min.
Typ.
Max.
15
22
6
Units
V
Supply Voltage VCC
Supply Voltages BOOTA, BOOTB
Voltage Identification Code Inputs, VID0-VID4
VFB, ENABLE/SS, PWRGD, PHASE, CLK
SW, ISNS
V
V
6
V
-3
15
0.5
V
PGNDA, PGNDB to AGND
Gate Drive Current, peak pulse
Junction Temperature, TJ
-0.5
V
3
A
-55
-65
150
150
°C
°C
°C
°C/W
Storage Temperature
Lead Soldering Temperature, 10 seconds
Thermal Resistance Junction-to-case, ΘJA
300
16
REV. 1.0.2 5/13/02
3
FAN5094
PRODUCT SPECIFICATION
Recommended Operating Conditions
Parameter
Conditions
Min.
16
Typ.
Max.
17
Units
V
Output Driver Supply, Boot
VCC
See Figure 1
10.8
2.0
12
13.2
V
Input Logic HIGH
Input Logic LOW
Ambient Operating Temperature
V
0.8
70
V
0
°C
Electrical Specifications
(VCC = 12V, VOUT = 1.500V, and TA = +25°C using circuit in Figure 1, unless otherwise noted.)
The • denotes specifications which apply over the full operating temperature range.
Parameter
Output Voltage
Conditions
See Table I
Min.
Typ.
Max.
Units
•
1.100
1.850
V
A
Output Current
60
Internal Reference Voltage
Initial Voltage Setpoint
Output Temperature Drift
Line Regulation
1.4925 1.5000 1.5075
V
ILOAD = 0.8A
1.488
1.500
+5
1.512
V
TA = 0 to 70°C
mV
µV
mV
%VOUT
V
VIN = 11.4V to 12.6V
ILOAD = 0.8A to Imax
RDROOP = TBD to TBD
ILOAD = 0.8A to Imax
•
+130
-100
Droop3
-90
-10
-110
0
Programmable Droop Range
Total Output Variation, Steady
State1
•
•
1.430
1.570
Total Output Variation,
Transient2
ILOAD = 0.8A to Imax
1.430
1.570
V
Response Time
∆VOUT = 10mV
100
1.0
0.2
0.5
0.2
0.5
20
nsec
Ω
Gate Drive On-Resistance
Upper Drive Low Voltage
Upper Drive High Voltage
Lower Drive Low Voltage
Lower Drive High Voltage
Output Driver Rise & Fall Time
Current Mismatch
VHDRV – VSW at Isink = 10µA
VBOOT – VHDRV at Isource = 10µA
Isink = 10µA
V
V
V
VCC – VLDRV at Isource = 10µA
See Figure 2
V
nsec
%
RDS,on(A) = RDS,on(B)
5
Output Overvoltage Detect
Efficiency
•
•
2.1
2.3
V
ILOAD = Imax
ILOAD = 2A, E*-mode enabled
,
85
70
%
Oscillator Frequency
Oscillator Range
RT = 41.2KΩ
450
200
600
750
KHz
KHz
%
RT = 125KΩ to 12.5KΩ
RT = 125KΩ
2000
Maximum Duty Cycle
Minimum LDRV on-time
Input Low Current, VID pins
Soft Start Current
90
RT=12.5KΩ
330
nsec
µA
VVID = 0.4V
50
10
µA
Enable Threshold
ON
1.0
V
OFF
0.4
4.75
220
BYPASS Voltage
5
5.25
V
BYPASS Capacitor
1000
nF
4
REV. 1.0.2 5/13/02
PRODUCT SPECIFICATION
FAN5094
Electrical Specifications (continued)
(VCC = 12V, VOUT = 1.500V, and TA = +25°C using circuit in Figure 1, unless otherwise noted.)
The • denotes specifications which apply over the full operating temperature range.
Parameter
Conditions
Min.
Typ.
Max.
Units
PWRGD Threshold
Logic LOW, minimum
Logic LOW, maximum
•
•
85
108
88
111
92
115
%Vout
PWRGD Hysteresis
PWRGD Output Voltage
PWRGD Delay
20
mV
V
Isink = 4mA
0.4
High → Low
500
9.5
1.0
20
µsec
V
12V UVLO
•
8.5
10.5
UVLO Hysteresis
V
12V Supply Current
Over Temperature Shutdown
Over Temperature Hysteresis
HDRV and LDRV open
mA
°C
°C
150
25
Notes:
1. Steady State Voltage Regulation includes Initial Voltage Setpoint, Output Ripple and Output Temperature Drift and is
measured at the converter’s VFB sense point.
2. As measured at the converter’s VFB sense point. For motherboard applications, the PCB layout should exhibit no more than
0.2mΩ trace resistance between the converter’s output capacitors and the CPU. Remote sensing should be used for optimal
performance.
3. Using the VFB pin for remote sensing of the converter’s output at the load, the converter will be in compliance with Intel’s
VRM 9.0 specification of +70, -70mV.
REV. 1.0.2 5/13/02
5
FAN5094
PRODUCT SPECIFICATION
Table 1. Output Voltage Programming Codes
VID4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VID3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
VID2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
VID1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
VID0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
VOUT to CPU
OFF
1.100V
1.125V
1.150V
1.175V
1.200V
1.225V
1.250V
1.275V
1.300V
1.325V
1.350V
1.375V
1.400V
1.425V
1.450V
1.475V
1.500V
1.525V
1.550V
1.575V
1.600V
1.625V
1.650V
1.675V
1.700V
1.725V
1.750V
1.775V
1.800V
1.825V
1.850V
Note:
1. 0 = VID pin is tied to GND.
1 = VID pin is pulled up to 5V.
6
REV. 1.0.2 5/13/02
PRODUCT SPECIFICATION
FAN5094
Internal Block Diagram
+12V
21
BYPASS
7
+12V
15
16
17
18
5V Reg
27
Master
Clock
f/2
÷2
+
-
Digital
Control
+12V
20
19
f/2
23
-
PHASE
+
-
+
6
CLK
VO
+12V
14
13
-
+
12
11
Digital
Control
-
+
+12V
9
5-Bit
DAC
Power
Good
10
1
2
3
4
5
26
ENABLE/SS
22
24
8
28
25
VID2 VID4
VID0
VID1
PWRGD
ISHR
AGND
DROOP/E*
VID3
REV. 1.0.2 5/13/02
7
FAN5094
PRODUCT SPECIFICATION
Typical Operating Characteristics
(VCC = 12V, and TA = +25°C using circuit in Figure 1 , unless otherwise noted.)
EFFICIENCY VS. OUTPUT CURRENT
88
V
= 1.850V
OUT
86
84
82
80
78
76
74
72
70
68
66
64
V
= 1.550V
OUT
0
10
20
30
40
50
60
OUTPUT CURRENT (A)
TRANSIENT RESPONSE, 0.5A TO 50A
TRANSIENT RESPONSE, 50A to 0.5A
1.590V
1.550V
1.480V
1.590V
1.550V
1.480V
TIME (20µs/DIVISION)
TIME (20µs/DIVISION)
HIGH-SIDE GATE DRIVES, NORMAL OPERATION
HIGH-SIDE GATE DRIVES, E*-MODE
TIME (500ns/DIVISION)
TIME (500ns/DIVISION)
8
REV. 1.0.2 5/13/02
PRODUCT SPECIFICATION
FAN5094
Typical Operating Characteristics (Continued)
OUTPUT RIPPLE VOLTAGE
GATE DRIVE RISE TIME
TIME (1µs/DIVISION)
TIME (50ns/DIVISION)
GATE DRIVE FALL TIME
ADAPTIVE GATE DELAY
TIME (50ns/DIVISION)
TIME (10ns/DIVISION)
POWER GOOD DURING DYNAMIC
VOLTAGE ADJUSTMENT
CURRENT SHARING BETWEEN INDUCTORS
TIME (500ns/DIVISION)
TIME (200µs/DIVISION)
REV. 1.0.2 5/13/02
9
FAN5094
PRODUCT SPECIFICATION
Typical Operating Characteristics (Continued)
Droop vs. R
Droop
, RT = 43KΩ
V
TEMPERATURE VARIATION
OUT
1.501
1.500
180
160
140
120
100
80
1.499
1.498
1.497
1.496
1.495
1.494
60
40
20
0
0
5
10 15 20 25 30 35 40 45 50
(KΩ)
0
25
70
100
R
TEMPERATURE (°C)
Droop
10
REV. 1.0.2 5/13/02
PRODUCT SPECIFICATION
FAN5094
Application Circuit
+5V
+12V
D1
D2
L1 (Optional)
D3
C5
+12V
C4
+12V
+12V
C
R5
IN
Q1
Q2
L2
R6
VID4
VID3
C2
A
VID2
VID1
VID0
1
2
3
4
5
6
7
8
9 10 11 12 13 14
VO
U1
FAN5094
C
OUT
+12V
28 27 26 25 24 23 22 21 20 19 18 17 16 15
ENABLE/SS
R7
R8
C1
Q3
L3
B
R3
R2
Q4
PWRGD
+5V
R1
+12V
R4
C3
+12V
R12
Q5
Q6
L4
R13
C6
A
1
2
3
4
5
6
7
8
9 10 11 12 13 14
U2
FAN5094
28 27 26 25 24 23 22 21 20 19 18 17 16 15
B
R10
R9
+12V
R11
C7
Figure 1. Three-Phase Application Circuit for 65A Willamette Processor
REV. 1.0.2 5/13/02
11
FAN5094
PRODUCT SPECIFICATION
Table 2. FAN5094 Application Bill of Materials for Figure 1
Manufacturer
Requirements/
Comments
Reference
Part #
Quantity
Description
C1, C3-5, C7
Panasonic
5
100nF, 50V Capacitor
ECU-V1H104ZFX
Any
C2, C6
CIN
2
2
1µF Ceramic Capacitor
Rubycon
16MBZ1500M
1500µF, 16V Electrolytic
IRMS = 5.4A @ 65°C
ESR ≤ 13mΩ
COUT
Rubycon
6.3MBZ2200M
5
3
2200µF, 6.3V Electrolytic
D1-3
Fairchild
0.5A, 20V Schottky Diode
MBR0520
L1
Coiltronics
DR127-1R5
Optional 1.5µH, 14A Inductor
DCR ~ 3mΩ
See Note 1.
L2-4
Coiltronics
DR127-R47
3
3
3
470nH, 19A Inductor
N-Channel MOSFET
DCR ~ 2mΩ
Q1, Q3, Q5
Q2, Q4, Q6
Fairchild
FDB6035AL
R
DS(ON) = 17mΩ @
VGS = 4.5V
N-Channel MOSFET with RDS(ON) = 6.5mΩ @
Fairchild
FDB6676S
Schottky
VGS = 10V
R1
Any
Any
Any
Any
Any
1
2
2
2
6
2
10KΩ
R2, R9
R3, R10
R4, R11
R5-8, R12-13
U1-2
24.9KΩ
2KΩ
10Ω
4.7Ω
Fairchild
DC/DC Controller
FAN5094M
Notes:
1. Inductor L1 is recommended to isolate the 12V input supply from noise generated by the MOSFET switching. L1 may be
omitted if desired.
2. For a spreadsheet on MOSFET selections, refer to Applications Bulletin AB-8.
12
REV. 1.0.2 5/13/02
PRODUCT SPECIFICATION
FAN5094
+5V
+12V
D1
D2
L1 (Optional)
+12V
D3
C5
+12V
C4
+12V
C
R5
IN
Q1
Q2
L2
R6
VID4
VID3
C2
A
VID2
VID1
VID0
1
2
3
4
5
6
7
8
9 10 11 12 13 14
VO
U1
FAN5094
C
OUT
+12V
28 27 26 25 24 23 22 21 20 19 18 17 16 15
ENABLE/SS
R7
R8
C1
Q3
L3
B
R3
R2
Q4
PWRGD
+5V
R1
+12V
R4
C3
+12V
R12
Q5
Q6
L4
R13
C6
A
1
2
3
4
5
6
7
8
9 10 11 12 13 14
U2
FAN5094
+12V
28 27 26 25 24 23 22 21 20 19 18 17 16 15
R14
Q7
Q8
L5
B
R10
R9
R15
+12V
R11
C7
Figure 2. Four-Phase Application Circuit for 81A Northwood Processor
REV. 1.0.2 5/13/02
13
FAN5094
PRODUCT SPECIFICATION
Table 3. FAN5094 Application Bill of Materials for Figure 2
Reference
C1, C3-5, C7 Panasonic
ECU-V1H104ZFX
Any
Manufacturer Part # Quantity
Description
Requirements/Comments
5
100nF, 50V Capacitor
C2, C6
CIN
2
2
1µF Ceramic Capacitor
1500µF, 16V Electrolytic
°
IRMS = 5.4A @ 65 C
Rubycon
16MBZ1500M
COUT
D1-3
L1
Rubycon
6.3MBZ2200M
9
3
2200µF, 6.3V Electrolytic ESR ≤ 13mΩ
Fairchild
MBR0520
0.5A, 20V Schottky Diode
Coiltronics
DR127-1R5
Optional 1.5µH, 14A Inductor
DCR ~ 3mΩ. See Note 1.
DCR ~ 2mΩ
L2-5
Coiltronics
DR127-R47
4
4
4
470nH, 19A Inductor
N-Channel MOSFET
Q1, Q3, Q5,
Q7
Fairchild
FDB6035AL
R
DS(ON) = 17mΩ @
GS = 4.5V
N-Channel MOSFET with RDS(ON) = 6.5mΩ @
V
Q2, Q4, Q6,
Q8
Fairchild
FDB6676S
Schottky
VGS = 10V
R1
Any
Any
Any
Any
1
2
2
2
8
1
10KΩ
R2, R9
R3, R10
R4, R11
24.9KΩ
2KΩ
10Ω
R5-8, R12-15 Any
4.7Ω
U1-U2
Fairchild
FAN5094M
DC/DC Controller
Notes:
1. Inductor L1 is recommended to isolate the 12V input supply from noise generated by the MOSFET switching. L1 may be
omitted if desired.
2. For a spreadsheet on MOSFET selections, refer to Applications Bulletin AB-8.
Test Parameters
t
t
R
F
90%
90%
HIDRV
2V
2V
10%
t
10%
t
DT
DT
2V
2V
LODRV
Figure 3. Output Drive Timing Diagram
14
REV. 1.0.2 5/13/02
PRODUCT SPECIFICATION
FAN5094
output pins for each phase. These outputs control the exter-
nal power MOSFETs.
Application Information
Operation
Remote Voltage Sense
The FAN5094 has true remote voltage sense capability, elim-
inating errors due to trace resistance. To utilize remote sense,
the VFB and AGND pins should be connected as a Kelvin
trace pair to the point of regulation, such as the processor
pins. The converter will maintain the voltage in regulation at
that point. Care is required in layout of these grounds; see
the layout guidelines in this datasheet.
The FAN5094 Controller
The FAN5094 is a programmable synchronous multi-phase
DC-DC controller IC. When designed around the appropriate
external components, the FAN5094 can be configured to
deliver more than 100A of output current, as appropriate for
the new generation of high-current processors. The
FAN5094 functions as a fixed frequency PWM step down
regulator, with a high efficiency mode (E*) at light load.
High Current Output Drivers
The FAN5094 contains four high current output drivers that
utilize MOSFETs in a push-pull configuration. The drivers
for the high-side MOSFETs use the BOOT pin for input
power and the SW pin for return. The drivers for the low-side
MOSFETs use the VCC pin for input power and the PGND
pin for return. Typically, the BOOT pin will use a charge
pump as shown in Figures 1–2. Note that the BOOT and
VCC pins are separated from the chip’s internal power and
ground, BYPASS and AGND, for switching noise immunity.
Main Control Loop
Refer to the FAN5094 Block Diagram on page 7. The
FAN5094 consists of two interleaved synchronous buck con-
verters, implemented with summing-mode control. Each
phase has its own current feedback, and there is a common
voltage feedback.
The two buck converters controlled by the FAN5094 are
interleaved, that is, they run 180° out of phase with each
other. This minimizes the RMS input ripple current, mini-
mizing the number of input capacitors required. It also
doubles the effective switching frequency, improving
transient response.
Adaptive Delay Gate Drive
The FAN5094 embodies an advanced design that ensures
minimum MOSFET transition times while eliminating
shoot-through current. It senses the state of the MOSFETs
and adjusts the gate drive adaptively to ensure that they are
never on simultaneously. When the high-side MOSFET turns
off, the voltage on its source begins to fall. When the voltage
there reaches approximately 2.5V, the low-side MOSFETs
gate drive is applied with approximately 50nsec delay. When
the low-side MOSFET turns off, the voltage at the LDRV pin
is sensed. When it drops below approximately 2V, the high-
side MOSFET’s gate drive is applied.
The FAN5094 implements “summing mode control”, which
is different from both classical voltage-mode and current-
mode control. It provides superior performance to either by
allowing a large converter bandwidth over a wide range of
output loads and external components.
The control loop of the regulator contains two main sections:
the analog control block and the digital control block. The
analog section consists of signal conditioning amplifiers
feeding into a comparator which provides the input to the
digital control block. The signal conditioning section accepts
inputs from a current sensor and a voltage sensor, with the
voltage sensor being common to both phases, and the current
sensor separate for each. The voltage sensor amplifies the
difference between the VFB signal and the reference voltage
from the DAC and presents the output to each of the two
comparators. The current control path for each phase takes
the difference between its PGND and SW pins when the
low-side MOSFET is on, reproducing the voltage across the
MOSFET and thus the input current; it presents the resulting
signal to the same input of its summing amplifier, adding its
signal to the voltage amplifier’s with a certain gain. These
two signals are thus summed together. This sum is then pre-
sented to a comparator looking at the oscillator ramp, which
provides the main PWM control signal to the digital control
block. The oscillator ramps are 180° out of phase with each
other, so that the two phases are on alternately.
Maximum Duty Cycle
In order to ensure that the current-sensing and charge-
pumping work, the FAN5094 guarantees that the low-side
MOSFET will be on a certain portion of each period. For low
frequencies, this occurs as a maximum duty cycle of approxi-
mately 90%. Thus at 500KHz, with a period of 2µsec, the
low-side will be on at least 2µsec • 10% = 200nsec. At higher
frequencies, this time might fall so low as to be ineffective.
The FAN5094 guarantees a minimum low-side on-time of
approximately 330nsec, regardless of what duty cycle this
corresponds to.
Current Sensing
The FAN5094 has two independent current sensors, one for
each phase. Current sensing is accomplished by measuring
the source-to-drain voltage of the low-side MOSFET during
its on-time. Each phase has its own power ground pin, to per-
mit the phases to be placed in different locations without
affecting measurement accuracy. For best results, it is impor-
tant to connect the PGND and SW pins for each phase as a
Kelvin trace pair directly to the source and drain, respec-
The digital control block takes the analog comparator input
to provide the appropriate pulses to the HDRV and LDRV
REV. 1.0.2 5/13/02
15
FAN5094
PRODUCT SPECIFICATION
tively, of the appropriate low-side MOSFET. Care is required
in the layout of these grounds; see the layout guidelines in
this datasheet.
BYPASS
10KΩ
10KΩ
Current Sharing
The two independent current sensors of the FAN5094 operate
with their independent current control loops to guarantee that
the two phases each deliver half of the total output current.
The only mismatch between the two phases occurs if there is
a mismatch between the RDS,on of the low-side MOSFETs.
2N2907
10KΩ
FAN5094
HI = E*-
mode on
pin25
2N2222
RDROOP
In normal usage, two FAN5094s will be operated in parallel.
By connecting the ISHR pins together, the two error amps of
the two ICs will be forced to operate at exactly the same duty
cycle, thus ensuring very close matching of the currents of
all four phases.
Figure 4. Implementing E*-mode Control
Note that the charge pump for the HIDRVs should be based
on the “B” phase of the FAN5094, since the “A” phase is off
in E*-mode.
Short Circuit Current Characteristics
Internal Voltage Reference
The FAN5094 short circuit current characteristic includes a
function that protects the DC-DC converter from damage in
the event of a short circuit. The short circuit limit is given by
the formula
The reference included in the FAN5094 is a precision band-
gap voltage reference. Its internal resistors are precisely
trimmed to provide a near zero temperature coefficient (TC).
Based on the reference is the output from an integrated 5-bit
DAC. The DAC monitors the 5 voltage identification pins,
VID0-4, and scales the reference voltage from 1.100V to
1.850V in 25mV steps.
6V
ISC = -------------------------------
10 • RDS, on
per phase.
BYPASS Reference
Precision Current Sensing
The internal logic of the FAN5094 runs on 5V. To permit the
IC to run with 12V only, it produces 5V internally with a
linear regulator, whose output is present on the BYPASS pin.
This pin should be bypassed with a 1µF capacitor for noise
suppression. The BYPASS pin should not have any external
load attached to it.
The tolerances associated with the use of MOSFET current
sensing can be circumvented by the use of a current sense
resistor.
Light Load Efficiency
At light load, the FAN5094 uses a number of techniques to
improve efficiency. Because a synchronous buck converter is
two quadrant, able to both source and sink current, during
light load the inductor current will flow away from the out-
put and towards the input during a portion of the switching
cycle. This reverse current flow is detected by the FAN5094
as a positive voltage appearing on the low-side MOSFET
during its on-time. When reverse current flow is detected, the
low-side MOSFET is turned off for the rest of the cycle, and
the current instead flows through the body diode of the
high-side MOSFET, returning the power to the source. This
technique substantially enhances light load efficiency.
Dynamic Voltage Adjustment
The FAN5094 has internal pullups on its VID lines. External
pullups should not be used. The FAN5094 can have its output
voltage dynamically adjusted to accommodate low power
modes. The designer must ensure that the transitions on the
VID lines all occur simultaneously (within less than 500nsec)
to avoid false codes generating undesired output voltages.
The Power Good flag tracks the VID codes, but has a
500µsec delay transitioning from high to low; this is long
enough to ensure that there will not be any glitches during
dynamic voltage adjustment.
E*-mode
Power Good (PWRGD)
In addition, further enhancement in efficiency can be obtained
by putting the FAN5094 into E*-mode. When the Droop pin
is pulled to the 5V BYPASS voltage, the “A” phase of the
FAN5094 is completely turned off, reducing in half the
amount of gate charge power being consumed. E*-mode can
be implemented with the circuit shown in Figure 4:
The FAN5094 Power Good function is designed in accor-
dance with the Pentium IV DC-DC converter specifications
and provides a continuous voltage monitor on the VFB pin.
The circuit compares the VFB signal to the VREF voltage
and outputs an active-low interrupt signal to the CPU should
the power supply voltage deviate more than +15%/-8% of its
nominal setpoint. The output is guaranteed open-collector
high when the power supply voltage is within +8%/-15% of
its nominal setpoint. The Power Good flag provides no
control functions to the FAN5094.
16
REV. 1.0.2 5/13/02
PRODUCT SPECIFICATION
FAN5094
with VDroop the desired droop voltage, RT the oscillator
Output Enable/Soft Start (ENABLE/SS)
resistor, Imax the load current at which the droop is desired,
n the number of phases, and RDS, on the on-state resistance of
one phase’s low-side MOSFET.
The FAN5094 will accept an open collector/TTL signal for
controlling the output voltage. The low state disables the
output voltage. When disabled, the PWRGD output is in the
low state.
Typical response time of the FAN5094 to an output voltage
change is 100nsec.
Even if an enable is not required in the circuit, this pin
should have attached a capacitor (typically 100nF) to soft-
start the switching. A softstart capacitor may be approxi-
mately chosen by the formula:
Important Note! The oscillator frequency must be selected
before selecting the droop resistor, because the value of RT
is used in the calculation of RDroop
.
t • 10µA
C = ---------------------
1 + Vout
Over-Voltage Protection
The FAN5094 constantly monitors the output voltage for
protection against over-voltage conditions. If the voltage at
the VFB pin exceeds 2.2V, an over-voltage condition is
assumed and the FAN5094 latches on the external low-side
MOSFET and latches off the high-side MOSFET. The
DC-DC converter returns to normal operation only after VCC
has been recycled.
However, C must be ≥ 100nF.
Oscillator
The FAN5094 oscillator section runs at a frequency deter-
mined by a resistor from the RT pin to ground according to
the formula
Thermal Design Considerations
50 • 109
RT(Ω) = ---------------------
f(Hz)
Because of the very large gate capacitances that the
FAN5094 may be driving, the IC may dissipate substantial
power. It is important to provide a path for the IC’s heat to be
removed, to avoid overheating. In practice, this means that
each of the pins should be connected to as large a trace as
possible. Use of the heavier weights of copper on the PCB is
also desirable. Since the MOSFETs also generate a lot of
heat, efforts should be made to thermally isolate them from
the IC.
The oscillator generates two square waves, 180° out of phase
with each other. One is used internally, the other is sent to a
second FAN5094 on the CLK pin.
The square wave generates two internal sawtooth ramps,
each at one-half the square wave frequency, and running
180° out of phase with each other. These ramps cause the
turn-on time of the two phases to be phased apart and the
four phases to be 90° apart each. The oscillator frequency of
the FAN5094 can be programmed from 400KHz to 4MHz
with each phase running at 100KHz to 1MHz, respectively.
Selection of a frequency will depend on various system
performance criteria, with higher frequency resulting in
smaller components but lower efficiency.
Over Temperature Protection
If the FAN5094 die temperature exceeds approximately
150°C, the IC shuts itself off. It remains off until the temper-
ature has dropped approximately 25°C, at which time it
resumes normal operation.
Component Selection
Programmable Active Droop™
MOSFET Selection
This application requires N-channel Enhancement Mode Field
Effect Transistors. Desired characteristics are as follows:
The FAN5094 features Programmable Active Droop™: as
the output current increases, the output voltage drops propor-
tionately an amount that can be programmed with an exter-
nal resistor. This feature is offered in order to allow
maximum headroom for transient response of the converter.
The current is sensed losslessly by measuring the voltage
across the low-side MOSFET during its on time. Consult the
section on current sensing for details. Note that this method
makes the droop dependent on the temperature and initial
tolerance of the MOSFET, and the droop must be calculated
taking account of these tolerances. Given a maximum load
current, the amount of droop can be programmed with a
resistor to ground on the droop pin, according to the formula
• Low Drain-Source On-Resistance,
• RDS,ON < 10mΩ (lower is better);
• Power package with low Thermal Resistance;
• Drain-Source voltage rating > 15V;
• Low gate charge, especially for higher frequency
operation.
For the low-side MOSFET, the on-resistance (RDS,ON) is the
primary parameter for selection. Because of the small duty
cycle of the high-side, the on-resistance determines the
power dissipation in the low-side MOSFET and therefore
significantly affects the efficiency of the DC-DC converter.
For high current applications, it may be necessary to use two
MOSFETs in parallel for the low-side for each phase.
2 • n • VDroop • RT
RDroop(Ω) = --------------------------------------------------
Imax • RDS, on
REV. 1.0.2 5/13/02
17
FAN5094
PRODUCT SPECIFICATION
For the high-side MOSFET, the gate charge is as important
as the on-resistance, especially with a 12V input and with
higher switching frequencies. This is because the speed of
the transition greatly affects the power dissipation. It may be
a good trade-off to select a MOSFET with a somewhat
higher RDS,on, if by so doing a much smaller gate charge is
available. For high current applications, it may be necessary
to use two MOSFETs in parallel for the high-side for each
phase.
Inductor Selection
Choosing the value of the inductor is a tradeoff between
allowable ripple voltage and required transient response. A
smaller inductor produces greater ripple while producing
better transient response. In any case, the minimum induc-
tance is determined by the allowable ripple. The first order
equation (close approximation) for minimum inductance for
a two-phase converter is:
V
in – 2 • Vout Vout
ESR
At the FAN5094’s highest operating frequencies, it may be
necessary to limit the total gate charge of both the high-side
and low-side MOSFETs together, to avert excess power dis-
sipation in the IC.
---------------------------------- ----------- -----------------
Lmin
=
•
•
f
Vin Vripple
where:
Vin = Input Power Supply
Vout = Output Voltage
f = DC/DC converter switching frequency
For details and a spreadsheet on MOSFET selection, refer to
Applications Bulletin AB-8.
ESR = Equivalent series resistance of all output capacitors in
parallel
Gate Resistors
Vripple = Maximum peak to peak output ripple voltage
budget.
Use of a gate resistor on every MOSFET is mandatory. The
gate resistor prevents high-frequency oscillations caused by
the trace inductance ringing with the MOSFET gate
capacitance. The gate resistors should be located physically
as close to the MOSFET gate as possible.
One other limitation on the minimum size of the inductor is
caused by the current feedback loop stability criterion. The
inductor must be greater than:
The gate resistor also limits the power dissipation inside the
IC, which could otherwise be a limiting factor on the switch-
ing frequency. It may thus carry significant power, especially
at higher frequencies. As an example, consider the gate
resistors used for the low-side MOSFETs (Q2 and Q4) in
Figure 1. The FDB7045L has a maximum gate charge of
70nC at 5V, and an input capacitance of 5.4nF. The total
energy used in powering the gate during one cycle is the
energy needed to get it up to 5V, plus the energy to get it up
to 12V:
L ≥ 3 • 10–10 • RDS, on • RDroop • (Vin – 2Vo)
where L is the inductance in Henries, RDS,on is the on-state
resistance of one phase’s low-side MOSFET, RDroop is the
value of the droop resistor in Ohms, Vin is either 5V or 12V,
and Vo is the output voltage. For most applications, this for-
mula will not present any limitation on the selection of the
inductor value.
A typical value for the inductor is 1.3µH at an oscillator
frequency of 1.2MHz (300KHz each phase) and 220nH at an
oscillator frequency of 4MHz (1MHz each phase). For other
frequencies, use the interpolating formula
2
1
2
1
2
2
--
E = QV + C • ∆V = 70nC • 5V + --5.4nF • (12V – 5V)
= 482nJ
1.86 × 106
L(nH) ≈ -------------------------- – 240
f(KHz)
This power is dissipated every cycle, and is divided between
the internal resistance of the FAN5094 gate driver and the
gate resistor. Thus,
E • f • Rgate
Schottky Diode Selection
•
PRgate = ------------------------------------------------ = 482nJ • 300KHz
(Rgate + Rinternal
4.7Ω
)
The application circuits of Figures 1-2 show a Schottky
diode, D1 (D2 respectively), one in each phase. They are
used as free-wheeling diodes to ensure that the body-diodes
in the low-side MOSFETs do not conduct when the upper
MOSFET is turning off and the lower MOSFETs are turning
on. It is undesirable for this diode to conduct because its high
forward voltage drop and long reverse recovery time
-------------------------------- = 19mW
4.7Ω + 1.0Ω
and each gate resistor thus requires a 1/4W resistor to ensure
worst case power dissipation.
degrades efficiency, and so the Schottky provides a shunt
path for the current. Since this time duration is extremely
short, being minimized by the adaptive gate delay, the selec-
tion criterion for the diode is that the forward voltage of the
Schottky at the output current should be less than the forward
The same calculation may be performed for the high-side
MOSFETs, bearing in mind that their gate voltage swings
only the charge pump voltage of 5V.
18
REV. 1.0.2 5/13/02
PRODUCT SPECIFICATION
FAN5094
voltage of the MOSFET’s body diode. Power capability is
not a criterion for this device, as its dissipation is very small.
It is necessary to have some low ESR capacitors at the input
to the converter. These capacitors deliver current when the
high side MOSFET switches on. Because of the interleaving,
the number of such capacitors required is greatly reduced
from that required for a single-phase buck converter. Figure
5 shows 3 x 1000µF, but the exact number required will vary
with the output voltage and current, according to the formula
Output Filter Capacitors
The output bulk capacitors of a converter help determine its
output ripple voltage and its transient response. It has
already been seen in the section on selecting an inductor that
the ESR helps set the minimum inductance. For most con-
verters, the number of capacitors required is determined by
the transient response and the output ripple voltage, and
these are determined by the ESR and not the capacitance
value. That is, in order to achieve the necessary ESR to meet
the transient and ripple requirements, the capacitance value
required is already very large.
Iout
Irms
=
4DC – 16DC2
--------
4
for the four phase FAN5094, where DC is the duty cycle,
DC = Vout / Vin. Capacitor ripple current rating is a function
of temperature, and so the manufacturer should be contacted
to find out the ripple current rating at the expected opera-
tional temperature. For details on the design of an input filter,
refer to Applications Bulletin AB-16.
The most commonly used choice for output bulk capacitors
is aluminum electrolytics, because of their low cost and low
ESR. The only type of aluminum capacitor used should be
those that have an ESR rated at 100kHz. Consult Application
Bulletin AB-14 for detailed information on output capacitor
selection.
1.3µH
Vin
+12V
1000µF, 16V
Electrolytic
For higher frequency applications, particularly those running
the FAN5094 oscillator at >1MHz, Oscon or ceramic capaci-
tors may be considered. They have much smaller ESR than
comparable electrolytics, but also much smaller capacitance.
Figure 5. Input Filter
Design Considerations and Component
Selection
Additional information on design and component selection
may be found in Fairchild’s Application Note 59.
The output capacitance should also include a number of
small value ceramic capacitors placed as close as possible to
the processor; 0.1µF and 0.01µF are recommended values.
Input Filter
The DC-DC converter design may include an input inductor
between the system main supply and the converter input as
shown in Figure 5. This inductor serves to isolate the main
supply from the noise in the switching portion of the DC-DC
converter, and to limit the inrush current into the input capac-
itors during power up. A value of 1.3µH is recommended.
REV. 1.0.2 5/13/02
19
FAN5094
PRODUCT SPECIFICATION
PC Motherboard Sample Layout and Gerber File
PCB Layout Guidelines
A reference design for motherboard implementation of the
FAN5094 along with the PCAD layout Gerber file and silk
screen can be obtained through your local Fairchild represen-
tative.
• Placement of the MOSFETs relative to the FAN5094 is
critical. Place the MOSFETs such that the trace length of
the HIDRV and LODRV pins of the FAN5094 to the FET
gates is minimized. A long lead length on these pins will
cause high amounts of ringing due to the inductance of the
trace and the gate capacitance of the FET. This noise
radiates throughout the board, and, because it is switching
at such a high voltage and frequency, it is very difficult to
suppress.
FAN5094 Evaluation Board
Fairchild provides an evaluation board to verify the system
level performance of the FAN5094. It serves as a guide to
performance expectations when using the supplied external
components and PCB layout. Please contact your local
Fairchild representative for an evaluation board.
• In general, all of the noisy switching lines should be kept
away from the quiet analog section of the FAN5094. That
is, traces that connect to pins 9-20 (LDRV, HDRV, GND
and BOOT) should be kept far away from the traces that
connect to pins 1 through 8, and pins 21-28.
Additional Information
For additional information contact your local Fairchild
representative.
• Place the 0.1µF decoupling capacitors as close to the
FAN5094 pins as possible. Extra lead length on these
reduces their ability to suppress noise.
• Each power and ground pin should have its own via to the
appropriate plane. This helps provide isolation between
pins.
• Place the MOSFETs, inductor, and Schottky of a given
phase as close together as possible for the same reasons as
in the first bullet above. Place the input bulk capacitors as
close to the drains of the high side MOSFETs as possible.
In addition, placement of a 0.1µF decoupling cap right on
the drain of each high side MOSFET helps to suppress
some of the high frequency switching noise on the input
of the DC-DC converter.
• Place the output bulk capacitors as close to the CPU as
possible to optimize their ability to supply instantaneous
current to the load in the event of a current transient.
Additional space between the output capacitors and the
CPU will allow the parasitic resistance of the board traces
to degrade the DC-DC converter’s performance under
severe load transient conditions, causing higher voltage
deviation. For more detailed information regarding
capacitor placement, refer to Application Bulletin AB-5.
• A PC Board Layout Checklist is available from Fairchild
Applications. Ask for Application Bulletin AB-11.
20
REV. 1.0.2 5/13/02
PRODUCT SPECIFICATION
FAN5094
Mechanical Dimension
28 Lead TSSOP
Notes:
Inches
Millimeters
Symbol
Notes
1. Dimensioning and tolerancing per ANSI Y14.5M-1982.
Min.
Max.
Min.
Max.
2. "D" and "E" do not include mold flash. Mold flash or
protrusions shall not exceed .010 inch (0.25mm).
A
—
.047
.006
.012
.013
.386
.180
—
1.20
0.15
0.30
0.20
9.80
4.50
A1
B
.002
.007
.008
.378
.172
0.05
0.19
0.09
9.60
4.30
3. "L" is the length of terminal for soldering to a substrate.
4. Terminal numbers are shown for reference only.
5. Symbol "N" is the maximum number of terminals.
C
D
E
2
2
e
.026 BSC
.252 BSC
.018 .030
0.65 BSC
6.40 BSC
0.45 0.75
H
L
3
5
N
α
28
28
0°
8°
0°
8°
ccc
—
.004
—
0.10
D
E
H
C
A1
A
α
SEATING
PLANE
– C –
L
B
LEAD COPLANARITY
ccc C
e
REV. 1.0.2 5/13/02
21
FAN5094
PRODUCT SPECIFICATION
Ordering Information
Product Number
Package
FAN5094MTC
28 pin TSSOP
Tape & Reel
FAN5094MTCX
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ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME
ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
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OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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