FAN5236QSCX [FAIRCHILD]
Dual Mobile-Friendly DDR / Dual-output PWM Controller; 双移动友好DDR /双输出PWM控制器
| 型号： | FAN5236QSCX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Dual Mobile-Friendly DDR / Dual-output PWM Controller |
| 文件： | 总20页 (文件大小：199K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
www.fairchildsemi.com
FAN5236
Dual Mobile-Friendly DDR / Dual-output PWM Controller
Features
General Description
• Highly flexible dual synchronous switching PWM
controller includes modes for:
The FAN5236 PWM controller provides high efficiency and
regulation for two output voltages adjustable in the range
from 0.9V to 5.5V that are required to power I/O, chip-sets,
and memory banks in high-performance notebook comput-
ers, PDAs and Internet appliances. Synchronous rectification
and hysteretic operation at light loads contribute to a high
efficiency over a wide range of loads. The hysteretic mode of
operation can be disabled separately on each PWM converter
if PWM mode is desired for all load levels. Efficiency is even
further enhanced by using MOSFET’s RDS(ON) as a current
sense component.
– DDR mode with in-phase operation for reduced
channel interference
– 90˚ phase shifted two-stage DDR Mode for reduced
input ripple
– Dual Independent regulators 180° phase shifted
• Complete DDR Memory power solution
– VTT Tracks VDDQ/2
– VDDQ/2 Buffered Reference Output
• Lossless current sensing on low-side MOSFET or
precision over-current using sense resistor
• VCC Under-voltage Lockout
Feed-forward ramp modulation, average current mode con-
trol scheme, and internal feedback compensation provide
fast response to load transients. Out-of-phase operation with
180 degree phase shift reduces input current ripple. The con-
troller can be transformed into a complete DDR memory
power supply solution by activating a designated pin. In
DDR mode of operation one of the channels tracks the out-
put voltage of another channel and provides output current
sink and source capability — features essential for proper
powering of DDR chips. The buffered reference voltage
required by this type of memory is also provided. The
FAN5236 monitors these outputs and generates separate
PGx (power good) signals when the soft-start is completed
and the output is within 10ꢀ of its set point. A built-in
over-voltage protection prevents the output voltage from
going above 120ꢀ of the set point. Normal operation is auto-
matically restored when the over-voltage conditions go
away. Under-voltage protection latches the chip off when
either output drops below 75ꢀ of its set value after the soft-
start sequence for this output is completed. An adjustable
over-current function monitors the output current by sensing
the voltage drop across the lower MOSFET. If precision cur-
rent-sensing is required, an external current-sense resistor
may optionally be used.
• Converters can operate from +5V or 3.3V or Battery
power input (5 to 24V)
• Excellent dynamic response with Voltage Feed-Forward
and Average Current Mode control
• Power-Good Signal
• Also supports DDR-II and HSTL
• Light load Hysteretic mode maximizes efficiency
• QSOP28, TSSOP28
Applications
• DDR VDDQ and VTT voltage generation
• Mobile PC dual regulator
• Server DDR power
• Hand-Held PC power
REV. 1.1.7 4/4/03
PRODUCT SPECIFICATION
FAN5236
Generic Block Diagrams
VIN (BATTERY)
= 5 to 24V
VCC
+5
FAN5236
Q1
VOUT1
= 2.5V
ILIM1
L OUT1
PWM 1
COUT1
Q2
DDR
Q3
L OUT2
VOUT2
= 1.8V
ILIM2/
REF2
PWM 2
COUT2
Q4
Figure 1. Dual output regulator
VIN (BATTERY)
= 5 to 24V
VCC
+5
FAN5236
Q1
ILIM1
VDDQ
= 2.5V
L OUT1
PWM 1
COUT1
Q2
R
R
DDR
+5
Q3
VTT =
VDDQ/2
L OUT2
PG2/REF
1.25V
COUT2
Q4
PWM 2
ILIM2/REF2
Figure 2. Complete DDR Memory Power Supply
2
REV. 1.1.7 4/4/03
FAN5236
PRODUCT SPECIFICATION
Pin Configurations
AGND
LDRV1
PGND1
SW1
VCC
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
LDRV2
PGND2
SW2
2
3
4
HDRV1
BOOT1
ISNS1
EN1
HDRV2
BOOT2
ISNS2
5
6
7
FAN5236
EN2
8
FPWM1
VSEN1
ILIM1
FPWM2
VSEN2
ILIM2/REF2
SS2
9
10
11
12
13
14
SS1
DDR
PG2/REF2OUT
PG1
VIN
QSOP-28 or TSSOP-28
= 90°C/W
θ
JA
Pin Definitions
Pin
Number Pin Name Pin Function Description
1
AGND
Analog Ground. This is the signal ground reference for the IC. All voltage levels are
measured with respect to this pin.
2
27
LDRV1
LDRV2
Low-Side Drive. The low-side (lower) MOSFET driver output. Connect to gate of low-side
MOSFET.
3
26
PGND1
PGND2
Power Ground. The return for the low-side MOSFET driver. Connect to source of low-
side MOSFET.
4
25
SW1
SW2
Switching node. Return for the high-side MOSFET driver and a current sense input.
Connect to source of high-side MOSFET and low-side MOSFET drain.
5
HDRV1
High-Side Drive. High-side (upper) MOSFET driver output. Connect to gate of high-side
24
MOSFET.
6
23
BOOT1
BOOT2
BOOT. Positive supply for the upper MOSFET driver. Connect as shown in Figure 3.
7
22
ISNS1
ISNS2
Current Sense input. Monitors the voltage drop across the lower MOSFET or external
sense resistor for current feedback.
8
21
EN1
EN2
Enable. Enables operation when pulled to logic high. Toggling EN will also reset the
regulator after a latched fault condition. These are CMOS inputs whose state is
indeterminate if left open.
9
20
FPWM1
FPWM2
Forced PWM mode. When logic low, inhibits the regulator from entering hysteretic mode.
Otherwise tie to VOUT. The regulator uses VOUT on this pin to ensure a smooth
transition from Hysteretic mode to PWM mode. When VOUT is expected to exceed VCC,
tie to VCC.
10
19
VSEN1
VSEN2
Output Voltage Sense. The feedback from the outputs. Used for regulation as well as
PG, under-voltage and over-voltage protection and monitoring.
11
ILIM1
Current Limit 1. A resistor from this pin to GND sets the current limit.
12
17
SS1
SS2
Soft Start. A capacitor from this pin to GND programs the slew rate of the converter
during initialization. During initialization, this pin is charged with a 5µA current source.
13
DDR
DDR Mode Control. High = DDR mode. Low = 2 separate regulators operating 180° out
of phase.
REV. 1.1.7 4/4/03
3
PRODUCT SPECIFICATION
FAN5236
Pin Definitions (continued)
14
VIN
Input Voltage. Normally connected to battery, providing voltage feed-forward to set the
amplitude of the internal oscillator ramp. When using the IC for 2-step conversion from 5V
input, connect through 100K to ground, which will set the appropriate ramp gain and
synchronize the channels 90˚ out of phase.
15
16
PG1
Power Good Flag. An open-drain output that will pull LOW when VSEN is outside of a
10ꢀ range of the 0.9V reference.
PG2 /
Power Good 2. When not in DDR Mode: Open-drain output that pulls LOW when the
REF2OUT VOUT is out of regulation or in a fault condition
Reference Out 2. When in DDR Mode, provides a buffered output of REF2. Typically
used as the VDDQ/2 reference.
18
28
ILIM2 /
REF2
Current Limit 2. When not in DDR Mode, A resistor from this pin to GND sets the current
limit.
Reference for reg #2 when in DDR Mode. Typically set to VOUT1 / 2.
VCC
VCC. This pin powers the chip as well as the LDRV buffers. The IC starts to operate when
voltage on this pin exceeds 4.6V (UVLO rising) and shuts down when it drops below 4.3V
(UVLO falling).
Absolute Maximum Ratings
Absolute maximum ratings are the values beyond which the device may be damaged or have its useful life
impaired. Functional operation under these conditions is not implied.
Parameter
Min.
Typ.
Max.
6.5
Units
V
VCC Supply Voltage:
VIN
27
V
BOOT, SW, ISNS, HDRV
BOOTx to SWx
33
V
6.5
V
All Other Pins
–0.3
–40
–65
VCC+0.3
150
V
Junction Temperature (TJ )
Storage Temperature
Lead Soldering Temperature, 10 seconds
°C
°C
°C
150
300
Recommended Operating Conditions
Parameter
Conditions
Min.
Typ.
Max.
5.25
24
Units
V
Supply Voltage VCC
Supply Voltage VIN
Ambient Temperature (TA )
4.75
5
V
Note 1
–10
85
°C
Note 1: Industrial temperature range (–40 to + 85°C) may be special ordered from Fairchild. Please contact your authorized Fairchild
representative for more information.
4
REV. 1.1.7 4/4/03
FAN5236
PRODUCT SPECIFICATION
Electrical Specifications Recommended operating conditions, unless otherwise noted.
Parameter
Conditions
Min.
Typ.
Max.
Units
Power Supplies
VCC Current
LDRV, HDRV Open, VSEN forced
above regulation point
2.2
3.0
mA
Shut-down (EN=0)
VIN = 24V
30
30
µA
µA
µA
µA
V
VIN Current – Sinking
VIN Current – Sourcing
VIN Current – Shut-down
UVLO Threshold
10
VIN = 0V
–15
–30
1
Rising VCC
Falling
4.3
4.1
4.55
4.25
300
4.75
4.45
V
UVLO Hysteresis
Oscillator
mV
Frequency
255
300
2
345
KHz
V
Ramp Amplitude, pk–pk
Ramp Amplitude, pk–pk
Ramp Offset
VIN = 16V
VIN = 5V
1.25
0.5
125
250
V
V
Ramp / VIN Gain
Ramp / VIN Gain
Reference and Soft Start
Internal Reference Voltage
VIN ≥ 3V
mV/V
mV/V
1V < VIN < 3V
0.891
0.9
5
0.909
V
µA
V
Soft Start current (ISS
)
at start-up
Soft Start Complete Threshold
PWM Converters
1.5
Load Regulation
IOUTX from 0 to 5A, VIN from 5 to 24V
-2
50
+2
120
65
ꢀ
nA
KΩ
ꢀ
VSEN Bias Current
80
55
VOUT pin input impedance
Under-voltage Shutdown
Over-voltage threshold
ISNS Over-Current threshold
Output Drivers
45
as ꢀ of set point. 2µS noise filter
as ꢀ of set point. 2µS noise filter
RILIM= 68.5KΩ see Figure 11.
70
75
80
115
112
120
140
125
168
ꢀ
µA
HDRV Output Resistance
Sourcing
Sinking
12
2.4
12
15
4
Ω
Ω
Ω
Ω
LDRV Output Resistance
Sourcing
Sinking
15
2
1.2
PG (Power Good Output) and Control pins
Lower Threshold
Upper Threshold
PG Output Low
as ꢀ of set point, 2µS noise filter
–86
108
–94
116
0.5
1
ꢀ
ꢀ
V
as ꢀ of set point, 2µS noise filter
IPG = 4mA
Leakage Current
PG2/REF2OUT Voltage
VPULLUP = 5V
µA
DDR = 1, 0 mA < IREF2OUT ≤10mA
99
1.01
ꢀ
VREF2
REV. 1.1.7 4/4/03
5
PRODUCT SPECIFICATION
FAN5236
Electrical Specifications Recommended operating conditions, unless otherwise noted. (continued)
Parameter
Conditions
Min.
Typ.
Max.
Units
DDR, EN Inputs
Input High
2
V
V
Input Low
0.8
0.1
FPWM Inputs
FPWM Low
FPWM High
V
V
FPWM connected to output
0.9
5V
VDD
CBOOT
BOOT
EN
VIN
Q1
POR/UVLO
FPWM/VOUT
FPWM
DDR
HDRV
SW
HYST
SS
HYST
VOUT
COUT
OVP
L
ADAPTIVE
GATE
Q2
OUT
VDD
CONTROLLOGIC
DDR
VIN
LDRV
PGND
RAMP
OSC
CLK
Q
R
PWM
S/H
S
PWM/HYST
PWM
RAMP
RSENSE
ILIM det.
MODE
ISNS
VSEN
CURRENT PROCESSING
DUTY
CYCLE
CLAMP
EA
IOUT
Σ
FPWM/VOUT
SS
ILIM
VREF
PGOOD
REF2
Reference and
Soft Start
PWM/HYST
DDR
Figure 3. IC Block Diagram
6
REV. 1.1.7 4/4/03
FAN5236
PRODUCT SPECIFICATION
Typical Applications
VIN (BATTERY)
= 5 to 24V
VIN
C1
C9
14
D1
VCC
BOOT1
Q1A
28
6
+5
+5
C4
C5
HDRV1
VDDQ
= 2.5V
5
4
R3
L1
ILIM1
EN1
SS1
11
8
SW1
C6A C6B
Q1B
PWM 1
R5
LDRV1
2
12
C2
R7
PGND2
ISNS1
+5
3
7
R4
FPWM1 (VOUT1)
VSEN1
9
PG1
15
R1
10
DDR
EN2
SS2
+5
13
21
17
BOOT2
Q2A
23
R6
D2
+5
HDRV2
SW2
C7
C3
24
25
VTT =
VDDQ/2
L2
R2
1.25V@10mA
PG2/REF
Q2B
C8A
16
1
PWM 2
LDRV2
27
AGND
PGND2
ISNS2
26
22
R8
C8B
FPWM2
VSEN2
20
19
18
ILIM2/REF2
Figure 4. DDR Regulator Application
Table 1. DDR Regulator BOM
Description
Qty Ref.
Vendor
AVX
Any
Part Number
Capacitor 68µf, Tantalum, 25V, ESR 150mΩ
Capacitor 10nf, Ceramic
1
2
1
2
2
1
2
3
1
2
2
1
2
2
1
1
1
1
C1
TPSV686*025#0150
C2, C3
C4
Capacitor 68µf, Tantalum, 6V, ESR 1.8Ω
Capacitor 150nF, Ceramic
Capacitor 180µf, Specialty Polymer 4V, ESR 15mΩ
Capacitor 1000µf, Specialty Polymer 4V, ESR 10mΩ
Capacitor 0.1µF, Ceramic
18.2KΩ, 1% Resistor
AVX
Any
TAJB686*006
C5, C7
C6A, C6B Panasonic EEFUE0G181R
C8
Kemet
Any
T510E108(1)004AS4115
C9
R1, R2
R6
Any
1.82KΩ, 1% Resistor
Any
56.2KΩ, 1% Resistor
R3
Any
10KΩ, 5% Resistor
R4
Any
3.24KΩ, 1% Resistor
R5
Any
1.5KΩ, 1% Resistor
R7, R8
D1, D2
L1,
Any
Schottky Diode 30V
Fairchild
BAT54
Inductor 6.4µH, 6A, 8.64mΩ
Inductor 0.8µH, 6A, 2.24mΩ
Dual MOSFET with Schottky
DDR Controller
Panasonic ETQ-P6F6R4HFA
Panasonic ETQ-P6F0R8LFA
L2
Q1, Q2
U1
Fairchild
Fairchild
FDS6986S (note 1)
FAN5236
Note 1: Suitable for typical notebook computer application of 4A continuous, 6A peak for VDDQ. If continuous operation above
6A is required use single SO-8 packages for Q1A (FDS6612A) and Q1B (FDS6690S) respectively. Using FDS6690S,
change R7 to 1200Ω. Refer to Power MOSFET Selection, page 15 for more information.
REV. 1.1.7 4/4/03
7
PRODUCT SPECIFICATION
FAN5236
Typical Applications (continued)
VIN (BATTERY)
= 5 to 24V
VIN
C9
C1
14
D1
L1
VCC
BOOT1
Q1A
28
11
6
+5
+5
C4
C5
HDRV1
5
4
R2
ILIM1
2.5V@6A
C6
SW1
EN1
SS1
Q1B
LDRV1
8
PWM 1
2
12
R6
C2
PGND2
ISNS1
+5
3
7
R4
R3
FPWM1 (VOUT1)
VSEN1
9
PG1
DDR
15
13
10
VIN
D2
BOOT2
Q2A
23
R5
+5
EN2
21
HDRV2
SW2
C7
24
25
PG2
SS2
L2
16
17
1.8V@6A
Q2B
C8
PWM 2
LDRV2
C3
27
R7
AGND
PGND2
ISNS2
R8
1
26
22
R9
R1
FPWM2
VSEN2
ILIM2
20
19
18
Figure 5. Dual Regulator Application
Qty Ref.
Table 2. Dual Regulator BOM
Item Description
Vendor
AVX
Any
Part Number
1
Capacitor 68µf, Tantalum, 25V, ESR 95mΩ
Capacitor 10nf, Ceramic
Capacitor 68µf, Tantalum, 6V, ESR 1.8Ω
Capacitor 150nF, Ceramic
Capacitor 330µf, Poscap, 4V, ESR 40mΩ
Capacitor 0.1µF, Ceramic
56.2KΩ, 1% Resistor
1
2
1
2
2
2
2
2
1
3
2
2
1
1
1
C1
TPSV686*025#095
TAJB686*006
4TPB330ML
2
C2, C3
C4
3
AVX
Any
4
C5, C7
C6, C8
C9
5
Sanyo
Any
5
11
12
13
14
15
27
28
29
30
R1, R2
R3
Any
10KΩ, 5% Resistor
Any
3.24KΩ, 1% Resistor
R4
Any
1.82KΩ, 1% Resistor
R5, R8, R9 Any
1.5KΩ, 1% Resistor
R6, R7
D1, D2
L1, L2
Q1
Any
Schottky Diode 30V
Fairchild
BAT54
Inductor 6.4µH, 6A, 8.64mΩ
Dual MOSFET with Schottky
DDR Controller
Panasonic ETQ-P6F6R4HFA
Fairchild
Fairchild
FDS6986S (note 1)
FAN5236
U1
Note 1: If currents above 4A continuous required, use single SO-8 packages for Q1A/Q2A (FDS6612A) and Q1B/Q2B
(FDS6690S) respectively. Using FDS6690S, change R6/R7 as required. Refer to Power MOSFET Selection, page 15
for more information.
8
REV. 1.1.7 4/4/03
FAN5236
PRODUCT SPECIFICATION
When used as a dual converter (as in Figure 5), out-of-phase
operation with 180 degree phase shift reduces input current
ripple.
Circuit Description
Overview
The FAN5236 is a multi-mode, dual channel PWM control-
ler intended for graphic chipset, SDRAM, DDR DRAM or
other low voltage power applications in modern notebook,
desktop, and sub-notebook PCs. The IC integrates a control
circuitry for two synchronous buck converters. The output
voltage of each controller can be set in the range of 0.9V to
5.5V by an external resistor divider.
For the “2-step” conversion (where the VTT is converted
from VDDQ as in Figure 4) used in DDR mode, the duty
cycle of the second converter is nominally 50ꢀ and the opti-
mal phasing depends on VIN. The objective is to keep noise
generated from the switching transition in one converter
from influencing the "decision" to switch in the other con-
verter.
The two synchronous buck converters can operate from
either an unregulated DC source (such as a notebook battery)
with voltage ranging from 5.0V to 24V, or from a regulated
system rail of 3.3V to 5V. In either mode of operation the IC
is biased from a +5V source. The PWM modulators use an
average current mode control with input voltage feed-for-
ward for simplified feedback loop compensation and
improved line regulation. Both PWM controllers have inte-
grated feedback loop compensation that dramatically
reduces the number of external components.
When VIN is from the battery, it’s typically higher than 7.5V.
As shown in Figure 6, 180° operation is undesirable since
the turn-on of the VDDQ converter occurs very near the
decision point of the VTT converter.
CLK
VDDQ
VTT
Depending on the load level, the converters can operate
either in fixed frequency PWM mode or in a hysteretic mode.
Switch-over from PWM to hysteretic mode improves the
converters’ efficiency at light loads and prolongs battery run
time. In hysteretic mode, comparators are synchronized to
the main clock that allows seamless transition between the
operational modes and reduced channel-to-channel interac-
tion. The hysteretic mode of operation can be inhibited inde-
pendently for each channel if variable frequency operation is
not desired.
Figure 6. Noise-susceptible 180° phasing for DDR1
In-phase operation is optimal to reduce inter-converter inter-
ference when VIN is higher than 5V, (when VIN is from a
battery), as can be seen in Figure 7. Since the duty cycle
of PWM1 (generating VDDQ) is short, it’s switching point
occurs far away from the decision point for the VTT
regulator, whose duty cycle is nominally 50ꢀ.
The FAN5236 can be configured to operate as a complete
DDR solution. When the DDR pin is set high, the second
channel can provide the capability to track the output voltage
of the first channel. The PWM2 converter is prevented from
going into hysteretic mode if the DDR pin is set high. In
DDR mode, a buffered reference voltage (buffered voltage of
the REF2 pin), required by DDR memory chips, is provided
by the PG2 pin.
CLK
VDDQ
VTT
Figure 7. Optimal In-Phase operation for DDR1
Converter Modes and Synchronization
When VIN ≈ 5V, 180° phase shifted operation can be
rejected for the same reasons demonstrated Figure 6.
In-phase operation with VIN ≈ 5V is even worse, since the
switch point of either converter occurs near the switch point
of the other converter as seen in Figure 8. In this case, as
VIN is a little higher than 5V it will tend to cause early
termination of the VTT pulse width. Conversely, VTT’s
switch point can cause early termination of the VDDQ pulse
width when VIN is slightly lower than 5V.
Table 3. Converter modes and Synchronization
DDR
Pin
PWM 2 w.r.t.
PWM1
Mode VIN
VIN Pin
DDR1 Battery VIN
HIGH IN PHASE
DDR2 +5V
DUAL ANY
R to GND HIGH + 90°
VIN
LOW + 180°
REV. 1.1.7 4/4/03
9
PRODUCT SPECIFICATION
FAN5236
When SS reaches 1.5V, the Power Good outputs are enabled
and hysteretic mode is allowed. The converter is forced into
PWM mode during soft start.
CLK
VDDQ
Operation Mode Control
VTT
The mode-control circuit changes the converter’s mode of
operation from PWM to Hysteretic and visa versa, based on
the voltage polarity of the SW node when the lower MOS-
FET is conducting and just before the upper MOSFET turns
on. For continuous inductor current, the SW node is negative
when the lower MOSFET is conducting and the converters
operate in fixed-frequency PWM mode as shown in Figure
10. This mode of operation achieves high efficiency at nomi-
nal load. When the load current decreases to the point where
the inductor current flows through the lower MOSFET in the
‘reverse’ direction, the SW node becomes positive, and the
mode is changed to hysteretic, which achieves higher effi-
ciency at low currents by decreasing the effective switching
frequency.
Figure 8. Noise-susceptible In-Phase operation for DDR2
These problems are nicely solved by delaying the 2nd con-
verter’s clock by 90° as shown in Figure 9. In this way, all
switching transitions in one converter take place far away
from the decision points of the other converter.
CLK
VDDQ
VTT
To prevent accidental mode change or "mode chatter" the
transition from PWM to Hysteretic mode occurs when the
SW node is positive for eight consecutive clock cycles (see
Figure 10). The polarity of the SW node is sampled at the
end of the lower MOSFET’s conduction time. At the transi-
tion between PWM and hysteretic mode both the upper and
lower MOSFETs are turned off. The phase node will ‘ring’
based on the output inductor and the parasitic capacitance on
the phase node and settle out at the value of the output volt-
age.
Figure 9. Optimal 90° phasing for DDR2
Initialization and Soft Start
Assuming EN is high, FAN5236 is initialized when VCC
exceeds the rising UVLO threshold. Should VCC drop
below the UVLO threshold, an internal Power-On Reset
function disables the chip.
The voltage at the positive input of the error amplifier is lim-
ited by the voltage at the SS pin which is charged with a 5µA
current source. Once CSS has charged to VREF (0.9V) the
output voltage will be in regulation. The time it takes SS to
reach 0.9V is:
The boundary value of inductor current, where current
becomes discontinuous, can be estimated by the following
expression.
(VIN – VOUT)VOUT
(2)
ILOAD(DIS) = --------------------------------------------------
2FSWLOUTVIN
0.9 × CSS
(1)
T0.9 = -----------------------
5
where T0.9 is in seconds if CSS is in µF.
VCORE
PWM Mode
1
Hysteretic Mode
I L
0
2
3
4
5
6
7
8
VCORE
Hysteretic Mode
3
PWM Mode
I L
0
1
2
4
5
6
7
8
Figure 10. Transitioning between PWM and Hysteretic Mode
10
REV. 1.1.7 4/4/03
FAN5236
PRODUCT SPECIFICATION
The switching frequency is primarily a function of:
Hysteretic Mode
Conversely, the transition from Hysteretic mode to PWM
mode occurs when the SW node is negative for 8 consecutive
cycles.
1. Spread between the two hysteretic thresholds
2. ILOAD
3. Output Inductor and Capacitor ESR
A sudden increase in the output current will also cause a
change from hysteretic to PWM mode. This load increase
causes an instantaneous decrease in the output voltage due to
the voltage drop on the output capacitor ESR. If the load
causes the output voltage (as presented at VSNS) to drop
below the hysteretic regulation level (20mV below VREF),
the mode is changed to PWM on the next clock cycle.
A transition back to PWM (Continuous Conduction Mode or
CCM) mode occurs when the inductor current rises suffi-
ciently to stay positive for 8 consecutive cycles. This occurs
when:
∆VHYSTERESIS
(3)
ILOAD(CCM) = ---------------------------------------
2 ESR
In hysteretic mode, the PWM comparator and the error
amplifier that provide control in PWM mode are inhibited
and the hysteretic comparator is activated. In hysteretic
mode the low side MOSFET is operated as a synchronous
rectifier, where the voltage across ( VDS(ON) ) it is monitored,
and it is switched off when VDS(ON) goes positive (current
flowing back from the load) allowing the diode to block
reverse conduction.
where ∆VHYSTERESIS = 15mV and ESR is the equivalent
series resistance of COUT
.
Because of the different control mechanisms, the value of the
load current where transition into CCM operation takes place
is typically higher compared to the load level at which transi-
tion into hysteretic mode occurs. Hysteretic mode can be
disabled by setting the FPWM pin low.
The hysteretic comparator initiates a PFM signal to turn on
HDRV at the rising edge of the next oscillator clock, when
the output voltage (at VSNS) falls below the lower threshold
(10mV below VREF) and terminates the PFM signal when
VSNS rises over the higher threshold (5mV above VREF).
0.17pf
S/H
17pf
1.5M
300K
4.14K
V to I
VSEN
RSENSE
ISNS
in +
in ñ
I1A =
ISNS
I1B =
ISNS
9
TO PWM COMP
LDRV
PGND
Reference and
Soft Start
RILIM
SS
ILIM
CSS
0.9V
2.5V
4 * ILIM
3
I2 =
ILIM det.
ILIM mirror
Figure 11. Current Limit / Summing Circuits
REV. 1.1.7 4/4/03
11
PRODUCT SPECIFICATION
FAN5236
Current Processing Section
The following discussion refers to Figure 11.
Q2
LDRV
ISNS
The current through RSENSE resistor (ISNS) is sampled
shortly after Q2 is turned on. That current is held, and
summed with the output of the error amplifier. This effec-
tively creates a current mode control loop. The resistor con-
nected to ISNSx pin (RSENSE) sets the gain in the current
feedback loop. For stable operation, the voltage induced by
the current feedback at the PWM comparator input should be
set to 30ꢀ of the ramp amplitude at maximum load currrent
and line voltage. The following expression estimates the
recommended value of RSENSE as a function of the maxi-
mum load current (ILOAD(MAX)) and the value of the
RSENSE
PGND
Figure 12. Improving current sensing accuracy
More accurate sensing can be achieved by using a resistor
(R1) instead of the RDS(ON) of the FET as shown in Figure
12. This approach causes higher losses, but yields greater
accuracy in both VDROOP and ILIMIT. R1 is a low value
(e.g. 10mΩ) resistor.
MOSFET’s RDS(ON)
:
I
LOAD(MAX) • RDS(ON) • 4.1K
0.30 • 0.125 • VIN(MAX)
(4a)
(4b)
RSENSE = ---------------------------------------------------------------------------- – 1 0 0
Current limit (ILIMIT) should be set sufficiently high as to
allow inductor current to rise in response to an output load
transient. Typically, a factor of 1.3 is sufficient. In addition,
since ILIMIT is a peak current cut-off value, we will need to
multiply ILOAD(MAX) by the inductor ripple current (we’ll
use 25ꢀ). For example, in Figure 5 the target for ILIMIT
would be:
RSENSE must, however, be kept higher than:
I
LOAD(MAX) • RDS(ON)
RSENSE(MIN) = ----------------------------------------------------------- – 1 0 0
150µA
Setting the Current Limit
I
> 1.2 × 1.25 × 1.6 × 6A ≈14A
(6)
LIMIT
A ratio of ISNS is also compared to the current established
when a 0.9 V internal reference drives the ILIM pin. The
threshold is determined at the point
Duty Cycle Clamp
During severe load increase, the error amplifier output can
go to its upper limit pushing a duty cycle to almost 100ꢀ for
significant amount of time. This could cause a large increase
of the inductor current and lead to a long recovery from a
transient, over-current condition, or even to a failure espe-
cially at high input voltages. To prevent this, the output of
the error amplifier is clamped to a fixed value after two clock
cycles if severe output voltage excursion is detected, limiting
the maximum duty cycle to
ISNS ILIM × 4
when the
. Since
------------- ----------------------
>
9
3
ILOAD × RDS(ON)
ISNS = ------------------------------------------- therefore,
100 + RSENSE
9 × (100 + RSENSE
)
0.9V
RILIM
4
3
(5a)
(5b)
-------------- -- ------------------------------------------------
ILIMIT
=
×
×
RDS(ON)
or
(100 + RSENSE
)
11.2
ILIMIT
VOUT
2.4
---------------- ---------------------------------------
RILIM
=
×
RDS(ON)
DCMAX = -------------- + ---------
VIN
VIN
Since the tolerance on the current limit is largely dependent
on the ratio of the external resistors it is fairly accurate if the
voltage drop on the Switching Node side of RSENSE is an
accurate representation of the load current. When using the
MOSFET as the sensing element, the variation of RDS(ON)
causes proportional variation in the ISNS. This value not
only varies from device to device, but also has a typical junc-
tion temperature coefficient of about 0.4ꢀ / °C (consult the
MOSFET datasheet for actual values), so the actual current
limit set point will decrease propotional to increasing
MOSFET die temperature. A factor of 1.6 in the current
limit setpoint should compensate for all MOSFET RDS(ON)
variations, assuming the MOSFET’s heat sinking will keep
its operating die temperature below 125°C.
This circuit is designed to not interfere with normal PWM
operation. When FPWM is grounded, the duty cycle clamp
is disabled and the maximum duty cycle is 87ꢀ.
Gate Driver section
The Adaptive gate control logic translates the internal PWM
control signal into the MOSFET gate drive signals providing
necessary amplification, level shifting and shoot-through
protection. Also, it has functions that help optimize the IC
performance over a wide range of operating conditions.
Since MOSFET switching time can vary dramatically from
type to type and with the input voltage, the gate control logic
provides adaptive dead time by monitoring the gate-to-
source voltages of both upper and lower MOSFETs.
12
REV. 1.1.7 4/4/03
FAN5236
PRODUCT SPECIFICATION
The lower MOSFET drive is not turned on until the gate-to-
source voltage of the upper MOSFET has decreased to less
than approximately 1 volt. Similarly, the upper MOSFET is
not turned on until the gate-to-source voltage of the lower
MOSFET has decreased to less than approximately 1 volt.
This allows a wide variety of upper and lower MOSFETs to
be used without a concern for simultaneous conduction, or
shoot-through.
C2
C1
R2
R1
VIN
EA Out
REF
There must be a low-resistance, low-inductance path
between the driver pin and the MOSFET gate for the adap-
tive dead-time circuit to work properly. Any delay along that
path will subtract from the delay generated by the adaptive
dead-time circit and shoot-through may occur.
C
o
n
v
e
rr
e
o
r
r a
t
er
m
p
modulator
18
14
0
Frequency Loop Compensation
FP0
FZ
FP
Due to the implemented current mode control, the modulator
has a single pole response with -1 slope at frequency deter-
mined by load
Figure 13. Compensation
1
FPO = ---------------------
(7)
Conditional stability may occur only when the main load
pole is positioned too much to the left side on the frequency
axis due to excessive output filter capacitance. In this case,
the ESR zero placed within the 10kHz...50kHz range gives
some additional phase ‘boost’. Fortunately, there is an oppo-
site trend in mobile applications to keep the output capacitor
as small as possible.
2πROCO
where RO is load resistance, CO is load capacitance.
For this type of modulator, Type 2 compensation circuit is
usually sufficient. To reduce the number of external compo-
nents and simplify the design task, the PWM controller has
an internally compensated error amplifier. Figure 13 shows a
Type 2 amplifier and its response along with the responses of
a current mode modulator and of the converter. The Type 2
amplifier, in addition to the pole at the origin, has a zero-pole
pair that causes a flat gain region at frequencies between the
zero and the pole.
If a larger inductor value or low ESR values are called for by
the application, additional phase margin can be achieved by
putting a zero at the LC crossover frequency. This can be
achieved with a capacitor across across the feedback resistor
(e.g. R5 from Figure 5) as shown below.
L(OUT)
VOUT
C(OUT)
1
(8a)
(8b)
FZ = ------------------- = 6kHz
2πR2C1
R5 C(Z)
R6
1
VSEN
FP = ------------------- = 600kHz
2πR2C2
This region is also associated with phase ‘bump’ or reduced
phase shift. The amount of phase shift reduction depends the
width of the region of flat gain and has a maximum value of
90 degrees. To further simplify the converter compensation,
the modulator gain is kept independent of the input voltage
variation by providing feed-forward of VIN to the oscillator
ramp.
Figure 14. Improving Phase Margin
The optimal value of C(Z) is:
L(OUT) × C(OUT)
C(Z) = ------------------------------------------------------
R5
(9)
The zero frequency, the amplifier high frequency gain and
the modulator gain are chosen to satisfy most typical appli-
cations. The crossover frequency will appear at the point
where the modulator attenuation equals the amplifier high
frequency gain. The only task that the system designer has to
complete is to specify the output filter capacitors to position
the load main pole somewhere within one decade lower than
the amplifier zero frequency. With this type of compensation
plenty of phase margin is easily achieved due to zero-pole
pair phase ‘boost’.
Protection
The converter output is monitored and protected against
extreme overload, short circuit, over-voltage and under-
voltage conditions.
A sustained overload on an output sets the PGx pin low and
latches-off the whole chip. Operation can be restored by
cycling the VCC voltage or by toggling the EN pin.
REV. 1.1.7 4/4/03
13
PRODUCT SPECIFICATION
FAN5236
If VOUT drops below the under-voltage threshold, the chip
shuts down immediately.
Design and Component Selection
Guidelines
As an initial step, define operating input voltage range, out-
put voltage, minimum and maximum load currents for the
controller.
Over-Current sensing
If the circuit’s current limit signal (“ILIM det” as shown in
Figure 11) is high at the beginning of a clock cycle, a pulse-
skipping circuit is activated and HDRV is inhibited. The
circuit continues to pulse skip in this manner for the next 8
clock cycles. If at any time from the 9th to the 16th clock
cycle, the “ILIM det” is again reached, the over-current
protection latch is set, disabling the the chip. If “ILIM det”
does not occur between cycle 9 and 16, normal operation is
restored and the over-current circuit resets itself.
Setting the Output Voltage
The interal reference is 0.9V. The output is divided down by
a voltage divider to the VSEN pin (for example, R5 and R6
in Figure 4). The output voltage therefore is:
V
OUT – 0.9V
----------- = --------------------------------
R6 R5
0.9V
(10a)
To minimize noise pickup on this node, keep the resistor to
GND (R6) below 2K. We selected R6 at 1.82K. Then choose
R5:
PGOOD
1
2
8 CLK
IL
(1.82K)(VOUT – 0.9)
(10b)
R5 = ----------------------------------------------------- = 3 . 2 4 K
SHUTDOWN
0.9
VOUT
For DDR applications converting from 3.3V to 2.5V, or other
applications requiring high duty cycles, the duty cycle clamp
must be disabled by tying the converter’s FPWM to GND.
When converter’s FPWM is GND, the converter’s maximum
duty cycle will be greater than 90ꢀ. When using as a DDR
converter with 3.3V input, set up the converter for In-Phase
synchronization by tying the VIN pin to +5V.
3
CH1 5.0V
CH2 2.0AΩ
CH2 100mV
M 10.0µs
Figure 15. Over-Current protection waveforms
Output Inductor Selection
The minimum practical output inductor value is the one that
keeps inductor current just on the boundary of continuous
conduction at some minimum load. The industry standard
practice is to choose the minimum current somewhere from
15ꢀ to 35ꢀ of the nominal current. At light load, the
controller can automatically switch to hysteretic mode of
operation to sustain high efficiency. The following equations
help to choose the proper value of the output filter inductor.
Over-Voltage / Under-voltage Protection
Should the VSNS voltage exceed 120ꢀ of VREF (0.9V) due
to an upper MOSFET failure, or for other reasons, the over-
voltage protection comparator will force LDRV high. This
action actively pulls down the output voltage and, in the
event of the upper MOSFET failure, will eventually blow the
battery fuse. As soon as the output voltage drops below the
threshold, the OVP comparator is disengaged.
∆VOUT
ESR
This OVP scheme provides a ‘soft’ crowbar function which
helps to tackle severe load transients and does not invert the
output voltage when activated — a common problem for
latched OVP schemes.
(11)
∆I = 2 × IMIN = ------------------
where ∆I is the inductor ripple current and ∆VOUT is the
maximum ripple allowed.
Similarly, if an output short-circuit or severe load transient
causes the output to droop to less than 75ꢀ of its regulation
set point. Should this condition occur, the regulator will shut
down.
VIN – VOUT VOUT
------------------------------ --------------
L =
×
(12)
FSW × ∆I
VIN
for this example we’ll use:
Over-Temperature Protection
VIN = 20V, VOUT = 2.5V
∆I = 20ꢀ * 6A = 1.2A
FSW = 300KHz.
The chip incorporates an over temperature protection circuit
that shuts the chip down when a die temperature of about
150°C is reached. Normal operation is restored at die
temperature below 125°C with internal Power On Reset
asserted, resulting in a full soft-start cycle.
therefore
L ≈ 6µH
14
REV. 1.1.7 4/4/03
FAN5236
PRODUCT SPECIFICATION
therefore:
Output Capacitor Selection
The output capacitor serves two major functions in a switch-
ing power supply. Along with the inductor it filters the
sequence of pulses produced by the switcher, and it supplies
the load transient currents. The output capacitor require-
ments are usually dictated by ESR, Inductor ripple current
(∆I) and the allowable ripple voltage (∆V).
2
2.5
------
16
2.5
IRMS = 3.5 ------ –
16
= 1.49A
(17)
Dual Converter 180° phased
In Dual mode (Figure 5), both converters contribute to the
capacitor input ripple current. With each converter operating
180° out of phase, the RMS currents add in the following
fashion:
∆V
-------
ESR <
(13)
∆I
In addition, the capacitor’s ESR must be low enough to allow
the converter to stay in regulation during a load step. The
ripple voltage due to ESR for the converter in Figure 5 is
120mV P-P. Some additional ripple will appear due to the
capacitance value itself:
2
IRMS
IRMS
=
=
IRMS(1)2 + IRMS(2) or
(18a)
(18b)
(I1)2(D1 – D12) + (I2)2(D2 – D2
)
2
which for the dual 3A converters of Figure 5, calculates to:
IRMS = 1.4A
∆I
∆V = ----------------------------------------
(14)
COUT × 8 × FSW
which is only about 1.5mV for the converter in Figure 5 and
can be ignored.
Power MOSFET Selection
Losses in a MOSFET are the sum of its switching (PSW) and
conduction (PCOND) losses.
The capacitor must also be rated to withstand the RMS
current which is approximately 0.3 X (∆I), or about 400mA
for the converter in Figure 5. High frequency decoupling
capacitors should be placed as close to the loads as
physically possible.
In typical applications, the FAN5236 converter’s output volt-
age is low with respect to its input voltage, therefore the
Lower MOSFET (Q2) is conducting the full load current for
most of the cycle. Q2 should therefore be selected to mini-
mize conduction losses, thereby selecting a MOSFET with
Input Capacitor Selection
The input capacitor should be selected by its ripple current
rating.
low RDS(ON)
.
In contrast, the high-side MOSFET (Q1) has a much shorter
duty cycle, and it’s conduction loss will therefore have less
of an impact. Q1, however, sees most of the switching losses,
so Q1’s primary selection criteria should be gate charge.
Two-Stage Converter Case
In DDR mode (Figure 4), the VTT power input is powered
by the VDDQ output, therefore all of the input capacitor rip-
ple current is produced by the VDDQ converter. A conserva-
tive estimate of the output
High-Side Losses:
Figure 15 shows a MOSFET’s switching interval, with the
upper graph being the voltage and current on the Drain to
Source and the lower graph detailing VGS vs. time with a
constant current charging the gate. The x-axis therefore is
current required for the 2.5V regulator is:
IVTT
IREG1 = IVDDQ + -----------
2
also representative of gate charge (QG) . CISS = CGD + CGS
,
and it controls t1, t2, and t4 timing. CGD receives the current
from the gate driver during t3 (as VDS is falling). The gate
charge (QG) parameters on the lower graph are either
specified or can be derived from MOSFET datasheets.
As an example, if average IVDDQ is 3A, and average IVTT is
1A, IVDDQ current will be about 3.5A. If average input volt-
age is 16V, RMS input ripple current will be:
IRMS = IOUT(MAX) D – D2
(15)
Assuming switching losses are about the same for both the
rising edge and falling edge, Q1’s switching losses, occur
during the shaded time when the MOSFET has voltage
across it and current through it.
where D is the duty cycle of the PWM1 converter:
VOUT
2.5
= ------
16
--------------
VIN
(16)
D <
REV. 1.1.7 4/4/03
15
PRODUCT SPECIFICATION
FAN5236
These losses are given by:
QG(SW)
IDRIVER
QG(SW)
P
= P + P
SW COND
UPPER
-------------------- ----------------------------------------------------
tS
=
≈
(20)
VCC – VSP
VDS × IL
----------------------------------------------
DRIVER + RGATE
R
---------------------
2
PSW
=
× 2 × tS FSW
(19a)
(19b)
Most MOSFET vendors specify QGD and QGS. QG(SW) can
be determined as: QG(SW) = QGD + QGS – QTH where QTH is
the the gate charge required to get the MOSFET to it’s
threshold (VTH). For the high-side MOSFET, VDS = VIN,
which can be as high as 20V in a typical portable applica-
tion. Care should also be taken to include the delivery of the
MOSFET’s gate power (PGATE ) in calculating the power
dissipation required for the FAN5236:
VOUT
--------------
PCOND
=
× IOUT2 × RDS(ON)
VIN
PUPPER is the upper MOSFET’s total losses, and PSW and
COND are the switching and conduction losses for a given
P
MOSFET. RDS(ON) is at the maximum junction temperature
(TJ). tS is the switching period (rise or fall time) and is t2+t3
Figure 15.
P
= Q × VCC × F
G SW
GATE
(21)
The driver’s impedance and CISS determine t2 while t3’s
where QG is the total gate charge to reach VCC.
period is controlled by the driver’s impedance and QGD
Since most of tS occurs when VGS = VSP we can use a
.
constant current assumption for the driver to simplify the
calculation of tS:
Low-Side Losses
Q2, however, switches on or off with its parallel shottky
diode conducting, therefore VDS ≈ 0.5V. Since PSW is
proportional to VDS , Q2’s switching losses are negligible
and we can select Q2 based on RDS(ON) only.
CISS
CRSS
CISS
VDS
Conduction losses for Q2 are given by:
PCOND = (1 – D) × IOUT2 × RDS(ON)
(22)
ID
where RDS(ON) is the RDS(ON) of the MOSFET at the highest
operating junction temperature and
QGS
QGD
VGS
VOUT
4.5V
D = --------------
is the minimum duty cycle for the converter.
VIN
VSP
VTH
Since DMIN < 20ꢀ for portable computers, (1-D) ≈ 1
produces a conservative result, further simplifying the
calculation.
QG(SW)
t1
CISS = CGS || CGD
t2
t3
t4
t5
The maximum power dissipation (PD(MAX) ) is a function of
the maximum allowable die temperature of the low-side
MOSFET, the θJ-A, and the maximum allowable ambient
temperature rise:
Figure 16. Switching losses and QG
T
J(MAX) – TA(MAX)
PD(MAX) = -------------------------------------------------
θJ – A
VIN
(23)
5V
CGD
RD
RGATE
θ
J-A, depends primarily on the amount of PCB area that can
HDRV
SW
G
be devoted to heat sinking (see FSC app note AN-1029 for
SO-8 MOSFET thermal information).
CGS
Figure 17. Drive Equivalent Circuit
16
REV. 1.1.7 4/4/03
FAN5236
PRODUCT SPECIFICATION
Keep the wiring traces from the IC to the MOSFET gate and
source as short as possible and capable of handling peak
currents of 2A. Minimize the area within the gate-source
path to reduce stray inductance and eliminate parasitic ring-
ing at the gate.
Layout Considerations
Switching converters, even during normal operation,
produce short pulses of current which could cause substan-
tial ringing and be a source of EMI if layout constrains are
not observed.
Locate small critical components like the soft-start capacitor
and current sense resistors as close as possible to the respec-
tive pins of the IC.
There are two sets of critical components in a DC-DC
converter. The switching power components process large
amounts of energy at high rate and are noise generators. The
low power components responsible for bias and feedback
functions are sensitive to noise.
The FAN5236 utilizes advanced packaging technologies
with lead pitches of 0.6mm. High performance analog semi-
conductors utilizing narrow lead spacing may require special
considerations in PWB design and manufacturing. It is
critical to maintain proper cleanliness of the area surround-
ing these devices. It is not recommended to use any type of
rosin or acid core solder, or the use of flux in either the
manufacturing or touch up process as these may contribute
to corrosion or enable electromigration and/or eddy currents
near the sensitive low current signals. When chemicals such
as these are used on or near the PWB, it is suggested that the
entire PWB be cleaned and dried completely before applying
power.
A multi-layer printed circuit board is recommended. Dedi-
cate one solid layer for a ground plane. Dedicate another
solid layer as a power plane and break this plane into smaller
islands of common voltage levels.
Notice all the nodes that are subjected to high dV/dt voltage
swing such as SW, HDRV and LDRV, for example. All
surrounding circuitry will tend to couple the signals from
these nodes through stray capacitance. Do not oversize
copper traces connected to these nodes. Do not place traces
connected to the feedback components adjacent to these
traces. It is not recommended to use High Density Intercon-
nect Systems, or micro-vias on these signals. The use of
blind or buried vias should be limited to the low current
signals only. The use of normal thermal vias is left to the
discretion of the designer.
REV. 1.1.7 4/4/03
17
PRODUCT SPECIFICATION
FAN5236
Mechanical Dimensions
28-Pin QSOP
Notes:
Inches
Millimeters
Symbol
Notes
1. Symbols are defined in the "MO Series Symbol List" in
Section 2.2 of Publication Number 95.
Min.
Max.
Min.
Max.
A
0.053
0.004
-
0.069
0.010
0.061
0.012
0.010
0.394
0.157
1.35
0.10
-
1.75
0.25
1.54
0.30
0.25
10.00
3.98
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
A1
A2
B
3. Dimension "D" does not include mold flash, protrusions
or gate burrs. Mold flash, protrusions shall not exceed
0.25mm (0.010 inch) per side.
0.008
0.007
0.386
0.150
0.20
0.18
9.81
3.81
9
4. Dimension "E" does not include interlead flash or
protrusions. Interlead flash and protrusions shall not
exceed 0.25mm (0.010 inch) per side.
C
D
E
3
4
5. The chamber on the body is optional. If it is not present,
a visual index feature must be located within the
crosshatched area.
e
0.025 BSC
0.635 BSC
H
h
0.228
0.244
5.80
0.26
0.41
6.19
0.49
1.27
0.0099 0.0196
5
6
7
6. "L" is the length of terminal for soldering to a substrate.
7. "N" is the maximum number of terminals.
0.016
0.050
L
N
α
28
28
8. Terminal numbers are shown for reference only.
0°
8°
0°
8°
9. Dimension "B" does not include dambar protrusion.
Allowable dambar protrusion shall be 0.10mm (0.004
inch) total in excess of "B" dimension at maximum
material condition.
10. Controlling dimension: INCHES. Converted millimeter
dimensions are not necessarily exact.
D
E
H
C
A1
A
A2
α
SEATING
PLANE
– C –
L
B
LEAD COPLANARITY
ccc C
e
18
REV. 1.1.7 4/4/03
FAN5236
PRODUCT SPECIFICATION
Mechanical Dimensions
28-Pin TSSOP
9.7 0.1
0.51 TYP
28
15
– B –
0.2
B A
0.65
0.42
14
ALL Lead Tips
PIN # 1 IDENT
LAND PATTERN RECOMMENDATION
1.2 MAX
0.1 C
ALL LEAD TIPS
+0.15
–0.10
0.90
See Detail A
0.09–0.20
– C –
0.10 0.05
C
0.65
0.19–0.30
0.13
A B
12.00° Top & Botom
R0.16
R0.31
GAGE PLANE
.025
DIMENSIONS ARE IN MILLIMETERS
0°–8°
0.61 0.1
NOTES:
SEATING PLANE
A. Conforms to JEDEC registration MO-153, variation AB,
Ref. Note 6, dated 7/93.
1.00
B. Dimensions are in millimeters.
C. Dimensions are exclusive of burrs, mold flash, and tie bar extensions.
D Dimensions and Tolerances per ANsI Y14.5M, 1982
DETAIL A
REV. 1.1.7 4/4/03
19
PRODUCT SPECIFICATION
FAN5236
Ordering Information
Part Number
FAN5236QSC
FAN5236QSCX
FAN5236MTC
FAN5236MTCX
Temperature Range
-10°C to 85°C
Package
QSOP-28
QSOP-28
TSSOP-28
TSSOP-28
Packing
Rails
-10°C to 85°C
Tape and Reel
Rails
-10°C to 85°C
-10°C to 85°C
Tape and Reel
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO
ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME
ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
4/4/03 0.0m 004
Stock#DS30005236
2002 Fairchild Semiconductor Corporation
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