FAN5240QSC [FAIRCHILD]
Multi-Phase PWM Controller for AMD Mobile Athlon TM and Duron TM; 多相PWM控制器，用于AMD移动Athlon TM和Duron TM
| 型号： | FAN5240QSC |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Multi-Phase PWM Controller for AMD Mobile Athlon TM and Duron TM |
| 文件： | 总19页 (文件大小：448K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
www.fairchildsemi.com
FAN5240
Multi-Phase PWM Controller for AMD Mobile
TM
TM
Athlon and Duron
Features
General Description
• CPU Core power: 0.925V to 2.0V output range
• ±±1 reꢀerenꢁe preꢁcicon over temperature
• Dynamcꢁ voltage iettcng wcth 5-bct DAC
• 5V to 24V cnput voltage range
The FAN5240 ci a icngle output 2-Phaie iynꢁhronoui buꢁk
ꢁontroller to power AMD’i mobcle CPU ꢁore. The FAN5240
cnꢁludei a 5-bct dcgctal-to-analog ꢁonverter (DAC) that
adjuiti the ꢁore PWM output voltage ꢀrom 0.925VDC to
2.0VDC, whcꢁh may be ꢁhanged durcng operatcon. Speꢁcal
meaiurei are taken to allow the output to tranictcon wcth
ꢁontrolled ilew rate to ꢁomply wcth AMD’i Power Now
teꢁhnology. The FAN5240 cnꢁludei a preꢁcicon reꢀerenꢁe,
and a proprcetary arꢁhcteꢁture wcth cntegrated ꢁompeniatcon
provcdcng exꢁellent itatcꢁ and dynamcꢁ ꢁore voltage regula-
tcon. The regulator cnꢁludei ipeꢁcal ꢁcrꢁuctry whcꢁh balanꢁei
the 2 phaie ꢁurrenti ꢀor maxcmum eꢀfiꢁcenꢁy.
• 2 phaie cnterleaved iwctꢁhcng
• Aꢁtcve droop to reduꢁe output ꢁapaꢁctor icze
• Dcꢀꢀerentcal remote voltage ienie
• Hcgh eꢀfiꢁcenꢁy:
>901 eꢀfiꢁcenꢁy over wcde load range
>801 eꢀfiꢁcenꢁy at lcght load
• Exꢁellent dynamcꢁ reiponie wcth Voltage Feed-Forward
and Average Current Mode ꢁontrol
• Dynamcꢁ duty ꢁyꢁle ꢁlamp mcncmczei cnduꢁtor ꢁurrent
bucld up
• Loiileii ꢁurrent ienicng on low-icde MOSFET or
Preꢁcicon ꢁurrent ienicng uicng ienie reicitor
• Fault proteꢁtconi: Over-voltage, Over-ꢁurrent, and
Thermal Shut-down
At lcght loadi, when the filter cnduꢁtor ꢁurrent beꢁomei
dciꢁontcnuoui, the ꢁontroller operatei cn a hyiteretcꢁ mode,
dramatcꢁally cmprovcng iyitem eꢀfiꢁcenꢁy. The hyiteretcꢁ
mode oꢀ operatcon ꢁan be cnhcbcted by the FPWM ꢁontrol
pcn.
• Controli: Enable, Forꢁed PWM, Power Good, Power
Good Delay
• QSOP28, TSSOP28
The FAN5240 monctori the output voltage and ciiuei a
PGOOD (Power-Good) when ioꢀt itart ci ꢁompleted and the
output ci cn regulatcon. A pcn ci provcded to add delay to
PGOOD wcth an external ꢁapaꢁctor.
Applications
• AMD Mobcle Athlon CPU VCORE Regulator
• AMD Mobcle Duron CPU VCORE Regulator
A buclt-cn over-voltage proteꢁtcon (OVP) ꢀorꢁei the lower
MOSFET on to prevent the output ꢀrom exꢁeedcng a iet
voltage. The PWM ꢁontroller'i overꢁurrent ꢁcrꢁuctry monc-
tori the ꢁonverter load by ienicng the voltage drop aꢁroii the
lower MOSFET. The overꢁurrent threihold ci iet by an exter-
nal reicitor. Iꢀ preꢁcicon overꢁurrent proteꢁtcon ci requcred,
an optconal external ꢁurrent-ienie reicitor may be uied.
REV. 1.1.7 8/29/02
FAN5240
PRODUCT SPECIFICATION
Typical Application
VIN (BATTERY)
= 5 to 24V
VIN
21
C1
C7
C2
+5
D2
VCC
BOOT1
+5
28
25
C3 C4
Q1
C8
HDRV1
24
23
SW1
+5
Phase 1
Q2
Q3
R1
LDRV1
27
R2
PGOOD
EN
19
14
PGND1
ISNS1
26
22
R6
VCORE
VCORE +
VCORE D
C5
18
17
C12 C13 C14
C15 C16
FPWM
12
VID0
VID1
VID2
VID3
VID4
11
10
9
D1
+5
BOOT2
3
VIN
C9
Q4
HDRV2
SW2
8
C6
Q6
4
5
7
Phase 2
SS
C11
20
16
Q5
C10
DELAY
LDRV2
1
R3
R4
ILIM
PGND2
ISNS2
13
15
2
6
AGND
Figure 1. AMD Mobile Athlon/Duron CPU Core Supply
Table 1. BOM for Figure 1
Description
Capacitor 22µF, Ceramic X7R 25V
Capacitor 1µF, Ceramic
Qty
2
Ref.
Vendor
Part Number
C1, C2
C3,C7,C9
C4–C6, C8, C11, C12 Any
TDK
3
Any
Capacitor 0.1µF, Ceramic
Capacitor 0.22µF, Ceramic
Capacitor 270µF, 2V, ESR 15mΩ
10KΩ, 5% Resistor
6
1
C10
Any
4
C13–C16
R1
Panasonic EEFUE0D271R
2
Any
Any
Any
1KΩ, 1% Resistor
1
R2, R3, R6
R4
56.2KΩ, 1% Resistor
2
Schottky Diode 40V
2
D1, D2
L1, L2
Fairchild
MBR0540
Inductor 1.6µH, 20A, 2.4mΩ
N-Channel SO-8 MOSFET, 11mΩ
N-Channel SO-8 SyncFET™ MOSFET, 6mΩ
1
Panasonic ETQP6F0R8LFA
1
Q1, Q4
Q2, Q3, Q5, Q6
Fairchild
Fairchild
FDS6694
1
FDS6676S
2
REV. 1.1.7 8/29/02
PRODUCT SPECIFICATION
FAN5240
Pin Configuration
LDRV2
PGND2
BOOT2
HDRV2
SW2
VCC
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
LDRV1
PGND1
BOOT1
HDRV1
SW1
2
3
4
5
ISNS2
VID4
6
ISNS1
VIN
7
FAN5240
VID3
8
VID2
SS
9
VID1
PGOOD
VCORE+
VCORED
DELAY
AGND
10
11
12
13
14
VID0
FPWM
ILIM
EN
QSOP-28 or TSSOP-28
= 90°C/W
θ
JA
Pin Definitions
Pin
Number
Pin
Name
Pin Function Description
1
LDRV2 Low-Side Drive. The low-side (lower) MOSFET driver output.
27
LDRV1
2
PGND2 Power Ground. The return for the low-side MOSFET driver.
26
PGND1
3
BOOT2 BOOT. The positive supply for the upper MOSFET driver. Connect as shown in Figure 1.
25
BOOT1
4
HDRV2 High-Side Drive. The high-side (upper) MOSFET driver output.
24
HDRV1
5
23
SW2
SW1
Switching node. The return for the high-side MOSFET driver.
6
22
ISNS2
ISNS1
Current Sense input. Monitors the voltage drop across the lower MOSFET or external
sense resistor for current feedback.
7 - 11
VID4 -
VID0
Voltage Identification Code. Input to VID DAC. Sets the output voltage according to the
codes set as defined in Table 2. These inputs have 1µA internal pull-up.
12
FPWM
Forced PWM mode. When logic high, inhibits the chip from entering hysteretic operating
mode. If tied low, hysteretic mode will be allowed.
13
14
ILIM
EN
Current Limit. A resistor from this pin to GND sets the current limit.
ENABLE. This pin enables IC operation when either left open, or pulled up to VCC.
Toggling EN will also reset the chip after a latched fault condition.
15
16
AGND
Analog Ground. This is the signal ground reference for the IC. All voltage levels are
measured with respect to this pin.
DELAY Power Good / Over-Current Delay. A capacitor to GND on this pin delays the PGOOD
from going high as well delaying the over-current shutdown.
18
17
VCORE+ VCORE Output Sense. Differential sensing of the output voltage. Used for regulation as
VCORE– well as PGOOD, under-voltage and over-voltage protection and monitoring. A resistor in
series with this VCORE+ sets the output voltage droop.
19
PGOOD Power Good Flag. An open-drain output that will pull LOW when the core output below
825mV. PGOOD delays its low to high transition for a time determined by CDELAY when
VCORE rises above 875mV.
REV. 1.1.7 8/29/02
3
FAN5240
PRODUCT SPECIFICATION
Pin Definitions (continued)
Pin
Number
Pin
Name
Pin Function Description
20
SS
Soft Start. A capacitor from this pin to GND programs the slew rate of the converter during
initialization as well as in operation. This pin is used as the reference against which the
output is compared. During initialization, this pin is charged with a 25µA current source.
Once this pin reaches 0.5V, its function changes, and it assumes the value of the voltage
as set by the VID programming. The current driving this pin is then limited to 500µA, that
together with C sets a controlled slew rate for VID code changes.
SS
21
28
VIN
Input voltage from battery. This voltage is used by the oscillator for feed-forward
compensation of input voltage variation.
VCC
VCC. This pin powers the chip. The IC starts to operate when voltage on this pin exceeds
4.6V (UVLO rising) and shuts down when it drops below 4.3V (UVLO falling).
Absolute Maximum Ratings
Absolute maximum ratings are the values beyond which the device may be damaged or have its useful life
impaired. Functional operation under these conditions is not implied.
Parameter
Min.
Typ.
Max.
6.5
Units
V
VCC Supply Voltage:
VIN
27
V
BOOT, SW, HDRV Pins
BOOT to SW
All Other Pins
33
V
6.5
V
–0.3
–10
–65
VCC+0.3
150
V
Junction Temperature (T )
J
°C
°C
°C
Storage Temperature
150
Lead Soldering Temperature, 10 seconds
300
Recommended Operating Conditions
Parameter
Supply Voltage VCC
Supply Voltage VIN
Conditions
Min.
4.75
6
Typ.
Max.
Units
V
5
5.25
24
V
Ambient Temperature (T )
–20
85
°C
A
4
REV. 1.1.7 8/29/02
PRODUCT SPECIFICATION
FAN5240
Electrical Specifications
(VCC = 5V, VIN = 6V–24V, and T = recommended operating ambient temperature range using circuit of Figure 1,
A
unless otherwise noted.)
Parameter
Conditions
Min.
Typ.
Max.
Units
Power Supplies
VCC Current
Operating, C = 10pF
L
2
10
mA
µA
µA
µA
V
Shut-down (EN=0)
Operating
1
VIN Current
25
Shut-down (EN=0)
Rising VCC
1
UVLO Threshold
4.3
3.8
4.45
3.95
4.6
4.10
Falling VCC
V
Regulator / Control Functions
Output voltage
per Table 2
0.925
2.00
V
dB
MHz
V/µS
µA
V
Error Amplifier Gain
Error Amplifier GBW
Error Amplifier Slew Rate
VCORE+ Input Current
ILIM Voltage
86
2.7
1
25
30
35
R
C
= 30KΩ
0.89
0.91
ILIM
ILIM T
HOLDOFF
= 22nF
1.16
2.35
2
mS
V
DELAY
Over-voltage Threshold
Over-voltage Protection delay
EN, input threshold
2.2
2
2.5
0.8
5
µS
V
Logic LOW
Logic HIGH
V
Phase to Phase current mismatch
IC contribution only
%
Guaranteed by design
Over-Temperature Shut-down
Over-Temperature Hysteresis
Output Drivers (note 1)
150
25
°C
°C
HDRV Output Resistance
Sourcing
Sinking
3.8
1.6
3.8
0.8
5
3
Ω
Ω
Ω
Ω
LDRV Output Resistance
Sourcing
Sinking
5
1.5
Oscillator
Frequency
255
300
2
345
KHz
V
Ramp Amplitude, pk–pk
Ramp Offset
Ramp Gain
VIN = 16V
0.5
125
V
RampAmplitude
----------------------------------------------
VIN
mV/V
Reference, DAC and Soft-Start
VID input threshold
Logic LOW
Logic HIGH
to VCC
0.8
V
V
2.0
VID pull-up current
1
µA
%
DAC output accuracy
–1
20
1
Soft Start Charging current (I
)
SS
V
V
< 90% of Programmed output
> 90% of Programmed output
27
34
µA
µA
SS
350
500
650
SS
Note 1: Guaranteed by slew rate testing.
REV. 1.1.7 8/29/02
5
FAN5240
PRODUCT SPECIFICATION
Electrical Specifications (continued)
Parameter
PGOOD
Conditions
Min.
Typ.
Max.
Units
VCORE Lower Threshold
Falling Edge
Rising Edge
800
850
825
875
12
850
900
mV
mV
mS
V
PGOOD Output Delay
PGOOD Output Low
Leakage Current
Low to High, CDELAY = 22nF
IPGOOD = 4mA
0.5
1
VPULLUP = 5V
µA
5V
VDD
CBOOT
BOOT
EN
SS
VIN
Q1
POR/UVLO
HYST
HDRV
SW
HYST
VCORE
L OUT
+
VOUT'
DAC
Soft Start &
OVP
Q2
COUT
FPWM
VDD
PGOOD
LDRV
Q
VIN
PWM
PGND
OSC
RAMP CLK
S
R
S/H
PWM/HYST
PWM
EA1
DUTY
CYCLE
CLAMP
RSENSE1
ILIM
det.
MODE
ISNS1
ISNS2
A
CURRENT
PROCESSING
RSENSE2
ISNS1-ISNS2
ISNS1+ISNS2
5
ISNS1 ISNS2
A2
VCORE+
A1
VOUT'
30mA
ILIM
B
VCORE-
TO PH 2
MODULATOR
ISNS2-ISNS1
1K
R6
Figure 2. IC Block Diagram
6
REV. 1.1.7 8/29/02
PRODUCT SPECIFICATION
FAN5240
Output Voltage Programming
Circuit Description
The output voltage oꢀ the ꢁonverter ci programmed by an
cnternal DAC cn dciꢁrete itepi oꢀ 25mV ꢀrom 0.925V to
±.300V and then cn 50mV itepi ꢀrom ±.300V to 2.00V:
Overview
The FAN5240 ci a 2-phaie, icngle output power management
IC, whcꢁh iupplcei the low-voltage, hcgh-ꢁurrent power to
modern proꢁeiiori ꢀor notebook PCi. Uicng very ꢀew exter-
nal ꢁomponenti, the IC ꢁontroli a preꢁcicon programmable
iynꢁhronoui buꢁk ꢁonverter drcvcng external N-Channel
power MOSFETi. The output voltage ci adjuitable ꢀrom
0.925V to 2.0V by ꢁhangcng the DAC (VID) ꢁode iettcngi
(iee Table 2). The output voltage oꢀ the ꢁore ꢁonverter ꢁan be
ꢁhanged on-the-fly wcth programmable ilew rate, whcꢁh
meeti a key requcrement oꢀ AMD'i Mobcle Athlon/Duron
proꢁeiiori.
Table 2. Output voltage VID
VID4 VID3 VID2 VID1 VID0 VOUT to CPU
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0.000
0.925
0.950
0.975
1.000
1.025
1.050
1.075
1.100
1.125
1.150
1.175
1.200
1.225
1.250
1.275
0.000
1.300
1.350
1.400
1.450
1.500
1.550
1.600
1.650
1.700
1.750
1.800
1.850
1.900
1.950
2.000
The ꢁonverter ꢁan operate cn two modei: fixed ꢀrequenꢁy
PWM, and varcable ꢀrequenꢁy hyiteretcꢁ dependcng on the
load. At loadi lower than the pocnt where filter cnduꢁtor ꢁur-
rent beꢁomei dciꢁontcnuoui, hyiteretcꢁ mode oꢀ operatcon ci
aꢁtcvated. Swctꢁhover ꢀrom PWM to hyiteretcꢁ operatcon at
lcght loadi cmprovei the ꢁonverter'i eꢀfiꢁcenꢁy and prolongi
battery run tcme. Ai the filter cnduꢁtor reiumei ꢁontcnuoui
ꢁurrent, the PWM mode oꢀ operatcon ci reitored.
1 - Logic High or open, 0 = Logic Low
VID0–4 pcni wcll aiiume a logcꢁ ± level cꢀ leꢀt open ai eaꢁh
cnput ci pulled up wcth a ±µA cnternal ꢁurrent iourꢁe.
REV. 1.1.7 8/29/02
7
FAN5240
PRODUCT SPECIFICATION
The PGOOD delay (TDLY, Fcgure 3) ꢁan be programmed
Initialization, Soft Start and PGOOD
wcth a ꢁapaꢁctor to GND on pcn ±6 (C
):
DELAY
Aiiumcng EN ci hcgh, FAN5240 ci cnctcalczed when power ci
applced on VCC. Should VCC drop below the UVLO threih-
old, an cnternal Power-On Reiet ꢀunꢁtcon dciablei the ꢁhcp.
CDELAY(in nF) = 1.8 × TDLY(in mS)
(3)
For ±2mS oꢀ TDLY, C
DELAY
= 22nF.
The IC attempti to regulate the VCORE output aꢁꢁordcng to
the voltage that appeari on the SS pcn (V ). Durcng itart-up
SS
oꢀ the ꢁonverter, thci voltage ci cnctcally 0, and rciei lcnearly
to 901 oꢀ the VID programmed voltage vca the ꢁurrent iup-
C
ci typcꢁally ꢁhoien to provcde ±mS oꢀ "blankcng"
DELAY
ꢀor the over-ꢁurrent ihut-down (see Over-Current Sensing,
on page ±2).
plced to C by the 25µA cnternal ꢁurrent iourꢁe. The tcme ct
SS
takei to reaꢁh thci threihold ci:
The ꢀollowcng ꢁondctconi iet the PGOOD pcn low:
±. Under-voltage - VCORE ci below a fixed voltage.
0.9 × VVID × CSS
(±)
T90% = --------------------------------------------
25
2. Chcp ihut-down due to over-temperature or over-ꢁurrent
ai defined below.
where T
901
ci cn ieꢁondi cꢀ C ci cn µF.
SS
At that pocnt, the ꢁurrent iourꢁe ꢁhangei to 500µA, whcꢁh
eitablcihei the ilew rate oꢀ voltage ꢁhangei at the output cn
reiponie to ꢁhangei cn VID.
Converter Operation (see Figure 2)
At nomcnal ꢁurrent the ꢁonverter operatei cn fixed ꢀrequenꢁy
PWM mode. The output voltage ci ꢁompared wcth a reꢀer-
enꢁe voltage iet by the DAC, whcꢁh appeari on the SS pcn.
The dercved error icgnal ci amplcfied by an cnternally ꢁom-
peniated error amplcfier and applced to the cnvertcng cnput
oꢀ the PWM ꢁomparator. To provcde output voltage droop ꢀor
enhanꢁed dynamcꢁ load regulatcon, a icgnal proportconal to
the output ꢁurrent ci added to the voltage ꢀeedbaꢁk icgnal
at the + cnput oꢀ A±. Scnꢁe the proꢁeiior ipeꢁcfiei a +±00mV/
-50mV toleranꢁe on VCORE, a fixed poictcve oꢀꢀiet oꢀ 30
mV ci ꢁreated wcth a 30µA ꢁurrent iourꢁe and external ±K
reicitor. Phaie load balanꢁcng ci aꢁꢁomplcihed by addcng
a icgnal proportconal to the dcꢀꢀerenꢁe oꢀ the two phaie
ꢁurrenti beꢀore the error amplcfier (at nodei A and B). Thci
ꢀeedbaꢁk iꢁheme cn ꢁonjunꢁtcon wcth a PWM ramp propor-
tconal to the cnput voltage allowi ꢀor ꢀait and itable loop
reiponie over a wcde range oꢀ cnput voltage and output
ꢁurrent varcatconi. For the iake oꢀ eꢀfiꢁcenꢁy and maxcmum
icmplcꢁcty, the ꢁurrent ienie icgnal ci dercved ꢀrom the volt-
age drop aꢁroii the lower MOSFET durcng cti ꢁonduꢁtcon
tcme. Thci ꢁurrent ienie icgnal ci uied to iet droop leveli ai
well ai ꢀor phaie balanꢁcng and ꢁurrent lcmctcng.
Thci dual ilope approaꢁh helpi to provcde iaꢀe rcie oꢀ volt-
agei and ꢁurrenti cn the ꢁonverteri durcng cnctcal itart-up and
at the iame tcme ieti a ꢁontrolled ipeed oꢀ the ꢁore voltage
ꢁhange when the proꢁeiior ꢁommandi to do io.
1.5V
1.35V
SS
EN
TDLY
PGOOD
Figure 3. Soft-Start function
C
typcꢁally ci ꢁhoien baied on the ilew rate deicred cn
SS
reiponie to a VID ꢁhange. For example, cꢀ the ipeꢁ requcrei a
500mV itep to oꢁꢁur cn ±00µS:
The PWM ꢁontroller hai a buclt-cn duty ꢁyꢁle ꢁlamp cn the
path ꢀrom the error amplcfier to the PWM ꢁomparator.
Durcng a ievere load itep, the output icgnal ꢀrom the error
amp ꢁan go to cti racl, puihcng the duty ꢁyꢁle to almoit ±001
ꢀor a icgncfiꢁant amount oꢀ tcme. Thci ꢁould ꢁauie a ievere
rcie cn the cnduꢁtor ꢁurrent, eipeꢁcally at hcgh battery volt-
age, and lead to a long reꢁovery tcme or even ꢀaclure oꢀ the
ꢁonverter. To prevent thci, the output oꢀ the error amplcfier ci
ꢁlamped to a fixed value aꢀter two ꢁloꢁk ꢁyꢁlei cꢀ a large
output voltage exꢁuricon ci deteꢁted. Senictcvcty oꢀ thci
ꢁcrꢁuct ci iet cn iuꢁh a way ai not to aꢀꢀeꢁt the PWM ꢁontrol
durcng tranicenti normally expeꢁted ꢀrom the load.
ISS
500µA
-------------------
500mV
------------------
CSS
=
∆t =
100µS = 0.1µF
(2)
∆VDAC
Aiiumcng VID ci iet to ±.5V, wcth thci value oꢀ C , the
SS
tcme ꢀor the output voltage to rcie to 0.9 oꢀ V
uicng equatcon ±:
ci ꢀound
VID
1.35V × 0.1
T90% = ------------------------------ = 5.4mS
25
The tranictcon ꢀrom 901 VID to ±001 VID oꢁꢁupcei 0.51
oꢀ the total ioꢀt-itart tcme, io TSS ci eiientcally T
.
901
8
REV. 1.1.7 8/29/02
PRODUCT SPECIFICATION
FAN5240
ꢁauiei the output voltage (ai preiented at VSNS) to drop
Operation Mode Control
below the hyiteretcꢁ regulatcon level (20mV below VREF),
the mode ci ꢁhanged to PWM on the next ꢁloꢁk ꢁyꢁle. Thci
cniurei the ꢀull power requcred by the cnꢁreaie cn output
ꢁurrent.
The mode-ꢁontrol ꢁcrꢁuct ꢁhangei the ꢁonverter’i mode oꢀ
operatcon ꢀrom PWM to Hyiteretcꢁ and vcia veria, baied
on the voltage polarcty oꢀ the SW node when the lower
MOSFET ci ꢁonduꢁtcng and juit beꢀore the upper MOSFET
turni on. For ꢁontcnuoui cnduꢁtor ꢁurrent, the SW node ci
negatcve when the lower MOSFET ci ꢁonduꢁtcng and the
ꢁonverteri operate cn fixed-ꢀrequenꢁy PWM mode ai ihown
cn Fcgure 4. Thci mode oꢀ operatcon aꢁhcevei hcgh eꢀfiꢁcenꢁy
at nomcnal load. When the load ꢁurrent deꢁreaiei to the pocnt
where the cnduꢁtor ꢁurrent flowi through the lower MOSFET
cn the ‘reverie’ dcreꢁtcon, the SW node beꢁomei poictcve,
and the mode ci ꢁhanged to hyiteretcꢁ, whcꢁh aꢁhcevei hcgher
eꢀfiꢁcenꢁy at low ꢁurrenti by deꢁreaicng the eꢀꢀeꢁtcve iwctꢁh-
cng ꢀrequenꢁy.
In hyiteretcꢁ mode, the PWM ꢁomparator and the error
amplcfier that provcde ꢁontrol cn PWM mode are cnhcbcted
and the hyiteretcꢁ ꢁomparator ci aꢁtcvated. In hyiteretcꢁ
mode the low icde MOSFET ci operated ai a iynꢁhronoui
reꢁtcfier, where the voltage aꢁroii V
DS(ON)
ci monctored,
and cti gate iwctꢁhed oꢀꢀ when V ) goei poictcve
DS(ON
(ꢁurrent flowcng baꢁk ꢀrom the load) bloꢁkcng reverie
ꢁonduꢁtcon
The hyiteretcꢁ ꢁomparator cnctcatei a PFM icgnal to turn on
HDRV when the output voltage (at VSNS) ꢀalli below the
lower threihold (±0mV below VREF) and termcnatei the
PFM icgnal when VSNS rciei over the hcgher threihold
(5mV above VREF).
To prevent aꢁꢁcdental mode ꢁhange or “mode ꢁhatter” the
tranictcon ꢀrom PWM to Hyiteretcꢁ mode oꢁꢁuri when the
SW node ci poictcve ꢀor ecght ꢁonieꢁutcve ꢁloꢁk ꢁyꢁlei
(iee Fcgure 4). The polarcty oꢀ the SW node ci iampled at the
end oꢀ the lower MOSFET'i ꢁonduꢁtcon tcme. At the tranic-
tcon between PWM and hyiteretcꢁ mode both the upper and
lower MOSFETi are turned oꢀꢀ. The phaie node wcll ‘rcng’
baied on the output cnduꢁtor and the paraictcꢁ ꢁapaꢁctanꢁe on
the phaie node and iettle out at the value oꢀ the output volt-
age.
The iwctꢁhcng ꢀrequenꢁy ci prcmarcly a ꢀunꢁtcon oꢀ:
±. Spread between the two hyiteretcꢁ threiholdi
2.
I
LOAD
3. Output Induꢁtor and Capaꢁctor ESR
The boundary value oꢀ cnduꢁtor ꢁurrent, where ꢁurrent
beꢁomei dciꢁontcnuoui, ꢁan be eitcmated by the ꢀollowcng
expreiicon.
A tranictcon baꢁk to PWM (Contcnuoui Conduꢁtcon Mode or
CCM) mode oꢁꢁuri when the cnduꢁtor ꢁurrent rciei iuꢀfi-
ꢁcently to itay poictcve ꢀor 8 ꢁonieꢁutcve ꢁyꢁlei. Thci oꢁꢁuri
when:
(VIN – V
)VOUT
ILOAD(DIS) = ----------------------O----U----T-------------------
(4)
2FSWLOUTVIN
∆VHYSTERESIS
ILOAD(CCM) = ----------------------------------------
(5)
2 ESR
Hysteretic Mode
Converiely, the tranictcon ꢀrom Hyiteretcꢁ mode to PWM
mode oꢁꢁuri when the SW node ci negatcve ꢀor 8 ꢁonieꢁutcve
ꢁyꢁlei.
where ∆V
= ±5mV and ESR ci the equcvalent
HYSTERESIS
iercei reicitanꢁe oꢀ C
.
OUT
Beꢁauie oꢀ the dcꢀꢀerent ꢁontrol meꢁhancimi, the value oꢀ the
load ꢁurrent where tranictcon cnto CCM operatcon takei plaꢁe
ci typcꢁally hcgher ꢁompared to the load level at whcꢁh tranic-
tcon cnto hyiteretcꢁ mode oꢁꢁuri.
A iudden cnꢁreaie cn the output ꢁurrent wcll alio ꢁauie a
ꢁhange ꢀrom hyiteretcꢁ to PWM mode. Thci load cnꢁreaie
ꢁauiei an cnitantaneoui deꢁreaie cn the output voltage due to
the voltage drop on the output ꢁapaꢁctor ESR. Iꢀ the load
VCORE
PWM Mode
Hysteretic Mode
IL
0
1
2
3
4
5
6
7
8
VCORE
Hysteretic Mode
3
PWM Mode
IL
0
1
2
4
5
6
7
8
Figure 4. Transitioning between PWM and Hysteretic Mode
REV. 1.1.7 8/29/02
9
FAN5240
PRODUCT SPECIFICATION
Wcth Aꢁtcve Droop, the output voltage varcei wcth the load ai
cꢀ a reicitor were ꢁonneꢁted cn iercei wcth the ꢁonverter’i out-
put, cn other wordi, ct'i eꢀꢀeꢁt ci to racie the output reicitanꢁe
oꢀ the ꢁonverter.
Current Processing Section
The ꢀollowcng dciꢁuiicon reꢀeri to Fcgure 6.
Setting RSENSE
Eaꢁh phaie ꢁurrent ci iampled about 200nS aꢀter the SW
node ꢁroiiei 0V. For proper ꢁonverter operatcon, ꢁhooie an
RSENSE value oꢀ:
1.2
VDROOP
R
DS(ON) • IMAX
RSENSE = ----------------------------------------
40µA
whcꢁh ci about ±K ꢀor the ꢁomponenti cn Fcgure ±.
ILOAD
IMAX
Active Droop
Figure 5. Active Droop
The ꢁore ꢁonverter cnꢁorporatei a proprcetary output voltage
droop method ꢀor optcmum handlcng oꢀ ꢀait load tranicenti
ꢀound cn modern proꢁeiiori.
To get the moit ꢀrom the Aꢁtcve Droop, cti magnctude ihould
be iꢁaled to matꢁh the output ꢁapaꢁctor’i ESR voltage drop.
“Aꢁtcve droop” or voltage poictconcng ci now wcdely uied cn
the ꢁomputer power applcꢁatconi. The teꢁhncque ci baied on
racicng the ꢁonverter voltage at lcght load cn antcꢁcpatcon oꢀ a
itep cnꢁreaie cn load ꢁurrent, and ꢁonveriely, lowercng
VCORE cn antcꢁcpatcon oꢀ a itep deꢁreaie cn load ꢁurrent.
VDROOP = IMAX × ESR
(6)
Aꢁtcve Droop allowi the icze and ꢁoit oꢀ the output ꢁapaꢁc-
tori requcred to handle CPU ꢁurrent tranicenti to be reduꢁed.
The reduꢁtcon may be almoit a ꢀaꢁtor oꢀ 2 when ꢁompared to
a iyitem wcthout Aꢁtcve Droop.
S/H
B-A
ISNS1-ISNS2
V to I
A
B
RSENSE
ISNS2
ISNS1
Σ
ISNS1
in +
in D
ISNS2-ISNS1
A-B
ISNS2
5
ISNS1
5
ISNS1
8
LDRV1
PGND1
To A1 (+)
RILIM
ILIM
0.9V
2.5V
I2 =
ILIM
ILIM det. 1
ILIM mirror
Figure 6. Current Limit and Active Droop Circuits
10
REV. 1.1.7 8/29/02
PRODUCT SPECIFICATION
FAN5240
Addctconally, the CPU power dciicpatcon ci alio ilcghtly
reduꢁed ai ct ci proportconal to the applced voltage iquared
and even ilcght voltage deꢁreaie tranilatei to a meaiurable
reduꢁtcon cn power dciicpated.
The ꢁurrent through eaꢁh R reicitor (ISNS) ci iam-
SENSE
pled ihortly aꢀter LDRV ci turned on. That ꢁurrent ci held ꢀor
the remacnder oꢀ the ꢁyꢁle, and then cnjeꢁted to produꢁe an
oꢀꢀiet to VCORE+ through the external ±K reicitor (R6 cn
Fcgure ±). Thci ꢁreatei a voltage at the cnput to the error
amplcfier that rciei wcth cnꢁreaicng ꢁurrent, ꢁauicng the regu-
lator’i output to droop ai the ꢁurrent cnꢁreaiei.
ILOAD
upper lim
Vout
ILOAD • RDS(ON)
(no droop)
VDROOP = -------------------------------------------
3 • RSENSE
(7)
VES
lower lim
upper lim
Gate Driver section
VES
Vout
droop ≈ ESR
The gate ꢁontrol logcꢁ tranilatei the cnternal PWM ꢁontrol
icgnal cnto the MOSFET gate drcve icgnali provcdcng
neꢁeiiary amplcfiꢁatcon, level ihcꢀtcng and ihoot-through
proteꢁtcon. Alio, ct hai ꢀunꢁtconi that help optcmcze the IC
perꢀormanꢁe over a wcde range oꢀ operatcng ꢁondctconi.
Scnꢁe MOSFET iwctꢁhcng tcme ꢁan vary dramatcꢁally ꢀrom
type to type and wcth the cnput voltage, the gate ꢁontrol logcꢁ
provcdei adaptcve dead tcme by monctorcng the gate-to-
iourꢁe voltagei oꢀ both upper and lower MOSFETi. The
lower MOSFET drcve ci not turned on untcl the gate-to-
iourꢁe voltage oꢀ the upper MOSFET hai deꢁreaied to leii
than approxcmately ± volt. Scmclarly, the upper MOSFET ci
not turned on untcl the gate-to-iourꢁe voltage oꢀ the lower
MOSFET hai deꢁreaied to leii than approxcmately ± volt.
Thci allowi a wcde varcety oꢀ upper and lower MOSFETi to
be uied wcthout a ꢁonꢁern ꢀor icmultaneoui ꢁonduꢁtcon, or
ihoot-through.
lower lim
Figure 7. Effect of Active Droop on ESR
The proꢁeiior regulatcon wcndow cnꢁludcng tranicenti ci
ipeꢁcfied ai +±00mV..–50mV. To aꢁꢁommodate the droop,
the output voltage oꢀ the ꢁonverter ci racied by about 30mV
at no load.
The ꢁonverter reiponie to the load itep ci ihown cn Fcgure 8.
At zero load ꢁurrent, the output voltage ci racied ~30mV
above nomcnal value oꢀ ±.5V. When the load ꢁurrent
cnꢁreaiei, the output voltage droopi down approxcmately
55mV. Due to uie oꢀ Aꢁtcve Droop, the ꢁonverter’i output
voltage adaptcvely ꢁhangei wcth the load ꢁurrent allowcng
better utclczatcon oꢀ the regulatcon wcndow.
There muit be a low – reicitanꢁe, low – cnduꢁtanꢁe path
between the drcver pcn and the MOSFET gate ꢀor the adap-
tcve dead-tcme ꢁcrꢁuct to work properly. Any delay along that
path wcll iubtraꢁt ꢀrom the delay generated by the adaptcve
dead-tcme ꢁcrꢁct and a ihoot-through ꢁondctcon may oꢁꢁur.
Frequency Loop Compensation
Due to the cmplemented ꢁurrent mode ꢁontrol, the modulator
hai a icngle pole reiponie wcth -± ilope at ꢀrequenꢁy deter-
mcned by load
1
FPO = -----------------------
(8)
2πROCO
where R ci load reicitanꢁe, C ci load ꢁapaꢁctanꢁe. For thci
O
O
Figure 8. Converter response to 5A load step
type oꢀ modulator Type 2 ꢁompeniatcon ꢁcrꢁuct ci uiually
iuꢀfiꢁcent. To reduꢁe the number oꢀ external ꢁomponenti and
icmplcꢀy the deicgn taik, the PWM ꢁontroller hai an cnter-
nally ꢁompeniated error amplcfier. Fcgure 9 ihowi a Type 2
amplcfier and cti reiponie along wcth the reiponiei oꢀ a ꢁur-
rent mode modulator and oꢀ the ꢁonverter. The Type 2 amplc-
fier, cn addctcon to the pole at the orcgcn, hai a zero-pole pacr
that ꢁauiei a flat gacn regcon at ꢀrequenꢁcei between the zero
and the pole.
REV. 1.1.7 8/29/02
11
FAN5240
PRODUCT SPECIFICATION
Over-Current sensing (see Figure 10)
C2
When the ꢁcrꢁuct'i ꢁurrent lcmct icgnal (“ILIM det” ai ihown
cn Fcgure 6) goei hcgh, a pulie-ikcppcng ꢁcrꢁuct ci aꢁtcvated
and a ±6-ꢁloꢁk ꢁyꢁle ꢁounter ci itarted. HDRV wcll be cnhcb-
cted ai long ai the ienied ꢁurrent ci hcgher than the ILIM
value. Thci lcmcti the ꢁurrent iupplced by the DC cnput.
R2 C1
R1
VIN
–
+
REF
EAOut
RESET
Clock
16 Clock
Counter and
Logic
Q TIMER
START
ILIM det. 1
ILIM det. 2
Modulator
Shut-down
18
14
0
DELAY
FP0
FZ
FP
Figure 10. Over-current shut-down delay logic
Iꢀ ILIM det goei hcgh durcng ꢁounti 9-±6 oꢀ the ꢁounter, the
overꢁurrent delay tcmer ci itarted and the ±6-ꢁloꢁk ꢁounter
itarti agacn. Thci tcmer delayi the ihut-down oꢀ the ꢁhcp and
Figure 9. Compensation
cti tcme ci a ꢀunꢁtcon oꢀ the value oꢀ C
.
DELAY
1
FZ = --------------------- = 6 kHz
2πR2C1
(9a)
(9b)
CDELAY(in nF)
1
THOLDOFF(in mS) = ---------------------------------------
(±0)
FP = --------------------- = 600 kHz
2πR2C2
19
Over-ꢁurrent muit deteꢁted at leait onꢁe durcng the firit 8
ꢁloꢁk ꢁyꢁlei and onꢁe durcng the 2nd 8 ꢁloꢁk ꢁyꢁlei oꢀ the
±6-ꢁyꢁle ꢁounter ꢀor the tcmer to ꢁontcnue tcmcng. Iꢀ the over-
ꢁurrent ꢁondctcon doei not oꢁꢁur at leait onꢁe per 8 ꢁloꢁk
ꢁounti durcng any ꢁloꢁk ꢁounter ꢁyꢁle whcle the tcmer ci
hcgh, the tcmer and the over-ꢁurrent deteꢁtcon ꢁcrꢁuct are
reiet, preventcng ihutdown. The ꢁloꢁk ꢁounter ꢁoutcnuei to
ꢁount and look ꢀor ILIM det puliei cn thci manner untcl
ecther:
Thci regcon ci alio aiioꢁcated wcth phaie ‘bump’ or reduꢁed
phaie ihcꢀt. The amount oꢀ phaie ihcꢀt reduꢁtcon dependi on
how wcde the regcon oꢀ flat gacn ci and hai a maxcmum value
oꢀ 90 degreei. To ꢀurther icmplcꢀy the ꢁonverter ꢁompenia-
tcon, the modulator gacn ci kept cndependent oꢀ the cnput
voltage varcatcon by provcdcng ꢀeed-ꢀorward oꢀ VIN to the
oiꢁcllator ramp.
The zero ꢀrequenꢁy, the amplcfier hcgh ꢀrequenꢁy gacn and
the modulator gacn are ꢁhoien to iatciꢀy moit typcꢁal applc-
ꢁatconi. The ꢁroiiover ꢀrequenꢁy wcll appear at the pocnt
where the modulator attenuatcon equali the amplcfier hcgh
ꢀrequenꢁy gacn. The only taik that the iyitem deicgner hai to
ꢁomplete ci to ipeꢁcꢀy the output filter ꢁapaꢁctori to poictcon
the load macn pole iomewhere wcthcn one deꢁade lower than
the amplcfier zero ꢀrequenꢁy. Wcth thci type oꢀ ꢁompeniatcon
plenty oꢀ phaie margcn ci eaicly aꢁhceved due to zero-pole
pacr phaie ‘booit’.
±. the IC ci ihut-down beꢁauie the tcmer tcmed out:
Iꢀ the tcmer pulie ci allowed to fincih by tcmcng out, the
IC ci ihut-down and ꢁan only be reitarted by removcng
power or togglcng the EN pcn.
2. ILIM det doei not go hcgh at leait onꢁe per 8 ꢁloꢁk
ꢁounti. In thci ꢁaie, the tcmer and over-ꢁurrent ihutdown
logcꢁ are reiet, and a ꢁhcp ihut-down ci averted.
PGOOD wcll go LOW cꢀ the IC ihuti down ꢀrom over-
ꢁurrent.
Condctconal itabclcty may oꢁꢁur only when the macn load
pole ci poictconed too muꢁh to the leꢀt icde on the ꢀrequenꢁy
axci due to exꢁeiicve output filter ꢁapaꢁctanꢁe. In thci ꢁaie,
the ESR zero plaꢁed wcthcn the ±0kHz...50kHz range gcvei
iome addctconal phaie ‘booit’. Fortunately, there ci an oppo-
icte trend cn mobcle applcꢁatconi to keep the output ꢁapaꢁctor
ai imall ai poiicble.
Setting the Current Limit
ISNS ci ꢁompared to the ꢁurrent eitablcihed when a 0.9 V
cnternal reꢀerenꢁe drcvei the ILIM pcn. The threihold ci
determcned at the pocnt when the
ILOAD • RDS(ON)
ISNS 0.9V
-------------- --------------
>
. Scnꢁe ISNS = -------------------------------------------
Protection
8
RILIM
RSENSE
The ꢁonverter output ci monctored and proteꢁted agacnit
ihort ꢁcrꢁuct (over-ꢁurrent), and over-voltage ꢁondctconi.
thereꢀore,
8 • (RSENSE
RDS(ON)
)
0.9V
ILIMIT
-------------- -----------------------------------
RILIM
=
×
(±±)
12
REV. 1.1.7 8/29/02
PRODUCT SPECIFICATION
FAN5240
Scnꢁe the toleranꢁe on the ꢁurrent lcmct ci largely dependent
on the ratco oꢀ the external reicitori ct ci ꢀacrly aꢁꢁurate cꢀ the
The over-ꢁurrent ꢁomparator ci iampled juit aꢀter LDRV ci
turned on, when the ꢁurrent ci near cti peak cn the ꢁyꢁle.
Aiiumcng 201 cnduꢁtor rcpple ꢁurrent, we ꢁan then add ±/2
oꢀ the rcpple ꢁurrent, or ±01. An addctconal ꢀaꢁtor oꢀ ±.2
aꢁꢁounti ꢀor the cnaꢁꢁuraꢁy cn the cnctcal (room temperature)
voltage drop on the Swctꢁhcng Node icde oꢀ R
SENSE
ci an
aꢁꢁurate repreientatcon oꢀ the load ꢁurrent. When uicng the
MOSFET ai the ienicng element, the varcatcon oꢀ R
DS(ON)
ꢁauiei proportconal varcatcon cn the ISNS. Thci value not
only varcei ꢀrom devcꢁe to devcꢁe, but alio hai a typcꢁal
junꢁtcon temperature ꢁoeꢀfiꢁcent oꢀ about 0.41 / °C (ꢁoniult
the MOSFET dataiheet ꢀor aꢁtual valuei), io the aꢁtual
ꢁurrent lcmct iet pocnt wcll deꢁreaie propotconal to cnꢁreaicng
MOSFET dce temperature. The iame dciꢁuiicon applcei to
R
oꢀ the MOSFETi wcth an addctconal ꢀaꢁtor oꢀ ±.4 to
DS(ON)
aꢁꢁommodate the rcie oꢀ the MOSFET R
DS(ON)
atcng wcth T @ ±25°C. Wcth a maxcmum load ꢁurrent oꢀ
±2.5A/phaie, the target ꢀor I
LIMIT
when oper-
J
(per phaie) would be:
20A
2
ILIMIT > 1.1 • 1.2 • 1.4 • 12.5A + ---------- ≈ 42A
(±2ꢁ)
the V
DROOP
ꢁalꢁulatcon.
io uicng equatcon ±±, wcth R
FDS6688 MOSFETi, R
ILIM
= 3mΩ ꢀor the 2 parallel
DS(ON)
≈ 56K:
Q2
LDRV
Over-Voltage Protection
RSENSE
ISNS
21
22
Should the output voltage exꢁeed 2.35V due to an upper
MOSFET ꢀaclure, or ꢀor other reaioni, the overvoltage
proteꢁtcon ꢁomparator wcll ꢀorꢁe the LDRV hcgh. Thci aꢁtcon
aꢁtcvely pulli down the output voltage and, cn the event oꢀ
the upper MOSFET ꢀaclure, wcll eventually blow the battery
ꢀuie. Ai ioon ai the output voltage dropi below the threih-
old, the OVP ꢁomparator ci dciengaged.
PGND
Figure 11. Improving current sensing accuracy
More aꢁꢁurate ienicng ꢁan be aꢁhceved by uicng a reicitor
(R±) cnitead oꢀ the R oꢀ the FET ai ihown cn Fcgure
Thci OVP iꢁheme provcdei a ‘ioꢀt’ ꢁrowbar ꢀunꢁtcon whcꢁh
helpi to taꢁkle ievere load tranicenti and doei not cnvert the
output voltage when aꢁtcvated — a ꢁommon problem ꢀor
OVP iꢁhemei wcth a latꢁh.
DS(ON)
±±. Thci approaꢁh ꢁauiei hcgher loiiei, but yceldi greater
aꢁꢁuraꢁy cn both V and I . R± ci a low value
DROOP LIMIT
(e.g. ±0mΩ) reicitor.
Over-Temperature Protection
The ꢁurrent lcmct (I ) iet pocnt ꢁhoien needi to aꢁꢁom-
LIMIT
The ꢁhcp cnꢁorporatei an over temperature proteꢁtcon ꢁcrꢁuct
that ihuti the ꢁhcp down when a dce temperature oꢀ ±50°C ci
reaꢁhed. Normal operatcon ci reitored at dce temperature
below ±25°C wcth cnternal Power On Reiet aiierted, reiult-
cng cn a ꢀull ioꢀt-itart ꢁyꢁle.
modate rcpple ꢁurrent, ilew ꢁurrent, and varcabclcty cn the
MOSFET'i R
.
DS(ON)
dV
-------
ILIMIT > ILOAD + C
(±2a)
OUT dt
dV
-------
Slew ꢁurrent ( C
) ci the ꢁurrent requcred ꢀor the
OUT dt
output voltage to ilew upwardi durcng VID ꢁode ꢁhangei,
icnꢁe the ꢁcrꢁuct wcll lcmct the regulator’i output ꢁurrent by
dV
-------
term we
pulie ikcppcng when I
LIMIT
ci reaꢁhed. The
dt
uied earlcer cn the dciꢁuiicon (iet up by the C ) wai
SS
oꢀ 4000µF, the
500mV/±00µS or 5V/mS. Aiiumcng C
OUT
at thci rate ci:
ꢁurrent requcred to ilew C
OUT
dV
-------
(±2b)
C
= 4mF • 5V/mS = 20A
OUT dt
whcꢁh ci ꢁontrcbuted roughly equally ꢀrom eaꢁh phaie,
thereꢀore, ±/2 oꢀ the ilew ꢁurrent ꢁomei ꢀrom a icngle phaie.
REV. 1.1.7 8/29/02
13
FAN5240
PRODUCT SPECIFICATION
The load tranicent requcrementi are a ꢀunꢁtcon oꢀ the ilew
rate (dc/dt) and the magnctude oꢀ the tranicent load ꢁurrent.
Modern mcꢁroproꢁeiiori produꢁe tranicent load ratei cn
exꢁeii oꢀ ±0A/µi. Hcgh ꢀrequenꢁy ꢁeramcꢁ ꢁapaꢁctori plaꢁed
beneath the proꢁeiior ioꢁket cnctcally iupply the tranicent
and reduꢁe the ilew rate ieen by the bulk ꢁapaꢁctori. The
bulk ꢁapaꢁctor valuei are generally determcned by the total
allowable ESR rather than aꢁtual ꢁapaꢁctanꢁe requcrementi.
Design and Component Selection
Guidelines
Ai an cnctcal itep, define operatcng voltage range and mcnc-
mum and maxcmum load ꢁurrenti ꢀor the ꢁontroller. For thci
dciꢁuiicon,
IOUT Max
VIN
25A
5.5 to 21 V
0.925 to 2 V
Hcgh ꢀrequenꢁy deꢁouplcng ꢁapaꢁctori ihould be plaꢁed ai
ꢁloie to the proꢁeiior power pcni ai phyicꢁally poiicble.
Coniult wcth the proꢁeiior manuꢀaꢁturer ꢀor ipeꢁcfiꢁ
deꢁouplcng requcrementi. Uie only ipeꢁcalczed low-ESR
eleꢁtrolytcꢁ ꢁapaꢁctori cntended ꢀor iwctꢁhcng-regulator
applcꢁatconi ꢀor the bulk ꢁapaꢁctori. The bulk ꢁapaꢁctor’i
ESR wcll determcne the output rcpple voltage and the cnctcal
voltage drop aꢀter a tranicent. In moit ꢁaiei, multcple eleꢁtro-
lytcꢁ ꢁapaꢁctori oꢀ imall ꢁaie icze perꢀorm better than a
icngle large ꢁaie ꢁapaꢁctor.
VOUT
Output Inductor Selection
The mcncmum praꢁtcꢁal output cnduꢁtor value ci the one that
keepi cnduꢁtor ꢁurrent juit on the boundary oꢀ ꢁontcnuoui
ꢁonduꢁtcon at iome mcncmum load. The cnduitry itandard
praꢁtcꢁe ci to ꢁhooie the rcpple ꢁurrent to be iomewhere ꢀrom
±51 to 351 oꢀ the nomcnal ꢁurrent. At lcght load, the rcpple
ꢁurrent alio determcnei the pocnt where the ꢁonverter wcll
automatcꢁally iwctꢁh to hyiteretcꢁ mode oꢀ operatcon (I
to iuitacn hcgh eꢀfiꢁcenꢁy. The ꢀollowcng equatconi help to
ꢁhooie the proper value oꢀ the output filter cnduꢁtor.
)
MIN
Input Capacitor Selection
The cnput ꢁapaꢁctor ihould be ieleꢁted by cti rcpple ꢁurrent
ratcng. For a 2 phaie ꢁonverter, the RMS ꢁurrenti ci ꢁalꢁu-
lated:
∆VOUT
ESR
,
∆I = 2 × IMIN = ------------------
IPK
IRMS
=
2D – 4D2
-------
(±4)
2
where ∆I ci the cnduꢁtor rcpple ꢁurrent, whcꢁh we wcll ꢁhooie
ꢀor 201 oꢀ the ꢀull load ꢁurrent (±2.5A cn eaꢁh phaie) and
∆V
OUT
ci the maxcmum output rcpple voltage allowed.
Thci equatcon produꢁei the worit ꢁaie value at maxcmum
duty ꢁyꢁle. For our example, that oꢁꢁuri when VIN = 5.5V
and VOUT = 2V. For 25A maxcmum output the maxcmum
V
IN – VOUT VOUT
(±3)
----------------------------- --------------
L =
×
FSW × ∆I
VIN
RMS ꢁurrent at C
:
IN
IRMS(MAX) = 5.6A
ꢀor thci example we’ll uie:
V
= 20V, V = ±.5V
OUT
Power MOSFET Selection
For the example cn the ꢀollowcng dciꢁuiicon, we wcll be
ieleꢁtcng ꢁomponenti ꢀor:
IN
∆I = 201 *±2.5A (per phaie) = 2.5A
= 300KHz.
F
SW
Thereꢀore,
L ≈ ±.8µH
VIN ꢀrom 5V to 20V
V
OUT
= ±.5V @ I = ±2.5A/phaie
LOAD(MAX)
The cnduꢁtor'i ꢁurrent ratcng ihould be ꢁhoien per the
The FAN5240 ꢁonverter’i output voltage ci very low wcth
reipeꢁt to the cnput voltage, thereꢀore the Lower MOSFET
(Q2) ci ꢁonduꢁtcng the ꢀull load ꢁurrent ꢀor moit oꢀ the ꢁyꢁle.
Thereꢀore, Q2 ihould be ieleꢁted to be a MOSFET wcth low
I
ꢁalꢁulated above. Some tranicent ꢁurrenti over the
LIMIT
cnduꢁtor ꢁurrent ratcng may be tolerable cꢀ the cnduꢁtor’i
dL
dI
------
iaturatcon ꢁharaꢁtercitcꢁ
ci iuꢀfiꢁcently “ioꢀt”.
R
to mcncmcze ꢁonduꢁtcon loiiei.
DS(ON)
Output Capacitor Selection
In ꢁontrait, Q± ci on ꢀor a maxcmum oꢀ 201 (when VIN =
5V) oꢀ the ꢁyꢁle, and cti ꢁonduꢁtcon loii wcll have leii oꢀ an
cmpaꢁt. Q±, however, ieei moit oꢀ the iwctꢁhcng loiiei, io
Q±’i prcmary ieleꢁtcon ꢁrcterca ihould be gate ꢁharge
The output ꢁapaꢁctor iervei two major ꢀunꢁtconi cn a iwctꢁh-
cng power iupply. Along wcth the cnduꢁtor ct filteri the
iequenꢁe oꢀ puliei produꢁed by the iwctꢁher, and ct iupplcei
the load tranicent ꢁurrenti. The filtercng requcrementi are a
ꢀunꢁtcon oꢀ the iwctꢁhcng ꢀrequenꢁy and the rcpple ꢁurrent
allowed, and are uiually eaiy to iatciꢀy cn hcgh ꢀrequenꢁy
ꢁonverteri.
(Q
).
G(SW)
14
REV. 1.1.7 8/29/02
PRODUCT SPECIFICATION
FAN5240
moit oꢀ t oꢁꢁuri when V = V we ꢁan uie a ꢁonitant
GS SP
ꢁurrent aiiumptcon ꢀor the drcver to icmplcꢀy the ꢁalꢁulatcon
oꢀ t :
S
High-Side Losses:
S
CISS
CRSS
CISS
VDS
QG(SW)
IDRIVER
QG(SW)
-------------------- -----------------------------------------------------
tS
=
≈
(±6)
VDD – VSP
------------------------------------------------
DRIVER + RGATE
R
For the hcgh-icde MOSFET, V = VIN, whcꢁh ꢁan be ai
DS
hcgh ai 20V cn a typcꢁal portable applcꢁatcon. Q2, however,
iwctꢁhei on or oꢀꢀ wcth cti parallel ihottky dcode ꢁonduꢁtcng,
ID
thereꢀore V ≈ 0.5V. Scnꢁe P
DS SW
ci proportconal to V ,
DS
Q2'i iwctꢁhcng loiiei are neglcgcble and we ꢁan ieleꢁt Q2
baied on R only.
QGS
QGD
VGS
DS(ON)
4.5V
VSP
VTH
Care ihould alio be taken to cnꢁlude the delcvery oꢀ the
MOSFET'i gate power ( P ) cn ꢁalꢁulatcng the power
QG(SW)
GATE
dciicpatcon requcred ꢀor the FAN5240:
t1
CISS = CGS || CGD
t2
t3
t4
t5
PGATE = QG × VDD × FSW
(±7)
Low-Side Losses
Figure 12. Switching losses and Q
G
Conduꢁtcon loiiei ꢀor Q2 are gcven by:
VIN
5V
PCOND = (1 – D) × IOUT2 × RDS(ON)
(±8)
CGD
RD
RGATE
HDRV
SW
19
20
G
where R
DS(ON)
ci the R
DS(ON)
oꢀ the MOSFET at the
CGS
VOUT
hcgheit operatcng junꢁtcon temperature and D = -------------- ci
VIN
the mcncmum duty ꢁyꢁle ꢀor the ꢁonverter. Scnꢁe D
ci 51
MIN
ꢀor portable ꢁomputeri, (±-D) ≈ ±, ꢀurther icmplcꢀycng the
ꢁalꢁulatcon.
Figure 13. Drive Equivalent Circuit
Aiiumcng iwctꢁhcng loiiei are about the iame ꢀor both the
rcicng edge and ꢀallcng edge, Q±’i iwctꢁhcng loiiei, ai ꢁan be
ieen by Fcgure ±2, are gcven by:
The maxcmum power dciicpatcon (P
) ci a ꢀunꢁtcon oꢀ
the maxcmum allowable dce temperature oꢀ the low-icde
D(MAX)
MOSFET, the θ , and the maxcmum allowable ambcent
J-A
temperature rcie:
PUPPER = PSW + PCOND
(±5a)
(±5b)
VDS × IL
T
J(MAX) – TA(MAX)
---------------------
PSW
=
× 2 × tS FSW
PD(MAX) = ------------------------------------------------
2
θJ – A
VOUT
PCOND
=
× IOUT2 × RDS(ON)
(±5ꢁ)
--------------
θ
, dependi prcmarcly on the amount oꢀ PCB area that ꢁan
J-A
VIN
be devoted to heat icnkcng (iee FSC app note AN-±029 ꢀor
SO-8 MOSFET thermal cnꢀormatcon).
where R
ci @T and:
J(MAX)
DS(ON)
t ci the iwctꢁhcng percod (rcie or ꢀall tcme) and ci predomc-
S
nantly the ium oꢀ t2, t3 (Fcgure ±2), a ꢀunꢁtcon oꢀ the cmped-
anꢁe oꢀ the drcver and the Q
oꢀ the MOSFET. Scnꢁe
G(SW)
REV. 1.1.7 8/29/02
15
FAN5240
PRODUCT SPECIFICATION
Keep the wcrcng traꢁei ꢀrom the IC to the MOSFET gate and
iourꢁe ai ihort ai poiicble and ꢁapable oꢀ handlcng peak ꢁur-
renti oꢀ 2A. Mcncmcze the area wcthcn the gate-iourꢁe path to
reduꢁe itray cnduꢁtanꢁe and elcmcnate paraictcꢁ rcngcng at the
gate.
Layout Considerations
Swctꢁhcng ꢁonverteri, even durcng normal operatcon,
produꢁe ihort puliei oꢀ ꢁurrent whcꢁh ꢁould ꢁauie iubitan-
tcal rcngcng and be a iourꢁe oꢀ EMI cꢀ layout ꢁonitracni are
not obierved.
Loꢁate imall ꢁrctcꢁal ꢁomponenti lcke the ioꢀt-itart ꢁapaꢁctor
and ꢁurrent ienie reicitori ai ꢁloie ai poiicble to the reipeꢁ-
tcve pcni oꢀ the IC.
There are two ieti oꢀ ꢁrctcꢁal ꢁomponenti cn a DC-DC
ꢁonverter. The iwctꢁhcng power ꢁomponenti proꢁeii large
amounti oꢀ energy at hcgh rate and are nocie generatori.
The low power ꢁomponenti reiponicble ꢀor bcai and ꢀeed-
baꢁk ꢀunꢁtconi are ienictcve to nocie.
The FAN5240 utclczei advanꢁed paꢁkagcng teꢁhnology that
wcll have lead pctꢁh oꢀ 0.6mm. Hcgh perꢀormanꢁe analog
iemcꢁonduꢁtori utclczcng narrow lead ipaꢁcng may requcre
ipeꢁcal ꢁonicderatconi cn PWB deicgn and manuꢀaꢁturcng. It
ci ꢁrctcꢁal to macntacn proper ꢁleanlcneii oꢀ the area iur-
roundcng theie devcꢁei. It ci not reꢁommended to uie any
type oꢀ roicn or aꢁcd ꢁore iolder, or the uie oꢀ flux cn ecther
the manuꢀaꢁturcng or touꢁh up proꢁeii ai theie may ꢁontrcb-
ute to ꢁorroicon or enable eleꢁtromcgratcon and/or eddy ꢁur-
renti near the ienictcve low ꢁurrent icgnali. When ꢁhemcꢁali
iuꢁh ai theie are uied on or near the PWB, ct ci iuggeited
that the entcre PWB be ꢁleaned and drced ꢁompletely beꢀore
applycng power.
A multc-layer prcnted ꢁcrꢁuct board ci reꢁommended.
Dedcꢁate one iolcd layer ꢀor a ground plane. Dedcꢁate
another iolcd layer ai a power plane and break thci plane
cnto imaller cilandi oꢀ ꢁommon voltage leveli.
Notcꢁe all the nodei that are iubjeꢁted to hcgh dV/dt voltage
iwcng iuꢁh ai SW, HDRV and LDRV, ꢀor example. All iur-
roundcng ꢁcrꢁuctry wcll tend to ꢁouple the icgnali ꢀrom theie
nodei through itray ꢁapaꢁctanꢁe. Do not overicze ꢁopper
traꢁei ꢁonneꢁted to theie nodei. Do not plaꢁe traꢁei ꢁon-
neꢁted to the ꢀeedbaꢁk ꢁomponenti adjaꢁent to theie traꢁei.
It ci not reꢁommended to uie Hcgh Denicty Interꢁonneꢁt
Syitemi, or mcꢁro-vcai on theie icgnali. The uie oꢀ blcnd or
burced vcai ihould be lcmcted to the low ꢁurrent icgnali only.
The uie oꢀ normal thermal vcai ci leꢀt to the dciꢁretcon oꢀ the
deicgner.
16
REV. 1.1.7 8/29/02
PRODUCT SPECIFICATION
FAN5240
Mechanical Dimensions
28-Pin QSOP
Notes:
Inches
Millimeters
Symbol
Notes
1. Symbols are defined in the "MO Series Symbol List" in
Section 2.2 of Publication Number 95.
Min.
Max.
Min.
Max.
A
0.053
0.004
-
0.069
0.010
0.061
0.012
0.010
0.394
0.157
1.35
0.10
-
1.75
0.25
1.54
0.30
0.25
10.00
3.98
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
A1
A2
B
3. Dimension "D" does not include mold flash, protrusions
or gate burrs. Mold flash, protrusions shall not exceed
0.25mm (0.010 inch) per side.
0.008
0.007
0.386
0.150
0.20
0.18
9.81
3.81
9
4. Dimension "E" does not include interlead flash or
protrusions. Interlead flash and protrusions shall not
exceed 0.25mm (0.010 inch) per side.
C
D
E
3
4
5. The chamber on the body is optional. If it is not present,
a visual index feature must be located within the
crosshatched area.
e
0.025 BSC
0.635 BSC
H
h
0.228
0.244
5.80
0.26
0.41
6.19
0.49
1.27
0.0099 0.0196
5
6
7
6. "L" is the length of terminal for soldering to a substrate.
7. "N" is the maximum number of terminals.
0.016
0.050
L
N
α
28
28
8. Terminal numbers are shown for reference only.
0°
8°
0°
8°
9. Dimension "B" does not include dambar protrusion.
Allowable dambar protrusion shall be 0.10mm (0.004
inch) total in excess of "B" dimension at maximum
material condition.
10. Controlling dimension: INCHES. Converted millimeter
dimensions are not necessarily exact.
D
E
H
C
A1
A
A2
α
SEATING
PLANE
– C –
L
B
LEAD COPLANARITY
ccc C
e
REV. 1.1.7 8/29/02
17
FAN5240
PRODUCT SPECIFICATION
Mechanical Dimensions
28-Pin TSSOP
9.7 0.1
0.51 TYP
28
15
– B –
0.2
B A
0.65
0.42
14
ALL Lead Tips
PIN # 1 IDENT
LAND PATTERN RECOMMENDATION
1.2 MAX
0.1 C
ALL LEAD TIPS
+0.15
–0.10
0.90
See Detail A
0.09–0.20
– C –
0.10 0.05
A B C
0.65
0.19–0.30
0.13
12.00° Top & Botom
R0.16
R0.31
GAGE PLANE
.025
DIMENSIONS ARE IN MILLIMETERS
0°–8°
0.61 0.1
NOTES:
SEATING PLANE
A. Conforms to JEDEC registration MO-153, variation AB,
Ref. Note 6, dated 7/93.
1.00
B. Dimensions are in millimeters.
C. Dimensions are exclusive of burrs, mold flash, and tie bar extensions.
D Dimensions and Tolerances per ANsI Y14.5M, 1982
DETAIL A
18
REV. 1.1.7 8/29/02
FAN5240
PRODUCT SPECIFICATION
Ordering Information
Part Number
FAN5240QSC
FAN5240QSCX
FAN5240MTC
FAN5240MTCX
Temperature Range
-10°C to 85°C
Package
QSOP-28
QSOP-28
TSSOP-28
TSSOP-28
Packing
Rails
-10°C to 85°C
Tape and Reel
Rails
-10°C to 85°C
-10°C to 85°C
Tape and Reel
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO
ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME
ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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8/29/02 0.0m 003
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2002 Fairchild Semiconductor Corporation
相关型号：
FAN5307MP18X_NL
Switching Regulator, Current-mode, 0.7A, 1200kHz Switching Freq-Max, 3 X 3 MM, LEAD FREE, MO-229WEEA, MLP-6
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