FAN5400_11 [FAIRCHILD]
FAN5400 / FAN5401 / FAN5402 / FAN5403 / FAN5404 / FAN5405 USB-Compliant Single-Cell Li-Ion Switching Charger; FAN5400 / FAN5401 / FAN5402 / FAN5403 / FAN5404 / FAN5405 USB兼容的单节锂离子电池开关充电器型号: | FAN5400_11 |
厂家: | FAIRCHILD SEMICONDUCTOR |
描述: | FAN5400 / FAN5401 / FAN5402 / FAN5403 / FAN5404 / FAN5405 USB-Compliant Single-Cell Li-Ion Switching Charger |
文件: | 总37页 (文件大小:1011K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
September 2011
FAN5400/FAN5401/FAN5402/FAN5403/FAN5404/FAN5405
USB-Compliant Single-Cell Li-Ion Switching Charger with
USB-OTG Boost Regulator
Features
Description
The FAN5400 family (FAN540X) combines a highly integrated
switch-mode charger, to minimize single-cell Lithium-ion
(Li-ion) charging time from a USB power source, and a boost
regulator to power a USB peripheral from the battery.
.
Fully Integrated, High-Efficiency Charger for Single-Cell
Li-Ion and Li-Polymer Battery Packs
.
.
Faster Charging than Linear
Charge Voltage Accuracy:
0.5% at 25°C
1% from 0 to 125°C
The charging parameters and operating modes are
programmable through an I2C Interface that operates up to
3.4Mbps. The charger and boost regulator circuits switch at
3MHz to minimize the size of external passive components.
.
.
.
.
.
.
5% Input Current Regulation Accuracy
5% Charge Current Regulation Accuracy
20V Absolute Maximum Input Voltage
6V Maximum Input Operating Voltage
1.25A Maximum Charge Rate
The FAN540X provides battery charging in three phases:
conditioning, constant current, and constant voltage.
To ensure USB compliance and minimize charging time, the
input current is limited to the value set through the I2C host.
Charge termination is determined by a programmable
minimum current level. A safety timer with reset control
provides a safety backup for the I2C host.
Programmable through High-Speed I2C Interface
(3.4Mb/s) with Fast Mode Plus Compatibility
–
–
–
–
Input Current
The integrated circuit (IC) automatically restarts the charge
cycle when the battery falls below an internal threshold. If the
input source is removed, the IC enters a high-impedance
mode with leakage from the battery to the input prevented.
Charge status is reported back to the host through the I2C
port. Charge current is reduced when the die temperature
reaches 120°C.
Fast-Charge / Termination Current
Charger Voltage
Termination Enable
.
3MHz Synchronous Buck PWM Controller with Wide
Duty Cycle Range
The FAN540X can operate as a boost regulator on
command from the system. The boost regulator includes a
soft-start that limits inrush current from the battery.
.
.
.
.
Small Footprint 1H External Inductor
Safety Timer with Reset Control
The FAN540X is available in a 1.96 x 1.87mm, 20-bump,
0.4mm pitch WLCSP package.
1.8V Regulated Output from VBUS for Auxiliary Circuits
Weak Input Sources Accommodated by Reducing
Charging Current to Maintain Minimum VBUS Voltage
1H
L1
VBUS
1F
SW
.
.
Low Reverse Leakage to Prevent Battery Drain to VBUS
RSENSE
CBUS
0.1F
COUT
5V, 300mA Boost Mode for USB OTG for 2.5 to 4.5V
Battery Input
PGND
CSIN
68m
PMID
4.7F
Battery
+
CMID
FAN540X
VBAT
SDA
SCL
Applications
CBAT
10F
SYSTEM
LOAD
.
.
.
Cell Phones, Smart Phones, PDAs
Tablet, Portable Media Players
Gaming Device, Digital Cameras
DISABLE
VREG
CREG
OTG/USB#
STAT
1F
Figure 1. Typical Application (FAN5403-05 Pin Out)
All trademarks are the property of their respective owners.
© 2009 Fairchild Semiconductor Corporation
FAN5400 Family • Rev. 1.0.7
www.fairchildsemi.com
Ordering Information
Part Number
FAN5400UCX
FAN5401UCX
FAN5402UCX
FAN5403UCX
FAN5404UCX
FAN5405UCX
Temperature Range
Package
PN Bits: IC_INFO[4:3]
Packing Method
Tape and Reel
Tape and Reel
Tape and Reel
Tape and Reel
Tape and Reel
Tape and Reel
-40 to 85°C
-40 to 85°C
-40 to 85°C
-40 to 85°C
-40 to 85°C
-40 to 85°C
01
00
01
10
11
10
20- Bump, Wafer-
Level Chip-Scale
Package (WLCSP),
0.4mm Pitch,
Estimated Size: 1.96
x 1.87mm
Table 1. Feature Comparison Summary
Battery
Absent
Behavior
Part
Number
Slave
Address
Automatic
Charge
Special
Safety
VREG
(E3 Pin)
PN Bits:
REG3[4:3]
E2 Pin
Charger(1) Limits
FAN5400
FAN5401
FAN5402
FAN5403
FAN5404
FAN5405
Note:
01
00
01
10
11
10
1101011
1101011
1101011
1101011
1101011
1101010
Yes
No
No
No
No
No
OFF
OFF
ON
AUXPWR
(Connect to
VBAT)
PMID
Yes
Yes
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
OFF
OFF
ON
DISABLE
1.8V
Yes
1. Special charger is a current limited charger that is not a USB compliant source.
Table 2. Recommended External Components
Component
Description
Vendor
Parameter
Typ.
1.0
Unit
H
L
Murata: LQM2MPN1R0M
or Equivalent
L1
1H, 20%, 1.3A, 2016
DCR (Series R)
85
m
Murata: GRM188R60J106M
TDK: C1608X5R0J106M
CBAT
CMID
C
C(2)
C
10
4.7
1.0
10F, 20%, 6.3V, X5R, 0603
4.7F, 10%, 6.3V, X5R, 0603
1.0F, 10%, 25V, X5R, 0603
F
F
F
Murata: GRM188R60J475K
TDK: C1608X5R0J475K
Murata GRM188R61E105K
TDK:C1608X5R1E105M
CBUS
Note:
2. 6.3V rating is sufficient for CMID since PMID is protected from over-voltage surges on VBUS by Q3 (Figure 3).
© 2009 Fairchild Semiconductor Corporation
FAN5400 Family • Rev. 1.0.7
www.fairchildsemi.com
2
Block Diagram
Figure 2. IC and System Block Diagram
VBUS
CIN1
PMID
Q3
CIN2
CHARGE
PUMP
Q1
Q1A
Q1B
CSIN
SW
L1
PMID
Q1A Q1B
OFF
OFF ON
Q2
1H
Greater than VBAT ON
Less than VBAT
RSENSE
68m
COUT
PGND
VBAT
Battery
+
CBAT
SYSTEM
LOAD
Figure 3. Power Stage
© 2009 Fairchild Semiconductor Corporation
FAN5400 Family • Rev. 1.0.7
www.fairchildsemi.com
3
Pin Configuration
A1
A2
B2
C2
D2
E2
A3
B3
C3
D3
E3
A4
B4
C4
D4
E4
A4
B4
C4
D4
E4
A3
B3
C3
D3
E3
A2
B2
C2
D2
E2
A1
B1
C1
D1
E1
B1
C1
D1
E1
Top View
Bottom View
Figure 4. WLCSP-20 Pin Assignments
Pin Definitions
Pin #
Name
Part # Description
Charger Input Voltage and USB-OTG output voltage. Bypass with a 1F capacitor to
PGND.
A1, A2
VBUS
ALL
No Connect. No external connection is made between this pin and the IC’s internal
circuitry.
I2C Interface Serial Clock. This pin should not be left floating.
A3
A4
NC
ALL
ALL
SCL
Power Input Voltage. Power input to the charger regulator, bypass point for the input
current sense, and high-voltage input switch. Bypass with a minimum of 4.7F, 6.3V
capacitor to PGND.
B1-B3
PMID
ALL
B4
SDA
SW
ALL
ALL
I2C Interface Serial Data. This pin should not be left floating.
C1-C3
Switching Node. Connect to output inductor.
Status. Open-drain output indicating charge status. The IC pulls this pin LOW when charge
is in process.
C4
STAT
ALL
ALL
Power Ground. Power return for gate drive and power transistors. The connection from this
pin to the bottom of CMID should be as short as possible.
D1-D3
PGND
On-The-Go. Enables boost regulator in conjunction with OTG_EN and OTG_PL bits (see
Table 16). On VBUS Power-On Reset (POR), this pin sets the input current limit for t15MIN
charging.
D4
E1
E2
OTG
CSIN
ALL
Current-Sense Input. Connect to the sense resistor in series with the battery. The IC uses
this node to sense current into the battery. Bypass this pin with a 0.1F capacitor to PGND.
ALL
FAN5400,
Auxiliary Power. Connect to the battery pack to provide IC power during High-Impedance
Mode. Bypass with a 1F capacitor to PGND.
AUXPWR FAN5401,
FAN5402
FAN5403, Charge Disable. If this pin is HIGH, charging is disabled. When LOW, charging is
DISABLE FAN5404, controlled by the I2C registers. When this pin is HIGH, the 15-minute timer is reset. This pin
FAN5405 does not affect the 32-second timer.
E2
Regulator Output. Connect to a 1F capacitor to PGND. This pin can supply up to 2mA of
DC load current. For FAN5400-FAN5402, the output voltage is PMID, which is limited to
6.5V. For FAN5403-FAN5405, the output voltage is regulated to 1.8V.
E3
E4
VREG
VBAT
ALL
ALL
Battery Voltage. Connect to the positive (+) terminal of the battery pack. Bypass with a
0.1F capacitor to PGND if the battery is connected through long leads.
© 2009 Fairchild Semiconductor Corporation
FAN5400 Family • Rev. 1.0.7
www.fairchildsemi.com
4
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above
the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended
exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum
ratings are stress ratings only.
Symbol
VBUS
VSTAT
VI
Parameter
Min.
–1.4
–2.0
–0.3
Max.
Unit
V
Continuous
VBUS Voltage
20.0
Pulsed, 100ms Maximum Non-Repetitive
STAT Voltage
PMID Voltage
16.0
7.0
V
V
SW, CSIN, VBAT, AUXPWR, DISABLE Voltage
Voltage on Other Pins
–0.3
–0.3
7.0
6.5(3)
VO
V
dVBUS
dt
Maximum VBUS Slope above 5.5V when Boost or Charger are Active
4
V/s
Human Body Model per JESD22-A114
Charged Device Model per JESD22-C101
2000
500
Electrostatic Discharge
Protection Level
ESD
V
TJ
TSTG
TL
Junction Temperature
Storage Temperature
–40
–65
+150
+150
+260
°C
°C
°C
Lead Soldering Temperature, 10 Seconds
Note:
3. Lesser of 6.5V or VI + 0.3V.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating
conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend
exceeding them or designing to absolute maximum ratings.
Symbol
Parameter
Min.
Max.
6
Units
VBUS
Supply Voltage
4
V
V
VBAT(MAX) Maximum Battery Voltage when Boost enabled
4.5
4
TA < 60°C
TA > 60°C
dVBUS
dt
Negative VBUS Slew Rate during VBUS Short Circuit,
CMID < 4.7F, see VBUS Short While Charging
V/s
2
TA
TJ
Ambient Temperature
–30
–30
+85
+120
°C
°C
Junction Temperature (see Thermal Regulation and Protection section)
Thermal Properties
Junction-to-ambient thermal resistance is a function of application and board layout. This data is measured with four-layer
2s2p boards in accordance to JEDEC standard JESD51. Special attention must be paid not to exceed junction temperature
TJ(max) at a given ambient temperature TA. For measured data, see Table 11.
Symbol Parameter
Typical
60
Units
°C/W
°C/W
Junction-to-Ambient Thermal Resistance
Junction-to-PCB Thermal Resistance
JA
JB
20
© 2009 Fairchild Semiconductor Corporation
FAN5400 Family • Rev. 1.0.7
www.fairchildsemi.com
5
Electrical Specifications
Unless otherwise specified: according to the circuit of Figure 1; recommended operating temperature range for TJ and TA;
VBUS=5.0V; HZ_MODE; OPA_MODE=0; (Charge Mode); SCL, SDA, OTG=0 or 1.8V; and typical values are for TJ=25°C.
Symbol
Parameter
Conditions
Min. Typ. Max. Units
Power Supplies
VBUS > VBUS(min), PWM Switching
10
mA
mA
VBUS > VBUS(min); PWM Enabled,
Not Switching (Battery OVP
Condition); I_IN Setting=100mA
2.5
IVBUS
VBUS Current
0°C < TJ < 85°C, HZ_MODE=1
63
90
5.0
20
10
A
A
V
BAT < VLOWV, 32S Mode
0°C < TJ < 85°C, HZ_MODE=1,
BAT=4.2V, VBUS=0V
0°C < TJ < 85°C, HZ_MODE=1,
BAT=4.2V
ILKG
VBAT to VBUS Leakage Current
0.2
V
V
Battery Discharge Current in High-
Impedance Mode
IBAT
A
FAN5403-05, DISABLE=1,
0°C < TJ < 85°C, VBAT=4.2V
Charger Voltage Regulation
Charge Voltage Range
3.5
–0.5%
–1%
4.4
VOREG
TA=25°C
+0.5%
+1%
V
Charge Voltage Accuracy
Charging Current Regulation
Output Charge Current Range
TJ=0 to 125°C
VLOWV < VBAT < VOREG
550
1250
mA
%
VBUS > VSLP, RSENSE=68m
FAN5400-02
FAN5403-05
FAN5400-02
FAN5403-05
95
92
97
94
100
97
105
102
103
100
20mV < VIREG
40mV
<
IOCHRG
Charge Current Accuracy Across
RSENSE
100
97
VIREG > 40mV
Weak Battery Detection
Weak Battery Threshold Range
3.4
–5
3.7
+5
V
%
VLOWV
Weak Battery Threshold Accuracy
Weak Battery Deglitch Time
Rising Voltage, 2mV Overdrive
30
ms
Logic Levels: DISABLE, SDA, SCL, OTG
VIH
VIL
IIN
High-Level Input Voltage
Low-Level Input Voltage
Input Bias Current
1.05
V
V
0.4
Input Tied to GND or VIN
0.01
1.00
A
Charge Termination Detection
VBAT > VOREG – VRCH, VBUS > VSLP
,
Termination Current Range
50
400
mA
RSENSE=68m
[VCSIN – VBAT] from 3mV to 20mV
–25
–5
+25
+5
I(TERM)
Termination Current Accuracy
%
[VCSIN – VBAT] from 20mV to 40mV
2mV Overdrive
Termination Current Deglitch Time
30
ms
1.8V Linear Regulator
VREG
1.8V Regulator Output
IREG from 0 to 2mA, FAN5403-05
1.7
1.8
1.9
V
Continued on the following page…
© 2009 Fairchild Semiconductor Corporation
FAN5400 Family • Rev. 1.0.7
www.fairchildsemi.com
6
Electrical Specifications
Unless otherwise specified: according to the circuit of Figure 1; recommended operating temperature range for TJ and TA;
VBUS=5.0V; HZ_MODE; OPA_MODE=0; (Charge Mode); SCL, SDA, OTG=0 or 1.8V; and typical values are for TJ=25°C.
Symbol
Parameter
Conditions
Min. Typ. Max. Units
Input Power Source Detection
VIN(MIN)1 VBUS Input Voltage Rising
VIN(MIN)2 Minimum VBUS during Charge
To Initiate and Pass VBUS Validation
During Charging
4.29
3.71
30
4.42
3.94
V
V
tVBUS_VALID VBUS Validation Time
ms
Special Charger (VBUS) (FAN5403 – FAN5405)
–3
+3
%
VSP
Special Charger Setpoint Accuracy
Input Current Limit
IIN Set to 100mA
IIN Set to 500mA
88
93
98
IINLIM
Input Current Limit Threshold
mA
450
475
500
VREF Bias Generator
Bias Regulator Voltage
Short-Circuit Current Limit
V
BUS > VIN(MIN) or VBAT > VBAT(MIN)
6.5
V
VREF
20
mA
Battery Recharge Threshold
Recharge Threshold
Below V(OREG)
100
120
130
150
mV
VRCH
Deglitch Time
VBAT Falling Below VRCH Threshold
ms
STAT Output
VSTAT(OL)
ISTAT(OH)
STAT Output Low
ISTAT=10mA
VSTAT=5V
0.4
1
V
STAT High Leakage Current
A
Battery Detection
Battery Detection Current before
IDETECT
tDETECT
–0.80
262
mA
ms
Charge Done (Sink Current)(4)
Battery Detection Time
Begins after Termination Detected
and VBAT < VOREG –VRCH
Sleep Comparator
Sleep-Mode Entry Threshold,
BUS – VBAT
VSLP
2.3V < VBAT < VOREG, VBUS Falling
Rising Voltage
0
0.04
30
0.10
V
V
Deglitch Time for VBUS Rising
Above VSLP + VSLP_EXIT
VSLP_EXIT
ms
Power Switches (see Figure 3)
Q3 On Resistance (VBUS to PMID) IIN(LIMIT)=500mA
180
130
150
250
225
225
RDS(ON)
Q1 On Resistance (PMID to SW)
Q2 On Resistance (SW to GND)
mΩ
Charger PWM Modulator
fSW
Oscillator Frequency
2.7
3.0
3.3
MHz
%
DMAX
DMIN
Maximum Duty Cycle
Minimum Duty Cycle
100
0
%
Synchronous to Non-Synchronous
Current Cut-Off Threshold(5)
Low-Side MOSFET (Q2) Cycle-by-
Cycle Current Limit
ISYNC
140
mA
Continued on the following page…
© 2009 Fairchild Semiconductor Corporation
FAN5400 Family • Rev. 1.0.7
www.fairchildsemi.com
7
Electrical Specifications
Unless otherwise specified: according to the circuit of Figure 1; recommended operating temperature range for TJ and TA;
VBUS=5.0V; HZ_MODE; OPA_MODE=0; (Charge Mode); SCL, SDA, OTG=0 or 1.8V; and typical values are for TJ=25°C.
Symbol
Parameter
Conditions
Min. Typ. Max. Units
Boost Mode Operation (OPA_MODE=1, HZ_MODE=0)
2.5V < VBAT < 4.5V, ILOAD from 0 to
200mA
4.80
4.85
5.07
5.07
5.17
5.17
VBOOST
Boost Output Voltage at VBUS
V
2.7V < VBAT < 4.5V, ILOAD from 0 to
200mA
IBAT(BOOST) Boost Mode Quiescent Current
PFM Mode, VBAT=3.6V, IOUT=0
140
1380
2.42
2.58
300
A
ILIMPK(BST)
Q2 Peak Current Limit
1100
1660
mA
While Boost Active
Minimum Battery Voltage for Boost
Operation
UVLOBST
V
To Start Boost Regulator
2.70
6.49
VBUS Load Resistance
Normal Operation
Charger Validation
1500
100
K
RVBUS
VBUS to PGND Resistance
Protection and Timers
VBUS Over-Voltage Shutdown
V
BUS Rising
6.09
6.29
100
V
VBUSOVP
ILIMPK(CHG)
VSHORT
ISHORT
Hysteresis
VBUS Falling
mV
Q1 Cycle-by-Cycle Peak Current
Limit
Charge Mode
2.3
A
Battery Short-Circuit Threshold
Hysteresis
VBAT Rising
1.95
20
2.00
100
30
2.05
40
V
VBAT Falling
Linear Charging Current
Thermal Shutdown Threshold(6)
Hysteresis(6)
VBAT < VSHORT
mA
°C
TJ Rising
145
10
TSHUTDWN
TJ Falling
TCF
tINT
Thermal Regulation Threshold(6)
Charge Current Reduction Begins
120
2.1
°C
s
Detection Interval
Charger Enabled
Charger Disabled
20.5
18.0
25.2
25.2
28.0
34.0
t32S
32-Second Timer(7)
s
15-Minute Mode (FAN5400,
FAN5402, FAN5404, FAN5405)
t15MIN
15-Minute Timer
12.0
–25
13.5
15.0
25
min
%
∆tLF
Low-Frequency Timer Accuracy
Charger Inactive
Notes:
4. Negative current is current flowing from the battery to VBUS (discharging the battery).
5. Q2 always turns on for 60ns, then turns off if current is below ISYNC
.
6. Guaranteed by design; not tested in production.
7. This tolerance (%) applies to all timers on the IC, including soft-start and deglitching timers.
© 2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN5400 Family • Rev. 1.0.7
8
I2C Timing Specifications
Guaranteed by design.
Symbol
Parameter
Conditions
Min. Typ. Max. Units
Standard Mode
Fast Mode
100
400
kHz
fSCL
SCL Clock Frequency
High-Speed Mode, CB < 100pF
High-Speed Mode, CB < 400pF
Standard Mode
3400
1700
4.7
Bus-Free Time between STOP
and START Conditions
tBUF
s
Fast Mode
1.3
Standard Mode
4
s
ns
ns
s
s
ns
ns
s
ns
ns
ns
s
ns
ns
START or Repeated START
Hold Time
tHD;STA
Fast Mode
600
160
4.7
1.3
160
320
4
High-Speed Mode
Standard Mode
Fast Mode
tLOW
SCL LOW Period
SCL HIGH Period
High-Speed Mode, CB < 100pF
High-Speed Mode, CB < 400pF
Standard Mode
Fast Mode
600
60
tHIGH
High-Speed Mode, CB < 100pF
High-Speed Mode, CB < 400pF
Standard Mode
120
4.7
600
160
250
100
10
tSU;STA
Repeated START Setup Time
Data Setup Time
Fast Mode
High-Speed Mode
Standard Mode
tSU;DAT
Fast Mode
ns
High-Speed Mode
Standard Mode
0
0
0
0
3.45
900
70
s
ns
ns
ns
Fast Mode
tHD;DAT
Data Hold Time
SCL Rise Time
SCL Fall Time
High-Speed Mode, CB < 100pF
High-Speed Mode, CB < 400pF
Standard Mode
150
1000
300
80
20+0.1CB
20+0.1CB
10
Fast Mode
tRCL
ns
ns
ns
High-Speed Mode, CB < 100pF
High-Speed Mode, CB < 400pF
Standard Mode
20
160
300
300
40
20+0.1CB
20+0.1CB
10
Fast Mode
tFCL
High-Speed Mode, CB < 100pF
High-Speed Mode, CB < 400pF
Standard Mode
20
80
20+0.1CB
20+0.1CB
10
1000
300
80
SDA Rise Time
Fast Mode
tRDA
Rise Time of SCL after a
Repeated START Condition
and after ACK Bit
tRCL1
High-Speed Mode, CB < 100pF
High-Speed Mode, CB < 400pF
20
160
Continued on the following page…
© 2009 Fairchild Semiconductor Corporation
FAN5400 Family • Rev. 1.0.7
www.fairchildsemi.com
9
I2C Timing Specifications
Guaranteed by design.
Symbol
Parameter
Conditions
Min. Typ. Max. Units
Standard Mode
Fast Mode
20+0.1CB
300
300
80
20+0.1CB
tFDA
SDA Fall Time
ns
High-Speed Mode, CB < 100pF
High-Speed Mode, CB < 400pF
Standard Mode
10
20
160
4
s
ns
ns
pF
tSU;STO
Stop Condition Setup Time
Fast Mode
600
160
High-Speed Mode
CB
Capacitive Load for SDA, SCL
400
Timing Diagrams
tF
tSU;STA
tBUF
SDA
tR
TSU;DAT
tHD;STO
tHIGH
tHD;DAT
SCL
tLOW
tHD;STA
tHD;STA
REPEATED
START
START
STOP
START
Figure 5. I2C Interface Timing for Fast and Slow Modes
REPEATED
START
STOP
tFDA
tRDA
tSU;DAT
SDAH
tSU;STA
tRCL1
tFCL
tHIGH
tHD;DAT
note A
tRCL
tSU;STO
SCLH
tLOW
tHD;STA
REPEATED
START
= MCS Current Source Pull-up
= RP Resistor Pull-up
Note A: First rising edge of SCLH after Repeated Start and after each ACK bit.
Figure 6. I2C Interface Timing for High-Speed Mode
© 2009 Fairchild Semiconductor Corporation
FAN5400 Family • Rev. 1.0.7
www.fairchildsemi.com
10
Charge Mode Typical Characteristics
Unless otherwise specified, circuit of Figure 1, VOREG=4.2V, VBUS=5.0V, and TA=25°C.
180
160
140
120
100
80
900
800
700
600
500
400
300
200
100
-
60
40
5.5VBUS
5.0VBUS
4.5VBUS
5.5VBUS
5.0VBUS
4.5VBUS
20
-
2.5
3
3.5
4
4.5
2.5
3
3.5
4
4.5
Battery Voltage, VBAT (V)
Battery Voltage, VBAT (V)
Figure 7. Battery Charge Current vs. VBUS with
IINLIM=100mA
Figure 8. Battery Charge Current vs. VBUS with IINLIM=500mA
94%
92%
90%
94%
92%
90%
88%
88%
4.20VBAT, 4.5VBUS
4.5VBUS
86%
84%
86%
4.20VBAT, 5.0VBUS
3.54VBAT, 5.0VBUS
3.54VBAT, 4.5VBUS
5.0VBUS
5.5VBUS
84%
550
650
750
850
950
1050
1150
1250
2.5
2.7
2.9
3.1
3.3
3.5
3.7
3.9
4.1
4.3
V
BAT Load Current (mA)
Battery Voltage, VBAT (V)
Figure 9. Charger Efficiency, No IINLIM, IOCHARGE=1,250mA
Figure 10. Charger Efficiency vs. VBUS, IINLIM=500mA
Figure 11. Auto-Charge Startup at VBUS Plug-in,
IINLIM=100mA, OTG=1, VBAT=3.4V
Figure 12. Auto-Charge Startup at VBUS Plug-in,
IINLIM=500mA, OTG=1, VBAT=3.4V
© 2009 Fairchild Semiconductor Corporation
FAN5400 Family • Rev. 1.0.7
www.fairchildsemi.com
11
Charge Mode Typical Characteristics
Unless otherwise specified, circuit of Figure 1, VOREG=4.2V, VBUS=5.0V, and TA=25°C.
Figure 13. AutoCharge Startup with 300mA Limited Charger
/ Adaptor, IINLIM=500mA, OTG=1, VBAT=3.4V
Figure 14. Charger Startup with HZ_MODE Bit Reset,
IINLIM=500mA, IOCHARGE=950mA, OREG=4.2V, VBAT=3.6V
Figure 15. Battery Removal / Insertion during Charging,
Figure 16. Battery Removal / Insertion during Charging,
VBAT=3.9V, IOCHARGE=950mA, No IINLIM, TE=1
VBAT=3.9V, IOCHARGE=950mA, No IINLIM, TE=0
© 2009 Fairchild Semiconductor Corporation
FAN5400 Family • Rev. 1.0.7
www.fairchildsemi.com
12
Charge Mode Typical Characteristics
Unless otherwise specified, circuit of Figure 1, VOREG=4.2V, VBUS=5.0V, and TA=25°C.
Figure 17. No Battery at VBUS Power-up; FAN5400, FAN5403 Figure 18. No Battery at VBUS Power-up; FAN5402, FAN5405
200
150
100
50
1.82
1.81
1.80
1.79
1.78
1.77
-30C
+25C
+85C
-10C, 5.0VBUS
+25C, 5.0VBUS
+85C, 5.0VBUS
0
4.0
4.5
5.0
Input Voltage, VBUS (V)
5.5
6.0
0
1
2
3
4
5
1.8V Regulator Load Current (mA)
Figure 19. VBUS Current in High-Impedance Mode
with Battery Open
Figure 20. VREG 1.8V Output Regulation
© 2009 Fairchild Semiconductor Corporation
FAN5400 Family • Rev. 1.0.7
www.fairchildsemi.com
13
Boost Mode Typical Characteristics
Unless otherwise specified, using circuit of Figure 1, VBAT=3.6V, TA=25°C.
100
95
90
85
80
75
100
95
90
85
80
75
2.7VBAT
3.6VBAT
4.2VBAT
-10C, 3.6VBAT
+25C, 3.6VBAT
+85C, 3.6VBAT
0
50
100
150
200
250
300
0
50
100
150
200
250
300
V
BUS Load Current (mA)
VBUS Load Current (mA)
Figure 21. Efficiency vs. VBAT
Figure 22. Efficiency Over Temperature
5.12
5.09
5.06
5.03
5.00
4.97
4.94
5.12
5.09
5.06
5.03
5.00
4.97
4.94
2.7VBAT
3.6VBAT
4.2VBAT
-10C, 3.6VBAT
+25C, 3.6VBAT
+85C, 3.6VBAT
0
50
100
150
200
250
300
0
50
100
150
200
250
300
VBUS Load Current (mA)
VBUS Load Current (mA)
Figure 23. Output Regulation vs. VBAT
Figure 24. Output Regulation Over Temperature
250
200
150
100
50
20
-30C
+25C
+85C
15
10
-30C
5
+25C
+85C
0
2
2.5
3
3.5
4
4.5
5
2
2.5
3
3.5
4
4.5
5
Battery Voltage, VBAT (V)
Battery Voltage, VBAT (V)
Figure 25. Quiescent Current
Figure 26. High-Impedance Mode Battery Current
© 2009 Fairchild Semiconductor Corporation
FAN5400 Family • Rev. 1.0.7
www.fairchildsemi.com
14
Boost Mode Typical Characteristics
Unless otherwise specified, using circuit of Figure 1, VBAT=3.6V, TA=25°C.
Figure 27. Boost PWM Waveform
Figure 28. Boost PFM Waveform
30
25
20
15
10
5
30
25
20
15
10
5
2.7VBAT
3.6VBAT
4.2VBAT
4.5VBAT
-30C, 3.6VBAT
+25C, 3.6VBAT
+85C, 3.6VBAT
0
0
0
50
100
150
200
250
300
0
50
100
150
200
250
300
VBUS Load Current (mA)
VBUS Load Current (mA)
Figure 29. Output Ripple vs. VBAT
Figure 30. Output Ripple vs. Temperature
© 2009 Fairchild Semiconductor Corporation
FAN5400 Family • Rev. 1.0.7
www.fairchildsemi.com
15
Boost Mode Typical Characteristics
Unless otherwise specified, using circuit of Figure 1, VBAT=3.6V, TA=25°C.
Figure 32. VBUS Fault Response, 3.6VBAT
Figure 31. Startup, 3.6VBAT, 44 Load, Additional 10µF,
X5R Across VBUS
Figure 33. Load Transient, 5-155-5mA, tR=tF=100ns
Figure 34. Load Transient, 5-255-5mA, tR=tF=100ns
© 2009 Fairchild Semiconductor Corporation
FAN5400 Family • Rev. 1.0.7
www.fairchildsemi.com
16
Circuit Description / Overview
When charging batteries with a current-limited input source,
such as USB, a switching charger’s high efficiency over a
wide range of output voltages minimizes charging time.
with a constant current if sufficient input power is available.
The current slew rate is limited to prevent overshoot.
The FAN540X is designed to work with a current-limited
input source at VBUS. During the current regulation phase of
charging, IINLIM or the programmed charging current limits the
amount of current available to charge the battery and power
the system. The effect of IINLIM on ICHARGE can be seen in
Figure 36.
FAN540X combines a highly integrated synchronous buck
regulator for charging with a synchronous boost regulator,
which can supply 5V to USB On-The-Go (OTG) peripherals.
The regulator employs synchronous rectification for both the
charger and boost regulators to maintain high efficiency over
a wide range of battery voltages and charge states.
V
OREG
The FAN540X has three operating modes:
ICHARGE
IOCHARGE
1. Charge Mode:
Charges a single-cell Li-ion or Li-polymer battery.
2. Boost Mode:
Provides 5V power to USB-OTG with an integrated
synchronous rectification boost regulator using the
battery as input.
ITERM
V
SHORT
ISHORT
3. High-Impedance Mode:
Both the boost and charging circuits are OFF in this
mode. Current flow from VBUS to the battery or from the
battery to VBUS is blocked in this mode. This mode
consumes very little current from VBUS or the battery.
PRE-
CHARGE
CURRENT REGULATION
VOLTAGE
REGULATION
Note: Default settings are denoted by bold typeface.
Figure 35. Charge Curve, ICHARGE Not Limited by IINLIM
Charge Mode
In Charge Mode, FAN540X employs four regulation loops:
VOREG
1. Input Current: Limits the amount of current drawn from
VBUS. This current is sensed internally and can be
programmed through the I2C interface.
2. Charging Current: Limits the maximum charging current.
This current is sensed using an external RSENSE resistor.
ITERM
VSHORT
3. Charge Voltage: The regulator is restricted from
exceeding this voltage. As the internal battery voltage
rises, the battery’s internal impedance and RSENSE work
in conjunction with the charge voltage regulation to
decrease the amount of current flowing to the battery.
Battery charging is completed when the voltage across
RSENSE drops below the ITERM threshold.
ISHORT
PRE-
CHARGE
CURRENT REGULATION
VOLTAGE
REGULATION
4. Temperature: If the IC’s junction temperature reaches
120°C, charge current is continuously reduced until the
IC’s temperature stabilizes at 120°C.
Figure 36. Charge Curve, IINLIM Limits ICHARGE
Assuming that VOREG is programmed to the cell’s fully
charged “float” voltage, the current that the battery accepts
with the PWM regulator limiting its output (sensed at VBAT)
to VOREG declines, and the charger enters the voltage
regulation phase of charging. When the current declines to
the programmed ITERM value, the charge cycle is complete.
Charge current termination can be disabled by resetting the
TE bit (REG1[3]).
In addition, the FAN5403-05 employ an additional loop to
limit the amount of drop on VBUS to a programmable voltage
(VSP) to accommodate “special chargers” that limit current to
a lower current than might be available from a “normal” USB
wall charger.
Battery Charging Curve
The charger output or “float” voltage can be programmed by
the OREG bits from 3.5V to 4.44V in 20mV increments, as
shown in Table 3.
If the battery voltage is below VSHORT, a linear current source
pre-charges the battery until VBAT reaches VSHORT. The PWM
charging circuit is then started and the battery is charged
© 2009 Fairchild Semiconductor Corporation
FAN5400 Family • Rev. 1.0.7
www.fairchildsemi.com
17
A new charge cycle begins when one of the following occurs:
Table 3. OREG Bits (OREG[7:2]) vs. Charger VOUT
(VOREG) Float Voltage
.
.
The battery voltage falls below VOREG - VRCH
Decimal Hex VOREG
Decimal Hex VOREG
VBUS Power On Reset (POR) clears and the battery
voltage is below the weak battery threshold (VLOWV).
This occurs for all versions except the FAN5401.
0
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
3.50
3.52
3.54
3.56
3.58
3.60
3.62
3.64
3.66
3.68
3.70
3.72
3.74
3.76
3.78
3.80
3.82
3.84
3.86
3.88
3.90
3.92
3.94
3.96
3.98
4.00
4.02
4.04
4.06
4.08
4.10
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
4.14
4.16
4.18
4.20
4.22
4.24
4.26
4.28
4.30
4.32
4.34
4.36
4.38
4.40
4.42
4.44
4.44
4.44
4.44
4.44
4.44
4.44
4.44
4.44
4.44
4.44
4.44
4.44
4.44
4.44
4.44
1
2
.
CE or HZ_MODE is reset through I2C write to
CONTROL1 (R1) register.
3
4
Charge Current Limit (IOCHARGE
)
5
Table 5. IOCHARGE (REG4 [6:4]) Current as Function
of IOCHARGE Bits and RSENSE Resistor Values
6
7
I
OCHARGE (mA)
VRSENSE
(mV)
8
DEC
BIN
HEX
68m 100m
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0
1
2
3
4
5
6
7
000
001
010
011
100
101
110
111
00
01
02
03
04
05
06
07
37.4
44.2
51.0
57.8
64.6
71.4
78.2
85.0
550
650
374
442
510
578
646
714
782
850
750
850
950
1050
1150
1250
Termination Current Limit
Current charge termination is enabled when TE (REG1[3])=1.
Typical termination current values are given in Table 6.
Table 6. ITERM Current as Function of ITERM Bits
(REG4[2:0]) and RSENSE Resistor Values
FAN5400 - FAN5402 FAN5403 - FAN5405
ITERM (mA)
ITERM (mA)
VRSENSE
(mV)
VRSENSE
(mV)
ITERM
68m 100m
68m 100m
0
1
2
3
4
5
6
7
3.4
50
34
3.3
6.6
49
33
66
6.8
100
150
200
250
300
350
400
68
97
10.2
13.6
17.0
20.4
23.8
27.2
102
136
170
204
238
272
9.9
146
194
243
291
340
388
99
The following charging parameters can be programmed by
the host through I2C:
13.2
16.5
19.8
23.1
26.4
132
165
198
231
264
Table 4. Programmable Charging Parameters
Parameter
Output Voltage Regulation
Battery Charging Current Limit
Input Current Limit
Name
VOREG
IOCHRG
IINLIM
Register
REG2[7:2]
REG4[6:4]
REG1[7:6]
REG4[2:0]
REG1[5:4]
When the charge current falls below ITERM, PWM charging
stops and the STAT bits change to READY (00) for about
500ms while the IC determines whether the battery and
charging source are still connected. STAT then changes to
CHARGE DONE (10), provided the battery and charger are
still connected.
Charge Termination Limit
Weak Battery Voltage
ITERM
VLOWV
© 2009 Fairchild Semiconductor Corporation
FAN5400 Family • Rev. 1.0.7
www.fairchildsemi.com
18
PWM Controller in Charge Mode
USB-Friendly Boot Sequence
The IC uses a current-mode PWM controller to regulate the
output voltage and battery charge currents. The synchronous
rectifier (Q2) has a negative current limit that turns off Q2 at
140mA to prevent current flow from the battery.
For all versions except FAN5401, FAN5404
At VBUS POR, when the battery voltage is above the weak
battery threshold (VLOWV), the IC operates in accordance with
its I2C register settings. If VBAT < VLOWV, the IC sets all
registers to their default values and enables the charger
using an input current limit controlled by the OTG pin
(100mA if OTG is LOW and 500mA if OTG is HIGH). This
feature can revive a battery whose voltage is too low to
ensure reliable host operation. Charging continues in the
absence of host communication even after the battery has
reached VOREG, whose default value is 3.54V, and the
charger remains active until t15MIN times out. Once the host
processor begins writing to the IC, charging parameters are
set by the host, which must continually reset the t32S timer to
continue charging using the programmed charging
parameters. If t32S.times out, the register defaults are loaded,
the FAULT bits are set to 110, STAT is pulsed HIGH, and
charging continues with default charge parameters.
Safety Timer
This section references Figure 41 and Figure 42.
At the beginning of charging, the IC starts a 15-minute timer
(t15MIN ). When this timer times out, charging is terminated.
Writing to any register through I2C stops and resets the t15MIN
timer, which in turn starts a 32-second timer (t32S). Setting
the TMR_RST bit (REG0[7]) resets the t32S timer. If the t32S
timer times out, charging is terminated, the registers are set
to their default values, and charging resumes using the
default values with the t15MIN timer running.
Normal charging is controlled by the host with the t32S timer
running to ensure that the host is alive. Charging with the
t15MIN timer running is used for charging that is unattended by
the host. If the t15MIN timer expires, the IC turns off the
The FAN5401 and FAN5404 do not automatically initiate
charging at VBUS POR. Instead, they wait for the host to
initiate charging through I2C commands.
charger, sets the
bit, and indicates a timer fault (110) on
CE
the FAULT bits (REG0[2:0]). This sequence prevents
overcharge if the host fails to reset the t32S timer.
Input Current Limiting
To minimize charging time without overloading VBUS current
limitations, the IC’s input current limit can be programmed by
the IINLIM bits (REG1[7:6]).
VBUS POR / Non-Compliant Charger Rejection
When the IC detects that VBUS has risen above VIN(MIN)1
(4.4V), the IC applies a 110 load from VBUS to GND. To
clear the VBUS POR (Power-On-Reset) and begin charging,
VBUS must remain above VIN(MIN)1 and below VBUSOVP for
Table 7. Input Current Limit
I
INLIM REG1[7:6]
Input Current Limit
100mA
t
VBUS_VALID (30ms) before the IC initiates charging. The VBUS
validation sequence always occurs before charging is
initiated or re-initiated (for example, after a VBUS OVP fault
or a VRCH recharge initiation).
00
01
10
11
500mA
800mA
tVBUS_VALID ensures that unfiltered 50/60hz chargers and
other non-compliant chargers are rejected.
No limit
For all versions except the FAN5401 and FAN5404, the OTG
pin establishes the input current limit when t15MIN is running.
For the FAN5401 and FAN5404, no charging occurs
automatically at VBUS POR, so the input current limit is
established by the IINLIM bits.
© 2009 Fairchild Semiconductor Corporation
FAN5400 Family • Rev. 1.0.7
www.fairchildsemi.com
19
Flow Charts
Figure 37. Charger VBUS POR
© 2009 Fairchild Semiconductor Corporation
FAN5400 Family • Rev. 1.0.7
www.fairchildsemi.com
20
CHARGE STATE
Disable Charging
NO
Indicate
VBUS Fault
Enable ISHORT
,
Reset Safety reg
YES
VBAT < VSHORT
VBUS OK?
YES
NO
Indicate Charging
NO
PWM Charging
T15MIN
VBUS OK?
YES
Indicate Charging
Timeout?
NO
YES
Disable Charging
Indicate timer fault
Set CE
Charge
Configuration
State
T15MIN
YES
Timeout?
Indicate
VBUS Fault
NO
NO
HIGHZ mode
IOUT < ITERM
YES
VBAT < VOREG–VRCH
Indicate Charge
Complete
NO
Termination enabled
VBAT > VOREG–VRCH
Reset Safety reg
Delay tINT
NO
YES
Battery Removed
Stop Charging
YES
VBAT < VOREG–VRCH
Reset charge
parameters
Enable IDET for TDETECT
Figure 38. Charge Mode
© 2009 Fairchild Semiconductor Corporation
FAN5400 Family • Rev. 1.0.7
www.fairchildsemi.com
21
Figure 39. Charge Configuration
Figure 40. HZ-State
© 2009 Fairchild Semiconductor Corporation
FAN5400 Family • Rev. 1.0.7
www.fairchildsemi.com
22
Charge Start
Start T15MIN
Reset Registers
YES
T32SEC
NO
Expired?
Start T32SEC
Stop T15MIN
YES
NO
T15MIN
I2C Write
received?
T15MIN
Continue
Charging
YES
NO
NO
Active?
Expired?
Timer Fault :
Set
YES
CE
Figure 41. Timer Flow Chart for FAN5400, FAN5402, FAN5403, FAN5405
Charge Start
from Host control
Timer Fault
Stop Charging and
Reset Registers
T32SEC
Reset T32SEC
Charge
NO
YES
Expired?
NO
TMR_RST
bit Set?
YES
Figure 42. Timer Flow Chart for FAN5401, FAN5404
© 2009 Fairchild Semiconductor Corporation
FAN5400 Family • Rev. 1.0.7
www.fairchildsemi.com
23
Table 9. ISAFE (IOCHARGE Limit) as Function of ISAFE
Bits (REG6[6:4])
Special Charger
FAN5403-05 Only
ISAFE (REG6[6:4])
The FAN5403, FAN5404, and FAN5405 have additional
functionality to limit input current in case a current-limited
“special charger” is supplying VBUS. The FAN5403-05
slowly increases the charging current until either:
ISAFE (mA)
DEC BIN HEX VRSENSE (mV)
68m 100m
0
1
2
3
4
5
6
7
000
001
010
011
100
101
110
111
00
01
02
03
04
05
06
07
37.4
44.2
51.0
57.8
64.6
71.4
78.2
85.0
550
650
374
442
510
578
646
714
782
850
.
IINLIM or IOCHARGE is reached
or
.
750
VBUS=VSP.
850
If VBUS collapses to VSP when the current is ramping up, the
FAN5403-05 charge with an input current that keeps
VBUS=VSP. When the VSP control loop is limiting the charge
current, the SP bit (REG5[4]) is set.
950
1050
1150
1250
Table 8. VSP as Function of SP Bits (REG5[2:0])
SP (REG5[2:0])
Table 10. VSAFE (VOREG Limit) as Function of VSAFE
Bits (REG6[3:0])
DEC
BIN
000
001
010
011
100
101
110
111
HEX
00
VSP
0
1
2
3
4
5
6
7
4.213
4.293
4.373
4.453
4.533
4.613
4.693
4.773
VSAFE (REG6[3:0])
01
Max. OREG
(REG2[7:2])
VOREG
Max.
02
DEC
BIN
HEX
03
0
1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
00
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
100011
100100
100101
100110
100111
101000
101001
101010
101011
101100
101101
101110
101111
110000
110001
110010
4.20
4.22
4.24
4.26
4.28
4.30
4.32
4.34
4.36
4.38
4.40
4.42
4.44
4.44
4.44
4.44
04
05
2
06
3
07
4
5
Safety Settings
6
FAN5403-FAN5405 Only
7
The FAN5403-05 contain a SAFETY register (REG6) that
prevents the values in OREG (REG2[7:2]) and IOCHARGE
(REG4[6:4]) from exceeding the values of the VSAFE and
ISAFE values.
8
9
10
11
12
13
14
15
After VBAT exceeds VSHORT, the SAFETY register is loaded
with its default value and may be written only before any
other register is written. After writing to any other register,
the SAFETY register is locked until VBAT falls below VSHORT
.
The ISAFE (REG6[6:4]) and VSAFE (REG6[3:0]) registers
establish values that limit the maximum values of IOCHARGE
and VOREG used by the control logic. If the host attempts to
write a value higher than VSAFE or ISAFE to OREG or
IOCHARGE, respectively; the VSAFE, ISAFE value appears
as the OREG, IOCHARGE register value, respectively.
Thermal Regulation and Protection
When the IC’s junction temperature reaches TCF (about 120°C),
the charger reduces its output current to 550mA to prevent
overheating. If the temperature increases beyond TSHUTDOWN
;
charging is suspended, the FAULT bits are set to 101, and
STAT is pulsed HIGH. In Suspend Mode, all timers stop and the
state of the IC’s logic is preserved. Charging resumes at
programmed current after the die cools to about 120°C.
© 2009 Fairchild Semiconductor Corporation
FAN5400 Family • Rev. 1.0.7
www.fairchildsemi.com
24
Battery Detection During Charging
Additional JA data points, measured using the FAN540X
evaluation board, are given in Table 11 (measured with
TA=25°C). Note that as power dissipation increases, the
effective JA decreases due to the larger difference between
the die temperature and its ambient.
The IC can detect the presence, absence, or removal of a
battery if the termination bit (TE) is set. During normal
charging, once VBAT is close to VOREG and the termination
charge current is detected, the IC terminates charging and
sets the STAT bits to 10. It then turns on a discharge current,
IDETECT, for tDETECT. If VBAT is still above VOREG – VRCH, the
battery is present and the IC sets the FAULT bits to 000. If
VBAT is below VOREG – VRCH, the battery is absent and the IC:
Table 11. FAN5400 Evaluation Board Measured JA
Power (W)
0.504
JA
54°C/W
50°C/W
46°C/W
1. Sets the registers to their default values.
2. Sets the FAULT bits to 111.
0.844
1.506
3. Resumes charging with default values after tINT
.
Charge Mode Input Supply Protection
Battery Short-Circuit Protection
If the battery voltage is below the short-circuit threshold
(VSHORT); a linear current source, ISHORT, supplies VBAT until
Sleep Mode
When VBUS falls below VBAT + VSLP, and VBUS is above
VIN(MIN), the IC enters Sleep Mode to prevent the battery from
draining into VBUS. During Sleep Mode, reverse current is
disabled by body switching Q1.
VBAT > VSHORT.
Battery Detection During Power-up
For FAN5400 and FAN5403
Input Supply Low-Voltage Detection
The IC continuously monitors VBUS during charging. If VBUS
falls below VIN(MIN), the IC:
At VBUS POR, a 5K load is applied to VBAT for 500ms to
discharge any residual system capacitance in case the
battery is absent. If VBAT
< VSHORT, linear charging
1. Terminates charging
commences. When VBAT rises above VSHORT, PWM charging
proceeds with the float voltage (OREG) temporarily set to
4V. If the battery voltage exceeds 3.7V within 32ms of the
beginning of PWM charging, the battery is absent. If battery
absent is detected:
2. Pulses the STAT pin, sets the STAT bits to 11, and sets
the FAULT bits to 011.
If VBUS recovers above the VIN(MIN) rising threshold after time
tINT (about two seconds), the charging process is repeated.
This function prevents the USB power bus from collapsing or
oscillating when the IC is connected to a suspended USB
port or a low-current-capable OTG device.
1. High-Impedance Mode is entered.
2. FAULT bits are set to 111.
3. The t15MIN timer is disabled until VBUS is removed.
Input Over-Voltage Detection
When the VBUS exceeds VBUSOVP, the IC:
If VBAT remains below 3.7V during the initial 32ms period, the
float voltage returns to the OREG register setting and PWM
charging continues.
1. Turns off Q3
2. Suspends charging
3. Sets the FAULT bits to 001, sets the STAT bits to 11,
and pulses the STAT pin.
System Operation with No Battery
The FAN5402 and FAN5405 continue charging after VBUS
POR with the default parameters, regulating the VBAT line to
3.54V until the host processor issues commands or the 15-
minute timer expires. In this way, the FAN5402 and
FAN5405 can start the system without a battery.
When VBUS falls about 150mV below VBUSOVP, the fault is
cleared and charging resumes after VBUS is revalidated (see
VBUS POR / Non-Compliant Charger Rejection).
VBUS Short While Charging
The FAN540X soft-start function can interfere with the
system supply with battery absent. The soft-start activates
whenever VOREG, IINLIM, or IOCHARGE are set from a lower to
higher value. During soft-start, the IIN limit drops to 100mA
for about 1ms unless IINLIM is set to 11 (no limit). This could
cause the system processor to fail to start. To avoid this
behavior, use the following sequence.
If VBUS is shorted with a very low impedance while the IC is
charging with IINLIMIT=100mA, the IC may not meet datasheet
specifications until power is removed. To trigger this
condition, VBUS must be driven from 5V to GND with a high
slew rate. Achieving this slew rate requires a 0 short to the
USB cable less than 10cm from the connector.
1. Set the OTG pin HIGH. When VBUS is plugged in, IINLIM
is set to 500mA until the system processor powers up
and can set parameters through I2C.
Charge Mode Battery Detection & Protection
VBAT Over-Voltage Protection
The OREG voltage regulation loop prevents VBAT from
overshooting the OREG voltage by more than 50mV when
the battery is removed. When the PWM charger runs with no
battery, the TE bit is not set and a battery is inserted that is
charged to a voltage higher than VOREG; PWM pulses stop. If
no further pulses occur for 30ms, the IC sets the FAULT bits
to 100, sets the STAT bits to 11, and pulses the STAT pin.
2. Program the Safety Register.
3. Set IINLIM to 11 (no limit).
4. Set OREG to the desired value (typically 4.18).
5. Reset the IOLEVEL bit, then set IOCHARGE.
6. Set IINLIM to 500mA if a USB source is connected.
© 2009 Fairchild Semiconductor Corporation
FAN5400 Family • Rev. 1.0.7
www.fairchildsemi.com
25
During the initial system startup, while the charger IC is
being programmed, the system current is limited to 325mA
for 1ms during steps 4 and 5. This is the value of the soft-
start ICHARGE current used when IINLIM is set to No Limit.
Charge Mode Control Bits
Setting either HZ_MODE or CE through I2C disables the
charger and puts the IC into High-Impedance Mode and
resets t32S. If VBAT < VLOWV while in High-Impedance Mode,
t32S begins running and, when it overflows, all registers
(except SAFETY) reset, which enables t15MIN charging on
versions with the 15-minute timer.
If the system is powered up without a battery present, the
CV bit should be set. When a battery is inserted, the CV bit
is cleared.
Charger Status / Fault Status
The STAT pin indicates the operating condition of the IC and
provides a fault indicator for interrupt driven systems.
When t15MIN overflows, the IC sets the CE bit and the IC
enters High-Impedance Mode. If CE was set by t15MIN
overflow, a new charge cycle can only be initiated through
I2C or VBUS POR.
Table 12. STAT Pin Function
Setting the RESET bit clears all registers. If HZ_MODE or
EN_STAT
Charge State
X
STAT Pin
OPEN
CE bits were set when the RESET bit is set, these bits are
also cleared, but the t32S timer is not started, and the IC
remains in High-Impedance Mode.
0
X
1
Normal Conditions
Charging
OPEN
LOW
Fault
(Charging or Boost)
128s Pulse,
then OPEN
Table 14. FAN5403–FAN5405 DISABLE Pin and
X
CE Bit Functionality
Charging
DISABLE Pin
HZ_MODE
The FAULT bits (R0[2:0]) indicate the type of fault in Charge
Mode (see Table 13).
CE
ENABLE
DISABLE
DISABLE
DISABLE
0
X
X
1
0
1
0
X
1
Table 13. Fault Status Bits During Charge Mode
Fault Bit
X
X
Fault Description
B2 B1 B0
X
Raising the DISABLE pin stops t32S from advancing, but
does not reset it. If the DISABLE pin is raised during t15MIN
charging, the t15MIN timer is reset.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Normal (No Fault)
VBUS OVP
Sleep Mode
Operational Mode Control
Poor Input Source
Battery OVP
OPA_MODE (REG1[0]) and the HZ_MODE (REG1[1]) bits in
conjunction with the FAULT state define the operational
mode of the charger.
Thermal Shutdown
Timer Fault
Table 15. Operation Mode Control
No Battery
HZ_MODE OPA_MODE FAULT Operation Mode
0
0
0
1
0
X
1
0
1
0
X
Charge
Charge Configure
Boost
X
High Impedance
The IC resets the OPA_MODE bit whenever the boost is
deactivated, whether due to a fault or being disabled by
setting the HZ_MODE bit.
© 2009 Fairchild Semiconductor Corporation
FAN5400 Family • Rev. 1.0.7
www.fairchildsemi.com
26
VBUS as a function of ILOAD can be computed when the
regulator is in PWM Mode (continuous conduction) as:
Boost Mode
Boost Mode can be enabled if the IC is in 32-Second Mode
with the OTG pin and OPA_MODE bits as indicated in Table
16. The OTG pin ACTIVE state is 1 if OTG_PL=1 and 0
when OTG_PL=0.
EQ. 1
VOUT 5.07ROUT ILOAD
At VBAT=3.3V, and ILOAD=200mA, VBUS would drop to:
If boost is active using the OTG pin, Boost Mode is initiated
even if the HZ_MODE=1. The HZ_MODE bit overrides the
OPA_MODE bit.
EQ. 1A
VOUT 5.070.260.2 5.018V
At VBAT=2.7V, and ILOAD=200mA, VBUS would drop to:
Table 16. Enabling Boost
EQ. 1B
VOUT 5.070.3270.2 5.005V
OTG
Pin
HZ_
MODE MODE
OPA_
OTG_EN
BOOST
PFM Mode
If VBUS > VREFBOOST (nominally 5.07V) when the minimum
off-time has ended, the regulator enters PFM Mode. Boost
pulses are inhibited until VBUS < VREFBOOST. The minimum
on-time is increased to enable the output to pump up
sufficiently with each PFM boost pulse. Therefore the
regulator behaves like a constant on-time regulator, with the
bottom of its output voltage ripple at 5.07V in PFM Mode.
1
ACTIVE
X
X
0
X
1
Enabled
Enabled
X
X
0
1
0
X
1
1
0
0
X
1
0
Disabled
Disabled
Disabled
Disabled
ACTIVE
X
ACTIVE
ACTIVE
Table 17. Boost PWM Operating States
Mode
LIN
Description
Linear Startup
Boost Soft-Start
Invoked When
VBAT > VBUS
To remain in Boost Mode, the TMR_RST must be set by the
host before the t32S timer times out. If t32S times out in Boost
Mode; the IC resets all registers, pulses the STAT pin, sets
the FAULT bits to 110, and resets the BOOST bit. VBUS
POR or reading R0 clears the fault condition.
SS
VBUS < VBST
V
BAT > UVLOBST and
SS Completed
BST
Boost Operating Mode
Boost PWM Control
Startup
The IC uses a minimum on-time and computed minimum off-
time to regulate VBUS. The regulator achieves excellent
transient response by employing current-mode modulation.
This technique causes the regulator to exhibit a load line.
During PWM Mode, the output voltage drops slightly as the
input current rises. With a constant VBAT, this appears as a
constant output resistance.
When the boost regulator is shut down, current flow is
prevented from VBAT to VBUS, as well as reverse flow from
VBUS to VBAT
.
LIN State
When EN rises, if VBAT > UVLOBST, the regulator first
attempts to bring PMID within 400mV of VBAT using an
internal 450mA current source from VBAT (LIN State). If
PMID has not achieved VBAT – 400mV after 560s, a FAULT
state is initiated.
The “droop” caused by the output resistance when a load is
applied allows the regulator to respond smoothly to load
transients with no undershoot from the load line. This can be
seen in Figure 33 and Figure 43.
350
325
300
275
250
225
200
SS State
When PMID > VBAT – 400mV, the boost regulator begins
switching with a reduced peak current limit of about 50% of
its normal current limit. The output slews up until VBUS is
within 5% of its set point; at which time, the regulation loop is
closed and the current limit is set to 100%.
If the output fails to achieve 95% of its set point (VBST) within
128s, the current limit is increased to 100%. If the output
fails to achieve 95% of its set point after this second 384s
period, a fault state is initiated.
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Battery Voltage, VBAT (V)
Figure 43. Output Resistance (ROUT
)
© 2009 Fairchild Semiconductor Corporation
FAN5400 Family • Rev. 1.0.7
www.fairchildsemi.com
27
BST State
VREG Pin
This is the normal operating mode of the regulator. The
regulator uses a minimum tOFF-minimum tON modulation
The VREG pin on FAN5400 - FAN5402 provides a voltage
protected from over-voltage surges on VBUS, which can be
used to run auxiliary circuits. This voltage is essentially a
current-limited replica of PMID. The maximum voltage on
this node is 5.9V.
V
IN
scheme. The minimum tOFF is proportional to
, which
V
OUT
keeps the regulator’s switching frequency reasonably
constant in CCM. tON(MIN) is proportional to VBAT and is a
higher value if the inductor current reached 0 before tOFF(MIN)
in the prior cycle.
FAN5403-FAN5405 provide a 1.8V regulated output on this
pin, which can be disabled through I2C by setting the
DIS_VREG bit (REG5[6]). VREG can supply up to 2mA. This
circuit, which is powered from PMID, is enabled only when
PMID > VBAT and does not drain current from the battery.
During boost, VREG is off. It is also off when the HZ_MODE
bit (REG1[1])=1.
To ensure the VBUS does not pump significantly above the
regulation point, the boost switch remains off as long as
FB > VREF
.
Boost Faults
If a BOOST fault occurs:
Monitor Register (Reg10H)
Additional status monitoring bits enable the host processor
to have more visibility into the status of the IC. The monitor
bits are real-time status indicators and are not internally
debounced or otherwise time qualified.
1. The STAT pin pulses.
2. OPA_MODE bit is reset.
3. The power stage is in High-Impedance Mode.
4. The FAULT bits (REG0[2:0]) are set per Table 18.
The state of the MONITOR register bits listed in High-
Impedance Mode are only valid when VBUS is valid.
Restart After Boost Faults
If boost was enabled with the OPA_MODE bit and
OTG_EN=0, Boost Mode can only be enabled through
subsequent I2C commands since OPA_MODE is reset on
boost faults. If OTG_EN=1 and the OTG pin is still ACTIVE
(see Table 16), the boost restarts after a 5.2ms delay, as
shown in Figure 44. If the fault condition persists, restart is
attempted every 5ms until the fault clears or an I2C
command disables the boost.
Table 18. Fault Bits During Boost Mode
Fault Bit
Fault Description
B2 B1 B0
0
0
0
0
0
1
Normal (no fault)
VBUS > VBUSOVP
VBUS fails to achieve the voltage required to
advance to the next state during soft-start
or sustained (>50s) current limit during the
BST state.
0
1
0
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
VBAT < UVLOBST
N/A: This code does not appear.
Thermal shutdown
Timer fault; all registers reset.
N/A: This code does not appear.
0
VBUS
560
5200
450mA
BATTERY
CURRENT
0
64
BOOST
ENABLED
Figure 44. Boost Response Attempting to Start into VBUS
Short Circuit (Times in s)
© 2009 Fairchild Semiconductor Corporation
FAN5400 Family • Rev. 1.0.7
www.fairchildsemi.com
28
Table 19. MONITOR Register Bit Definitions
STATE
BIT#
NAME
Active When
0
1
MONITOR
Address 10H
CSIN – VBAT < VITERM
V
VCSIN – VBAT > VITERM
VCSIN – VBAT > 1mV
VBAT > VSHORT
Charging with TE=1
Charging with TE=0
Charging
7
ITERM_CMP
VCSIN – VBAT < 1mV
VBAT < VSHORT
6
VBAT_CMP
VBAT < VLOWV
VBAT > VLOWV
High-Impedance Mode
Boosting
VBAT < UVLOBST
Linear Charging Not Enabled
TJ < 120°
VBAT > UVLOBST
Linear Charging Enabled
TJ > 120°
5
4
LINCHG
T_120
Charging
Charging Current Controlled by
ICHARGE Control Loop
Charging Current Not Controlled by
ICHARGE Control Loop
3
ICHG
Charging
2
1
0
IBUS
IBUS Limiting Charging Current
VBUS Not Valid
Charge Current Not Limited by IBUS Charging
VBUS_VALID
CV
VBUS is Valid
VBUS > VBAT
Charging
Constant Current Charging
Constant Voltage Charging
© 2009 Fairchild Semiconductor Corporation
FAN5400 Family • Rev. 1.0.7
www.fairchildsemi.com
29
I2C Interface
Slave Releases
Master Drives
The FAN540X’s serial interface is compatible with Standard,
Fast, Fast Plus, and High-Speed Mode I2C-Bus®
specifications. The FAN540X’s SCL line is an input and its
SDA line is a bi-directional open-drain output; it can only pull
down the bus when active. The SDA line only pulls LOW
during data reads and when signaling ACK. All data is
shifted in MSB (bit 7) first.
tHD;STO
ACK(0) or
NACK(1)
SDA
SCL
Slave Address
Figure 47. Stop Bit
Table 20. I2C Slave Address Byte
During a read from the FAN540X (Figure 50), the master
issues a Repeated Start after sending the register address
and before resending the slave address. The Repeated Start
is a 1-to-0 transition on SDA while SCL is HIGH, as shown in
Figure 48.
Part Types
FAN5400–FAN5404
FAN5405
7 6 5 4 3 2 1
0
1
1
1
1
0
0
1
1
0
0
1
1
1
0
R/W
R/W
High-Speed (HS) Mode
In hex notation, the slave address assumes a 0 LSB. The
hex slave address for the FAN5405 is D4H and is D6H for all
other parts in the family.
The protocols for High-Speed (HS), Low-Speed (LS), and
Fast-Speed (FS) Modes are identical except the bus speed
for HS Mode is 3.4MHz. HS Mode is entered when the bus
master sends the HS master code 00001XXX after a start
condition. The master code is sent in Fast or Fast Plus Mode
(less than 1MHz clock); slaves do not ACK this transmission.
Bus Timing
As shown in Figure 45, data is normally transferred when
SCL is LOW. Data is clocked in on the rising edge of SCL.
Typically, data transitions shortly at or after the falling edge
of SCL to allow ample time for the data to set up before the
next SCL rising edge.
The master then generates a repeated start condition
(Figure 48) that causes all slaves on the bus to switch to HS
Mode. The master then sends I2C packets, as described
above, using the HS Mode clock rate and timing.
Data change allowed
The bus remains in HS Mode until a stop bit (Figure 47) is
sent by the master. While in HS Mode, packets are
separated by repeated start conditions (Figure 48).
SDA
TH
Slave Releases
tSU;STA
tHD;STA
TSU
SCL
ACK(0) or
NACK(1)
SLADDR
MS Bit
SDA
SCL
Figure 45. Data Transfer Timing
Each bus transaction begins and ends with SDA and SCL
HIGH. A transaction begins with a START condition, which is
defined as SDA transitioning from 1 to 0 with SCL HIGH, as
shown in Figure 46.
Figure 48. Repeated Start Timing
THD;STA
Slave Address
MS Bit
SDA
SCL
Figure 46. Start Bit
A transaction ends with a STOP condition, which is defined
as SDA transitioning from 0 to 1 with SCL HIGH, as shown
in Figure 47.
© 2009 Fairchild Semiconductor Corporation
FAN5400 Family • Rev. 1.0.7
www.fairchildsemi.com
30
Read and Write Transactions
The figures below outline the sequences for data read and
write. Bus control is signified by the shading of the packet,
Table 21. Bit Definitions for Figure 49, Figure 50
Symbol
Definition
Master Drives Bus
Slave Drives Bus
defined as
All
and
data
.
S
START, see Figure 46.
addresses
and
are
MSB
first.
ACK. The slave drives SDA to 0 to acknowledge
the preceding packet.
A
NACK. The slave sends a 1 to NACK the
preceding packet.
A
R
P
Repeated START, see Figure 48
STOP, see Figure 47
0
0
0
7 bits
8 bits
8 bits
Data
S
Slave Address
0
A
Reg Addr
A
A
P
Figure 49. Write Transaction
0
0
0
1
7 bits
8 bits
7 bits
8 bits
Data
S
Slave Address
0
A
Reg Addr
A
R
Slave Address
1
A
A
P
Figure 50. Read Transaction
© 2009 Fairchild Semiconductor Corporation
FAN5400 Family • Rev. 1.0.7
www.fairchildsemi.com
31
Register Descriptions
The FAN5400-FAN5402 have seven user-accessible registers; the FAN5403-05 have an additional two registers, as defined in
Table 22.
Table 22. I2C Register Address
Register
Address Bits
IC
Name
REG#
7
0
0
0
6
0
0
0
5
0
0
0
4
0
0
0
3
0
0
0
2
0
0
0
1
0
0
1
0
0
1
0
CONTROL0
CONTROL1
OREG
0
1
2
ALL
03
or
IC_INFO
0
0
0
0
0
0
1
1
3BH
IBAT
4
5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
0
1
0
0
SP_CHARGER
SAFETY
FAN5403-FAN5405
ALL
6
MONITOR
10H
Table 23. Register Bit Definitions
This table defines the operation of each register bit for all IC versions. Default values are in bold text.
Bit
Name
Value Type
Description
CONTROL0
Register Address: 00
Default Value=X1XX 0XXX
W
Writing a 1 resets the t32S timer; writing a 0 has no effect
Returns the OTG pin level (1=HIGH)
TMR_RST
7
1
OTG
R
Prevents STAT pin from going LOW during charging; STAT pin still pulses to
enunciate faults
0
R/W
6
EN_STAT
1
00
01
10
11
0
Enables STAT pin LOW when IC is charging
R
Ready
Charge in progress
5:4
STAT
Charge done
Fault
R
IC is not in Boost Mode
3
BOOST
FAULT
1
IC is in Boost Mode
2:0
R
Fault status bits: for Charge Mode, see Table 13; for Boost Mode: see Table 18
© 2009 Fairchild Semiconductor Corporation
FAN5400 Family • Rev. 1.0.7
www.fairchildsemi.com
32
Table 23. Register Bit Definitions (Continued)
Bit Name Value Type
Description
CONTROL1
Register Address: 01
Default Value=0011 0000 (30H)
7:6
IINLIM
R/W Input current limit, see Table 7
R/W 3.4V
00
01
10
11
0
3.5V
5:4
VLOWV
Weak battery voltage threshold
3.6V
3.7V
R/W Disable charge current termination
Enable charge current termination
R/W Charger enabled
Charger disabled
3
2
1
0
TE
CE
1
0
1
0
R/W Not High-Impedance Mode
High-Impedance Mode
R/W Charge Mode
Boost Mode
HZ_MODE
OPA_MODE
1
See Table 16
0
1
OREG
Register Address: 02
Default Value=0000 1010 (0AH)
Charger output “float” voltage; programmable from 3.5 to 4.44V in 20mV
increments; defaults to 000010 (3.54V), see Table 3
7:2
OREG
R/W
0
1
0
1
R/W OTG pin active LOW
OTG pin active HIGH
R/W Disables OTG pin
Enables OTG pin
1
0
OTG_PL
OTG_EN
IC_INFO
Register Address: 03 or 3B
Default Value=100X XXXX
7:5
4:3
Vendor Code
100
R
R
R
Identifies Fairchild Semiconductor as the IC supplier
PN
Part number bits, see the Ordering Info on page 1
2:0
REV
IC Revision, revision 1.X, where X is the decimal of these three bits
IBAT
Register Address: 04
Default Value=1000 1001 (89H)
Writing a 1 resets charge parameters, except the Safety register (Reg6), to their
defaults: writing a 0 has no effect; read returns 1
7
RESET
1
W
6:4
3
IOCHARGE
Reserved
ITERM
Table 5
1
R/W Programs the maximum charge current, see Table 5
Unused
R
2:0
Table 6
R/W Sets the current used for charging termination, see Table 6
© 2009 Fairchild Semiconductor Corporation
FAN5400 Family • Rev. 1.0.7
www.fairchildsemi.com
33
Table 23. Register Bit Definitions (Continued)
SP_CHARGER (FAN5403 – FAN5405) Register Address: 05
Default Value=001X X100
7
Reserved
0
0
1
0
R
Unused
R/W 1.8V regulator is ON
6
DIS_VREG
1.8V regulator is OFF
R/W Output current is controlled by IOCHARGE bits
5
4
IO_LEVEL
SP
Voltage across RSENSE for output current control is set to 22.1mV (325mA for
SENSE=68m, 221mA for 100m)
Special charger is not active (VBUS is able to stay above VSP
1
R
0
R
R
)
1
Special charger has been detected and VBUS is being regulated to VSP
DISABLE pin is LOW
0
1
3
EN_LEVEL
VSP
DISABLE pin is HIGH
2:0
Table 8
R/W Special charger input regulation voltage, see Table 8
SAFETY (FAN5403 – FAN5405)
Register Address: 06
Default Value=0100 0000 (40H)
7
Reserved
ISAFE
0
R
Bit disabled and always returns 0 when read back
6:4
3:0
Table 9
R/W Sets the maximum IOCHARGE value used by the control circuit, see Table 9
VSAFE
Table 10 R/W Sets the maximum VOREG used by the control circuit, see Table 10
Register Address: 10H (16)
See Table 19
MONITOR
7
6
5
ITERM_CMP
R
R
R
ITERM comparator output, 1 when VRSENSE > ITERM reference
Output of VBAT comparator
VBAT_CMP
LINCHG
30mA linear charger ON
Thermal regulation comparator; when=1 and T_145=0, the charge current is limited
to 22.1mV across RSENSE
4
T_120
R
See
Table 19
3
2
1
ICHG
IBUS
R
R
R
0 indicates the ICHARGE loop is controlling the battery charge current
0 indicates the IBUS (input current) loop is controlling the battery charge current
1 indicates VBUS has passed validation and is capable of charging
VBUS_VALID
1 indicates the constant-voltage loop (OREG) is controlling the charger and all
current limiting loops have released
0
CV
R
© 2009 Fairchild Semiconductor Corporation
FAN5400 Family • Rev. 1.0.7
www.fairchildsemi.com
34
PCB Layout Recommendations
Bypass capacitors should be placed as close to the IC as
possible. In particular, the total loop length for CMID should
be minimized to reduce overshoot and ringing on the SW,
PMID, and VBUS pins. All power and ground pins must be
routed to their bypass capacitors using top copper if
possible. Copper area connecting to the IC should be
maximized to improve thermal performance.
Figure 51. PCB Layout Recommendations
© 2009 Fairchild Semiconductor Corporation
FAN5400 Family • Rev. 1.0.7
www.fairchildsemi.com
35
Physical Dimensions
F
BALL A1
E
A
INDEX AREA
1.20
B
Ø0.20
Cu Pad
0.03 C
2X
A1
1.60
D
0.40
Ø0.30 Solder
Mask Opening
0.40
0.03 C
2X
TOP VIEW
RECOMMENDED LAND PATTERN
(NSMD TYPE)
0.06 C
0.625
0.547
0.378±0.018
0.208±0.021
E
0.05 C
C
D
SEATING PLANE
SIDE VIEWS
NOTES:
A. NO JEDEC REGISTRATION APPLIES.
B. DIMENSIONS ARE IN MILLIMETERS.
0.005
C A B
1.20
Ø0.260±0.02
20X
0.40
C. DIMENSIONS AND TOLERANCE
PER ASMEY14.5M, 1994.
E
D
C
B
1.60
D. DATUM C IS DEFINED BY THE SPHERICAL
CROWNS OF THE BALLS.
(Y) ±0.018
F
0.40
A
E. PACKAGE NOMINAL HEIGHT IS 586 MICRONS
±39 MICRONS (547-625 MICRONS).
2
3
4
1
(X) ±0.018
F. FOR DIMENSIONS D, E, X, AND Y SEE
PRODUCT DATASHEET.
BOTTOM VIEW
G. DRAWING FILNAME: MKT-UC020AArev2.
Figure 52. 20-Ball WLCSP, 4X5 Array, 0.4mm Pitch, 250µm Ball
Product-Specific Dimensions
Product
D
E
X
Y
FAN540XUCX
1.960 +0.030
1.870 +0.030
0.335
0.180
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without
notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most
recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty
therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2009 Fairchild Semiconductor Corporation
FAN5400 Family • Rev. 1.0.7
www.fairchildsemi.com
36
© 2009 Fairchild Semiconductor Corporation
FAN5400 Family • Rev. 1.0.7
www.fairchildsemi.com
37
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