FAN6757MRMX_技术文档

November 2013

FAN6757— mWSaver® PWM Controller

Features

Description

The FAN6757 is a next-generation Green Mode PWM

controller with innovative mWSaver® technology, which

dramatically reduces standby and no-load power

consumption, enabling conformance to worldwide

Standby Mode efficiency guidelines.

An innovative AX-CAP^®method minimizes losses in the

EMI filter stage by eliminating X-cap discharge resistors

while meeting IEC61010-1 safety requirements.

.

Single-Ended Topologies, such as Flyback and

Forward Converters

.

mWSaver® Technology

- Achieves Low No-Load Power Consumption:

<50 mW at 230 V_AC(EMI Filter Loss Included)

- Eliminates X Capacitor Discharge Resistor Loss

with AX-CAP^®Technology

- Linearly Decreases Switching Frequency

Protections ensure safe operation of the power system

in various abnormal conditions. A proprietary frequency-

hopping function decreases EMI emission. Built-in

synchronized slope compensation allows more stable

Peak-Current-Mode control over a wide range of input

voltage and load conditions. The proprietary internal line

compensation ensures constant output power limit over

the entire universal line voltage range.

to 23 kHz

- Burst Mode Operation at Light-Load Condition

- 500 V High-Voltage JFET Startup Circuit to

Eliminate Startup Resistor Loss

.

Highly Integrated with Rich Features

- Proprietary Frequency Hopping to Reduce EMI

- High-Voltage Sampling to Detect Input Voltage

Requiring a minimum number of external components,

FAN6757 provides a basic platform that is well suited for

cost-effective flyback converter designs that require

extremely low standby power consumption.

- Peak-Current-Mode Control with Slope

Compensation

- Cycle-by-Cycle Current Limiting with Line

Applications

Compensation

- Leading-Edge Blanking (LEB)

- Built-In 7 ms Soft-Start

Flyback power supplies that demand extremely low

standby power consumption, such as:

.

Advanced Protections

.

Adapters for Notebooks, Printers, Game Consoles

- Brown-In/Brownout Recovery

Open-Frame SMPS for LCD TV, LCD Monitors,

Printers

- Internal Overload / Open-Loop Protection (OLP)

- V_DDUnder-Voltage Lockout (UVLO)

- V_DDOver-Voltage Protection (V_DDOVP)

- Over-Temperature Protection (OTP)

- Current-Sense Short-Circuit Protection (SSCP)

Ordering Information

Protections⁽¹⁾

Operating

Temperature Range

Packing

Method

Part Number

OLP

Package

OVP

OTP SSCP

A/R

8-Pin, Small-Outline

Package (SOP)

Tape &

Reel

FAN6757MRMX

A/R

L

-40 to +105°C

Note:

1. A/R = Auto Recovery Mode protection, L = Latch Mode protection.

www.fairchildsemi.com

FAN6757 • Rev. 1.0.1

Application Diagram

+

VAC

V_O

-

FAN6757

1

2

GND

GATE

VDD

8

7

FB

3

4

NC

HV

SENSE

RT

6

5

Figure 1. Typical Application

Internal Block Diagram

NC

3

HV

4

VDDOVP

Latch

OTP

SSCP

OLP

Line

Sensing

Re-Start

Protection

Brownout Function

Soft

Driver

High/Low Line

Compensation

8

GATE

V_Limit

V_PWM

S

R

Q

OSC

Internal

BIAS

SSCP

Comparator

VDD

7

VSSCP-H/L

SSCP

UVLO

t_D-SSCP

V_RESET

…

Soft-Start

Comparator

V_DD-ON

V_RESTART

/

Pattern

Generator

Soft-Start

V_Limit

Current Limit

Comparator

V_RESET

Blanking

Circuit

SENSE

6

Green

Mode

VDD

OVP

t_D-VDDOVP

PWM

Comparator

V_DD-OVP

V_FB-OPEN

Max.

Duty

Slope

V_PWM

Compensation

I_RT

Z_FB

RT

5

t_D-OTP1

3R

R

OTP

FB

2

OLP

t_D-OLP

V_RTTH1

OLP

Comparator

t_D-OTP2

V_RTTH2

V_FB-OLP

1

GND

Figure 2. Functional Block Diagram

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FAN6757 • Rev. 1.0.1

2

Marking Information

Z - Plant Code

X - 1-Digit Year Code

Y - 1-Digit Week Code

TT - 2-Digit Die Run Code

T - Package Type (M=SOP)

M - Manufacture Flow Code

ZXYTT

6757

TM

Figure 3. Top Mark

Pin Configuration

SOP-8

GND

FB

1

2

3

4

8

7

6

5

GATE

VDD

SENSE

RT

NC

HV

Figure 4. Pin Configuration (Top View)

Pin Definitions

Pin #

Name

Description

Ground. This pin is used for the ground potential of all the pins. A 0.1 µF decoupling capacitor

placed between VDD and GND is recommended.

1

GND

Feedback. The output voltage feedback information from the external compensation circuit is fed

into this pin. The PWM duty cycle is determined from this pin and the current-sense signal from

Pin 6. The FAN6757 performs open-loop protection: if the FB voltage is higher than a threshold

voltage (around 4.6 V) for more than 57.5 ms, the controller latches off the PWM.

2

3

FB

NC

No connection

High-Voltage Startup. This pin is connected to the line input or bulk capacitor, via 200 kΩ

resistors, to achieve brownout and high/low line compensation. If the voltage of the HV pin is

lower than the brownout voltage (AC line peak voltage less than 100 V) and lasts for 65 ms,

PWM output turns off. High/low line compensation dominates the OCP level and cycle-by-cycle

current limit, to solve the unequal OCP level and power-limit problems under universal input.

4

HV

Over-Temperature Protection. An external NTC thermistor is connected from this pin to the

GND pin. The impedance of the NTC thermistor decreases at high temperatures. Once the

voltage of the RT pin drops below the threshold voltage, the controller latches off the PWM. If the

RT pin is not connected to an NTC resistor for over-temperature protection, it is recommended to

place one 100 kΩ resistor to ground to prevent from noise interference. This pin is limited by an

internal clamping circuit.

5

RT

Current Sense. The sensed voltage is used for peak-current-mode control and cycle-by-cycle

current limiting.

6

7

8

SENSE

VDD

Power Supply. The internal protection circuit disables PWM output as long as V_DDexceeds the

OVP trigger point.

Gate Drive Output. The totem-pole output driver for the power MOSFET. It is internally clamped

below 14.5 V.

GATE

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FAN6757 • Rev. 1.0.1

3

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only.

Symbol

V_VDD

Parameter

Min.

Max.

Units

DC Supply Voltage^(1,2)

FB Pin Input Voltage

30

7.0

V

V_FB

-0.3

V_SENSESENSE Pin Input Voltage

7.0

V

V_RT

V_HV

P_D

RT Pin Input Voltage

7.0

V

HV Pin Input Voltage

500

400

150

+125

+150

+260

6.5

V

Power Dissipation (T_A＜50°C)

mW

ϴ_JA

T_J

Thermal Resistance (Junction-to-Air)

Operating Junction Temperature

C/W

C

-40

-55

T_STG

T_L

Storage Temperature Range

C

Lead Temperature (Wave Soldering or IR, 10 Seconds)

C

Human Body Model, JEDEC:JESD22-A114

Charged Device Model, JEDEC:JESD22-C101 All Pins except HV Pin⁽³⁾

All Pins except HV Pin⁽³⁾

ESD

kV

2.0

Notes:

1. All voltage values, except differential voltages, are given with respect to the network ground terminal.

2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.

3. ESD level on the HV pin is CDM=1 kV and HBM=1 kV.

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. We does not

recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol

Parameter

Resistance on HV Pin

Min.

Typ.

Max.

Unit

R_HV

150

200

250

kΩ

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FAN6757 • Rev. 1.0.1

4

Electrical Characteristics

V_DD=15 V and T_J=T_A=25C unless otherwise noted.

Symbol

Parameter

Conditions

Min.

Typ. Max. Unit

V_DDSection

V_DD-ON

Threshold Voltage to Startup

V_DDRising

16

17

18

V

Threshold Voltage to Stop Switching in

Normal Mode

V_UVLO

V_DDFalling

5.5

6.5

7.5

Threshold Voltage to enable HV Startup

to Charge V_DDin Normal Mode

V_RESTART

V_DD-OFF

V_DD-OLP

V_DD-LH

4.7

11

7

V

Threshold Voltage to Stop Operating in

Protection Mode

10

6

12

8

Threshold Voltage to Enable HV Startup

to Charge V_DDin Protection Mode

Threshold Voltage to Release Latch

Mode

3.5

4.0

4.5

Minimum Voltage of VDD Pin for

Enabling Brown-in to Avoid Startup Fail

V_UVLOV_UVLOV_UVLO

V_DD-AC

I_DD-ST

V

+2.5

+3.0

+3.5

Startup Current

V_DD=V_DD-ON– 0.16 V

30

µA

mA

V_DD=15 V, V_FB=3 V,

Gate Open

I_DD-OP1

Supply Current in PWM Operation

1.8

800

190

V_DD=15 V, V_FB<1.4 V,

Gate Off

I_DD-OP2

I_DD-OLP

I_LH

Supply Current when PWM Stops

µA

V

Internal Sink Current when V_DD-

_OLP<V_DD<V_DD-OFFin Protection Mode

V_DD= V_DD-OLP+ 0.1 V

V_DD= 5 V

90

30

140

Internal Sink Current when V_DD<V_DD-OLP

in Latch-Protection Mode

Threshold Voltage for V_DDOver-Voltage

Protection

V_DD-OVP

23.5

110

24.5

205

25.5

300

V_DDOver-Voltage Protection Debounce

Time

t_D-VDDOVP

HV Section

I_HV

µs

V_AC=90 V (V_DC=120 V),

V_DD=0 V

Inherent Current Limit of HV Pin

Threshold Voltage for Brownout

Threshold Voltage for Brown-In

V_AC-ON– V_AC-OFF

1.50

90

3.25

100

110

5.00

110

120

mA

V

DC Source Series,

R=200 kΩ to HV Pin

V_AC-OFF

V_AC-ON

△V_AC

DC Source Series,

R=200 kΩ to HV Pin

100

V

DC Source Series,

R=200 kΩ to HV Pin

8

12

65

16

90

V

t_D-AC-OFFDebounce Time for Brownout

40

95

ms

Work Period of HV-Sampling Circuit in

Standby Mode

t_S-WORK

V_FB<V_FB-ZDC

140

185

Rest Period of HV-Sampling Circuit in

Standby Mode

t_S-REST

V_FB<V_FB-ZDC

180

V_DC

260

V_DC

320

V_DC

ms

V

V_HV-DIS

HV Discharge Threshold

R_HV=200 kΩ to HV Pin

×0.45 ×0.51 ×0.56

t_D-HV-DIS

t_HV-DIS

Debounce Time for HV Discharge

HV Discharge Time

75

115

510

155

660

ms

360

Continued on the following page…

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FAN6757 • Rev. 1.0.1

5

Electrical Characteristics

V_DD=15 V and T_J=T_A=25C unless otherwise noted.

Symbol

Parameter

Conditions

Min.

Typ. Max. Unit

Oscillator Section

Center Frequency

Hopping Range (V_FB>V_FB-N

V_FB>V_FB-G

62

65

68

f_OSC

t_HOP

Frequency in Normal Mode

Hopping Period

kHz

ms

)

±3.55 ±4.25 ±4.95

5.12

20

6.40

23

7.68

26

Center Frequency

Hopping Range (Increase

V_FBfrom V_FB-GUntil Hopping ±1.25 ±1.50 ±1.75

Starts)

f_OSC-G

Green-Mode Frequency

kHz

f_DV

f_DT

Frequency Variation vs. V_DDDeviation

V_DD=11 V to 22 V

5

%

Frequency Variation vs. Temperature

Deviation

5

T_A=-40 to 105C

Feedback Input Section

Input Voltage to Current-Sense

Attenuation

A_V

1/4.50 1/3.75 1/3.00

V/V

Z_FB

Pull High Impedance at Normal Mode

17

5.2

4.3

45.0

2.6

2.1

19

5.4

4.6

57.5

2.8

2.3

21

5.6

4.9

70.0

3.0

2.5

kΩ

V

V_FB-OPENOutput High Voltage

FB Pin Open

V_FB-OLP

t_D-OLP

V_FB-N

FB Open-Loop Trigger Level

V

Delay of FB Pin Open-Loop Protection

Green-Mode Entry FB Voltage

ms

V

V_FB-G

Green-Mode Ending FB Voltage

V

FB Threshold Voltage for Zero-Duty

Recovery at Normal Mode

V_FB-ZDCR

V_FB-ZDC

1.9

1.8

2.1

2.0

2.3

2.2

V

FB Threshold Voltage for Zero-Duty at

Normal Mode

Current-Sense Section

t_PD

Delay to Output

100

265

250

330

ns

t_LEB

Leading-Edge Blanking Time

200

Current Limit at Low Line

(V_AC-RMS=86 V)

V_DC=122 V,

Series R=200 kΩ to HV

V_LIMIT-L

V_LIMIT-H

V_SSCP-L

0.43

0.46

0.39

50

0.49

0.42

70

V

Current Limit at High Line

(V_AC-RMS=259 V)

V_DC=366 V,

Series R=200 kΩ to HV

0.36

30

Threshold Voltage for SENSE Short-

Circuit Protection

V_DC=122 V,

Series R=200 kΩ to HV

mV

Threshold Voltage for SENSE Short-

Circuit Protection

V_DC=366 V,

Series R=200 kΩ to HV

V_SSCP-H

t_ON-SSCP

t_D-SSCP

t_SS

80

4.00

110

5

100

4.55

170

7

120

5.10

230

9

mV

µs

On Time for V_SSCP-(L/H)Checking

V_SENSE<V_SSCP-(L/H)

Startup Time

Debounce Time for SENSE Short-

Circuit Protection

µs

Soft-Startup Time

ms

Continued on the following page…

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FAN6757 • Rev. 1.0.1

6

Electrical Characteristics

V_DD=15 V and T_J=T_A=25C unless otherwise noted.

Symbol

Parameter

Conditions

Min.

Typ. Max. Unit

GATE Section

DCY_MAXMaximum Duty Cycle

75.0

82.5

90.0

1.5

%

V

V_GATE-L

Gate Low Voltage

V_DD=15 V, I_O=50 mA

V_DD=12 V, I_O=50 mA

V_DD=15 V, C_L=1 nF

V_DD=22 V

V_GATE-H

Gate High Voltage

8

85

V

t_r

t_f

Gate Rising Time (10~90%)

Gate Falling Time (10~90%)

110

40

135

50

ns

V

30

V_GATE-CLAMPGate Output Clamping Voltage

11.0

14.5

18.0

RT Section

I_RT

Output Current of RT Pin

100

µA

V

Threshold Voltage, Latch Protection

(Generally Used for External OTP

Triggering)

V

_RTTH2＜ V_RT＜V_RTTH1

,

V_RTTH1

1.000 1.035 1.070

After 14.5 ms Latch Off

Second Latch Protection Threshold

Voltage

V

_RTTH2＜ 0.7 V,

V_RTTH2

R_OTP

0.65

9.66

11.0

0.70

0.75

V

After 185 µs Latch Off

Value of V_RTTH1/I_RT

10.50 11.34

kΩ

ms

Debounce Time, First Latch Protection

Triggering

t_D-OTP1

V_RTTH2＜ V_RT＜ V_RTTH1

14.5

185

18.0

260

Debounce Time, Second Latch

Protection Triggering

t_D-OTP2

V_RT< V_RTTH2

110

µs

Over-Temperature Protection Section (OTP)

T_OTPProtection Junction Temperature

+135

°C

T_OTP

-

T_RESTARTRestart Junction Temperature

25

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FAN6757 • Rev. 1.0.1

7

Typical Characteristics

6.0

5.5

5.0

4.5

4.0

3.5

3.0

11.4

11.2

11.0

10.8

10.6

10.4

10.2

10.0

9.8

9.6

-40 -30 -15

0

25 50 75 85 100 125

-40 -30 -15

0

25 50 75 85 100 125

Temperature (ºC)

Figure 5. V_RESTARTvs. Temperature

Figure 6. V_DD-OFFvs. Temperature

9.0

8.5

8.0

7.5

7.0

6.5

6.0

5.5

5.0

8

7

6

5

4

3

2

1

0

-40 -30 -15

0

25 50 75 85 100 125

-40 -30 -15

0

25 50 75 85 100 125

Temperature (ºC)

Figure 7. V_DD-OLPvs. Temperature

Figure 8. V_DD-LHvs. Temperature

70

65

60

55

50

45

40

35

30

100

90

80

70

60

50

40

30

20

10

0

-40 -30 -15

0

25 50 75 85 100 125

Temperature (ºC)

-40 -30 -15

0

25 50 75 85 100 125

Temperature (ºC)

Figure 9. T_D-OLPvs. Temperature

Figure 10.I_LHvs. Temperature

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FAN6757 • Rev. 1.0.1

8

Typical Characteristics

120

118

116

114

112

110

108

106

104

102

100

115

110

105

100

95

90

85

80

-40 -30 -15

0

25 50 75 85 100 125

-40 -30 -15

0

25 50 75 85 100 125

Temperature (ºC)

Figure 11.V_AC-ONvs. Temperature

Figure 12.V_AC-OFFvs. Temperature

80

75

70

65

60

55

50

6.0

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

-40 -30 -15

0

25 50 75 85 100 125

-40 -30 -15

0

25 50 75 85 100 125

Temperature (ºC)

Figure 13.f_OSCvs. Temperature

Figure 14.1/AV vs. Temperature

21.0

20.5

20.0

19.5

19.0

18.5

18.0

17.5

17.0

16.5

16.0

6.0

5.9

5.8

5.7

5.6

5.5

5.4

5.3

5.2

5.1

5.0

-40 -30 -15

0

25 50 75 85 100 125

-40 -30 -15

0

25 50 75 85 100 125

Temperature (ºC)

Figure 15.Z_FBvs. Temperature

Figure 16.V_FB-OPENvs. Temperature

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FAN6757 • Rev. 1.0.1

9

Typical Characteristics

100

90

80

70

60

50

40

30

0.60

0.55

0.50

0.45

0.40

0.35

0.30

-40 -30 -15

0

25 50 75 85 100 125

-40 -30 -15

0

25 50 75 85 100 125

Temperature (ºC)

Figure 17. DCY_MAXvs. Temperature

Figure 18.V_LIMIT-Lvs. Temperature

0.60

0.55

0.50

0.45

0.40

0.35

0.30

0.25

0.20

380

360

340

320

300

280

260

240

220

200

-40 -30 -15

0

25 50 75 85 100 125

-40 -30 -15

0

25 50 75 85 100 125

Temperature (ºC)

Figure 19.V_LIMIT-Hvs. Temperature

Figure 20.t_LEBvs. Temperature

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FAN6757 • Rev. 1.0.1

10

Functional Description

Current Mode Control

switching, reducing switching loss for lower power

consumption, as shown in Figure 23.

FAN6757 employs peak current-mode control, as shown

in Figure 21. An opto-coupler (such as the H11A817A)

and a shunt regulator (such as the KA431) are typically

used to implement the feedback network. Comparing

the feedback voltage with the voltage across the R_sense

resistor makes it possible to control the switching duty

cycle. The built-in slope compensation stabilizes the

current loop and prevents sub-harmonic oscillation.

V_O

V_FB

V_FB.ZDCR

V_FB.ZDC

5.4 V

I_Drain

V_O

Z_FB

FB

2

PWM

3R

Switching

Disabled

Switching

Disabled

Comparator

GATE

Gate

driver

KA431

8

Figure 23. Burst Switching in Green Mode

R

Operating Current

SENSE

+

Secondary

side

6

Primary side

In normal conditions, operating current is less than

1.8 mA (I_DD-OP1). When V_FB<1.4 V, operating current is

further reduced below 800 µA (I_DD-OP2) by disabling

several blocks of the FAN6757. The low operating

current improves light-load efficiency and reduces the

requirement of V_DDhold-up capacitance.

+

Slope

compensatin

Figure 21. Current Mode Control Circuit Diagram

Green-Mode Operation

High-Voltage Startup and Line Sensing

The FAN6757 modulates the PWM frequency as a

function of the FB voltage to improve the medium- and

light-load efficiency, as shown in Figure 22. Since the

output power is proportional to the FB voltage in current-

mode control, the switching frequency decreases as

load decreases. In heavy-load conditions, the switching

frequency is fixed at 65 kHz. Once V_FBdecreases below

V_FB-N(2.8 V), the PWM frequency starts linearly

decreasing from 65 kHz to 23 kHz to reduce switching

losses. As V_FBdrops to V_FB-G(2.3 V), where switching

frequency is decreased to 23 kHz, the switching

frequency is fixed to avoid acoustic noise.

The HV pin is typically connected to the AC line input

through two external diodes and one resistor (R_HV), as

shown in Figure 24. When the AC line voltage is

applied, the V_DDhold-up capacitor is charged by the line

voltage through the diodes and resistor. After V_DD

reaches the turn-on threshold voltage (V_DD-ON), the

startup circuit charging V_DDcapacitor is switched off and

V_DDis supplied by the auxiliary winding of the

transformer. Once the FAN6757 starts up, it continues

operation until V_DDdrops below 6.5 V (V_UVLO). The IC

startup time with a given AC line input voltage is:

2 2

f_S

V_ACIN





t_STARTUP R_HVC_DDln

(1)

f_OSC

2 2

V_ACIN



V_DDON



R_HV

HV

4

f_OSC-G

7

+

VDD

Good

VDD

-

V_FB-ZDCV_FB-ZDCRV_FB-G

V_FB-N

V_FB

C_DD

V_DD-ON

/

V_RESTART

Figure 22. V_FBvs. PWM Frequency

C_X

R_LS

When V_FBfalls below V_FB-ZDC(2.0 V) as load decreases

further, the FAN6757 enters Burst Mode operation,

where PWM switching is disabled. Then the output

voltage starts to drop, causing the feedback voltage to

rise. Once V_FBrises above V_FB-ZDCR(2.1 V), switching

resumes. Burst Mode alternately enables and disables

Sampling

Circuit

Brown-in/out

Function

AC Line

V_LIMIT

V_OCP

High/ Low Line

Compensation

Figure 24. Startup Circuit

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FAN6757 • Rev. 1.0.1

11

The HV pin detects the AC line voltage using a switched

voltage divider consisting of an external resistor (R_HV

increases. The current-limit level is also proportional to

the R_HVresistor value and the power-limit level can be

tuned using the R_HVresistor.

)

and an internal resistor (R_LS), as shown in Figure 24.

The internal line-sensing circuit detects line voltage

using a sampling circuit and a peak-detection circuit.

Since the voltage divider causes power consumption

when it is switched on, the switching is driven by a

signal with a very narrow pulse width to minimize power

loss. The sampling frequency is also adaptively

changed according to the load condition to minimize

power consumption in light-load condition.

5.4 V

Z_FB

PWM

3R

Comparator

2

OSC

FB

SS

comparator

R

GATE

Q

S

R

DRV

8

V_SS

+

Based on the detected line voltage, brown-in and

brownout thresholds are determined as:

+

Slope

compensation

V_LIMIT

Current limit

comparator

SENSE

HV

R_HVV_{AC ON}

Line

Sensing

Power Limit Line

Compensation

6

V_BROWN-IN(RMS) 

V_BROWN-OUT(RMS) 



4

(2)

(3)

200k

2

R_HVV_{AC OFF}



Figure 25. Pulse-by-pulse Current Limit Circuit

200k

2

V_LIMIT(V)

0.5

Since the internal resistor (R_LS=1.62 kΩ) of the voltage

divider is much smaller than R_HV, the thresholds are

given as a function of R_HV

.

0.45

Note that V_DDmust be larger than V_DD-ACto start up,

even though sensed line voltage satisfies Equation 2.

R_HV=240 kΩ

AX-CAP^®Discharge

R_HV=200 kΩ

0.4

The EMI filter in the front end of the Switched-Mode

Power Supply (SMPS) typically includes a capacitor

across the AC line connector. Most of the safety

regulations, such as UL 1950 and IEC61010-1, require

the capacitor be discharged to a safe level within a

given time when AC plug is removed from its receptacle.

Typically, discharge resistors across the capacitor are

used to ensure the capacitor is discharged naturally,

which introduces power loss as long as it is connected

to the receptacle.

R_HV=160 kΩ

0.35

0.3

70

110

150

190

230

270

Line Voltage (V_AC

)

Figure 26. Current Limit vs. Line Voltage

The innovative AX-CAP^®technology intelligently

discharges the filter capacitor only when the power

supply is unplugged from the power outlet. Since the

AX-CAP^®discharge circuit is disabled in normal

operation, the power loss in the EMI filter can be

virtually removed.

Under-Voltage Lockout (UVLO)

As shown in Figure 27, as long as protection is not

triggered, the turn-off threshold of V_DDis fixed internally

at V_UVLO(6.5 V). When Protection Mode is triggered, the

V_DDlevel to terminate PWM gate switching is changed

to V_DD-OFF(11 V), as shown in Figure 28. When V_DD

drops below V_DD-OFF, switching is terminated and the

operating current from VDD is reduced to I_DD-OLPto slow

The discharge of the capacitor is achieved through the

HV pin. Once AC outlet detaching is detected, the

FAN6757 discharges the capacitor across the AC line

connector by the external resistor on the HV pin.

down the discharge of VDD until V_DDreaches V_DD-OLP

.

This delays re-startup after shutdown by protection to

minimize the input power and voltage/current stress of

switching devices during fault condition.

High/Low Line Compensation for Constant

Power Limit

FAN6757 has pulse-by-pulse current limit, as shown in

Figure 25, to limit the maximum input power with a given

input voltage. If the output consumes beyond this

maximum power, the output voltage drops triggering the

overload protection.

V_DD

V_DD-ON

17 V

6.5 V

4.7 V

V_UVLO

V_RESTART

As shown in Figure 25, the high/low line compensation

block adjusts the current-limit level, V_LIMIT, based on the

line voltage. Figure 26 shows how the pulse-by-pulse

current-limit level changes with the line voltage for

different R_HVresistors. To maintain the constant output

power limit regardless of line voltage, the cycle-by-cycle

current-limit level, V_LIMIT, decreases as line voltage

GATE

t

Figure 27. V_DDUVLO at Normal Mode

www.fairchildsemi.com

FAN6757 • Rev. 1.0.1

12

function. For OTP applications, an NTC thermistor,

R_NTC, usually in series with a resistor R_A, is connected

between the RT pin and ground. The internal current

source, I_RT, (100 µA) introduces voltage on RT as:

V_DD

17 V

V_DD-ON

11 V

7 V

V_RTI_RT(R_NTCR_A)

(4)

V_DD-OFF

V_DD-OLP

At high ambient temperature, R_NTCdecreases reducing

V_RT. When V_RTis lower than V_RTTH1(1.035 V) for longer

than t_D-OTP1(14.5 ms), the protection is triggered and the

FAN6757 enters latch mode protection.

GATE

The OTP can be also trigged by pulling down the RT pin

voltage using an opto-coupler or transistor. Once V_RTis

less than V_RTTH2(0.7 V) for longer than t_D-OTP2(185 µs),

the protection is triggered and latch mode protection

begins.

t

Figure 28. V_DDUVLO at Protection Mode

Leading-Edge Blanking (LEB)

When OTP is not used, it is recommended to place a

10 kΩ resistor between this pin and ground to prevent

noise interference.

Each time the power MOSFET is switched on, a turn-on

spike occurs on the sense resistor. To avoid premature

termination of the switching pulse, a leading-edge

blanking time, t_LEB, is introduced. During this blanking

period, the current-limit comparator is disabled and

cannot switch off the gate driver.

Sense-Pin Short-Circuit Protection

FAN6757 provides safety protection for Limited Power

Source (LPS) test. When the current-sense resistor is

short circuited by a soldering defect during production,

the current-sensing information is not properly obtained,

which results in unstable operation of the power supply.

Gate Output / Soft Driving

The BiCMOS output stage has a fast totem-pole gate

driver. The output driver is clamped by an internal

14.5 V Zener diode to protect power MOSFET gate from

over voltage. A soft driving is implemented to minimize

electromagnetic interference (EMI) by reducing the

switching noise.

To protect the power supply against a short circuit

across the current-sense resistor, the FAN6757 shuts

down when the current-sense voltage is very low, even

with a relatively large duty cycle. As shown in Figure 29,

the current-sense voltage is sampled t_ON-SSCP(4.55 µs)

after the gate turn-on. If the sampled voltage (V_S-CS) is

lower than V_SSCPfor 11 consecutive switching cycles

(170 µs), the FAN6757 shuts down immediately. V_SSCP

varies linearly with the line voltage. At 122 V DC input, it

is typically 50 mV (V_SSCP-L); while at 366 V DC, it is

typically100 mV (V_SSCP-H).

V_DDOver-Voltage Protection (OVP)

V_DDover-voltage protection prevents IC damage from

over-voltage exceeding the IC voltage rating. When the

V_DDvoltage exceeds 24.5 V, the protection is triggered.

This protection is typically caused by open circuit of the

secondary-side feedback network.

t_D-SSCP

Soft-Start

An internal soft-start circuit progressively increases the

pulse-by-pulse current-limit level of the MOSFET for

7 ms during startup to establish the correct working

conditions for the transformers and capacitors.

V_S-CS

V_SENSE

GATE

Over-Temperature Protection (OTP)

t_ON-SSCP

Figure 29. Timing Diagram of SSCP

The RT pin provides adjustable Over-Temperature

Protection (OTP) and an external latch triggering

www.fairchildsemi.com

FAN6757 • Rev. 1.0.1

13

Typical Application Circuit

Application

PWM Controller

Input Voltage Range

Output

65 W Notebook Adapter

FAN6757MRMX

85 V_AC~ 265 V_AC

19 V, 3.42 A

X-cap

0.33F/275V

BD1

C_DOR_DO

1nF/100V 23.5

2A/600V

L_O

1.5H

TF1

510H

+

V_AC

ZD_SN

P6KE150A

D_O

20A/150V

C_O1

C_O2

V_O

1000F/

25V

470F/

25V

D_SN

FR107

C_IN

120F/

400V

-

1N4007

Q₁

FQPF7N65C

R_G

20

R_SENSE

0.176

R_HV

200k

FAN6757

R_LPF

100

1

2

GND

GATE

VDD

8

7

R_D

1.2k

FB

R₁

200k

3

4

NC

HV

SENSE

RT

6

5

C_LPF

470pF

PC817A

R_F

4.7k

C_F

2.2nF

C_FB

1nF

D_DD

1N4935

R_A

5.6k

C_DD

47F/ 50V

KA431

R_NTC

100k

R₂

30k

Figure 30. Schematic of Typical Application Circuit

Transformer Schematic Diagram

.

Core: Ferrite Core RM-10

Bobbin: RM-10

RM-10

4

3-Layer Tape

S

F

N4

N₁

5

3-Layer Tape

Shielding

1-Layer Tape

N₂

N3

N2

N₄

6

3-Layer Tape

Shielding

1-Layer Tape

7

N1

N₃

9

Bobbin

Figure 31. Transformer Specification

www.fairchildsemi.com

FAN6757 • Rev. 1.0.1

14

Winding Specification

Pin (Start → Finish)

Wire

Turns

Winding Method

Remark

N1

4 → 5

0.5φ×1

19

Solenoid Winding

Enameled Copper Wire

Insulation: Polyester Tape, t = 0.025 mm, 1 Layer

Shielding: Adhesive Tape of Copper Foil, t = 0.025×7 mm, 1.2 Layers, Open Loop, Connected to Pin 4

Insulation: Polyester Tape t = 0.025 mm, 3 Layers

N2

Insulation: Polyester Tape, t = 0.025mm, 3 Layers

N3 9 → 7 0.4φ×1

Insulation: Polyester Tape, t = 0.025 mm, 1 Layer

S → F

0.9φ×1

8

Solenoid Winding

Triple Insulated Wire

7

Solenoid Winding

Enameled Copper Wire

Shielding: Adhesive Tape of Copper Foil, t = 0.025×7 mm, 1.2 Layers, Open Loop, Connected to Pin 4

Insulation: Polyester Tape t = 0.025 mm, 3 Layers

N4

5 → 6

0.5φ×1

19

Solenoid Winding

Enameled Copper Wire

Insulation: Polyester Tape t = 0.025 mm, 3 Layers

Electrical Characteristics

Specification

510 H ±5%

Remark

1 kHz, 1 V

Primary-Side Inductance

4－6

Primary-Side Effective Leakage Inductance

Short All Other Pins

20 H Maximum

Typical Performance

Table 1. Power Consumption

Input Voltage

Output Power

Actual Output Power

Input Power

Specification

No Load

0.25 W

0.5 W

0 W

0.045 W

0.360 W

0.711 W

Input Power < 0.05 W

Input Power < 0.5 W

Input Power < 1 W

230 V_AC

0.255 W

0.521 W

Table 2. Efficiency

Output Power

16.25 W

32.5 W

48.75 W

86.92%

87.82%

65 W

Average

115 V 60 Hz

230 V 50 Hz

87.84%

87.88%

87.42%

87.95%

86.23%

87.69%

87.10%

87.83%

www.fairchildsemi.com

FAN6757 • Rev. 1.0.1

15

Physical Dimensions

5.00

4.80

A

0.65

3.81

8

5

B

1.75

6.20

5.80

4.00

3.80

5.60

1

4

PIN ONE

INDICATOR

1.27

(0.33)

0.25

C B A

LAND PATTERN RECOMMENDATION

SEE DETAIL A

0.25

0.10

0.25

0.19

C

1.75 MAX

0.10

0.51

0.33

OPTION A - BEVEL EDGE

0.50

0.25

x 45°

R0.10

GAGE PLANE

OPTION B - NO BEVEL EDGE

0.36

NOTES: UNLESS OTHERWISE SPECIFIED

8°

0°

0.90

0.40

A) THIS PACKAGE CONFORMS TO JEDEC

MS-012, VARIATION AA.

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS DO NOT INCLUDE MOLD

FLASH OR BURRS.

D) LANDPATTERN STANDARD: SOIC127P600X175-8M.

E) DRAWING FILENAME: M08Arev14

F) FAIRCHILD SEMICONDUCTOR.

SEATING PLANE

(1.04)

DETAIL A

SCALE: 2:1

Figure 32. 8-Pin, SOP-8 Package

Package drawings are provided as a service to customers considering our components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact our representative to verify or obtain the most recent

revision. Package specifications do not expand the terms of our worldwide terms and conditions, specifically the warranty therein,

which covers our products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/dwg/M0/M08A.pdf.

FAN6757 • Rev. 1.0.1

16

FAN6757 • Rev. 1.0.1

17


型号：	FAN6757MRMX
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	Switching Controller, Current-mode, 68kHz Switching Freq-Max, PDSO8 开关光电二极管
文件：	总17页 (文件大小：1345K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

FAN6757MRMX [FAIRCHILD]

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