FAN7317MX [FAIRCHILD]
LCD Backlight Inverter Drive IC; LCD背光逆变器驱动IC型号: | FAN7317MX |
厂家: | FAIRCHILD SEMICONDUCTOR |
描述: | LCD Backlight Inverter Drive IC |
文件: | 总23页 (文件大小:1860K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
January 2008
FAN7317
LCD Backlight Inverter Drive IC
Features
Description
The FAN7317 is a LCD backlight inverter drive IC that
controls P-N full-bridge topology by using the new
patented phase-shift method.
High-Efficiency Single-Stage Power Conversion
Wide Input Voltage Range: 6V to 24V
Backlight Lamp Ballast and Soft Dimming
Minimal Required External Components
Precision Voltage Reference Trimmed to 2%
ZVS Full-Bridge Topology
Soft-Start
The FAN7317 provides a low-cost solution and reduces
external components by integrating full wave rectifiers for
open-lamp protection and regulation (patent pending).
The operating voltage range of the FAN7317 is wide, so
an external regulator isn’t necessary to supply the
voltage to the IC.
PWM Control at Fixed Frequency
Burst Dimming Function
Programmable Striking Frequency
Open-Lamp Protection
The FAN7317 provides various protections, such as
open-lamp regulation, open-lamp protection, arc
protection, short-Lamp protection, CMP-high protection,
and FB-high protection, to increase the system reliability.
The FAN7317 provides burst dimming function and
analog dimming is possible, in a narrow range, by adding
some external components.
Open-Lamp Regulation
Arc Protection
Short-Lamp Protection
CMP-High Protection
The FAN7317 is available in a 20-SOIC package.
High-FB Protection
Thermal Shutdown
20-Pin SOIC
Applications
LCD TV
LCD Monitor
Ordering Information
Part Number
Package
Operating Temperature
Packing Method
FAN7317M
20-SOIC
20-SOIC
-25 to +85°C
-25 to +85°C
RAIL
FAN7317MX
TAPE & REEL
All packages are lead free per JEDEC: J-STD-020B standard.
Protected under U.S. patent nos. 5,652,479 and 7,158,390.
© 2007 Fairchild Semiconductor Corporation
FAN7317 • 1.0.2
www.fairchildsemi.com
Block Diagram
Short Lamp Protection
Min.
-
Disable @ striking
1ms delay (operation
@ burst dimming on)
0.3V
+
OLR1
OLR2
OUTA
OUTB
Arc Protection
TSD 150oC
+
-
3V
2V
Protection
Min. &
Max.
Detector
/Full Wave
Recifier
Over-Voltage Protection
Output Driver
7V 0.2A/0.3A
dead time
Disable @ striking
OLR output 32 count
@ normal
Reset by BCT edge
detect
Max.
+
-
200ns
OLR3
OLR4
+
1.6s delay @ striking
10ms delay @ normal
2V
OUTC
OUTD
-
0μA
+
1μA
1.8V
-
Error. Amp. source
current change
Gm Amp.
-
Open Lamp Regulation
2.2V
+
Gm = 350, Max. current 85μA
Oscillator
max. 2V
Control
Logic
On @ striking
min. 0.5V
CT
-
GND
+
CMP
Error. Amp. source
current change
0μA sink current @ striking
-
UVLO 5.5V
Error Amp.
High CMP Protection
disable @ striking
1.35V
Linear region 0~4V
+
-
+
VIN
+
Hys. 0.45V
High_CMP
3V
-
-
1.35V
+
52μA burst
sink current on
ENA
High FB Protection
disable @ striking
200k
+
OLP max.
High_FB
3.5V
-
Striking off
Voltage Reference
& Internal Bias
5V, max. 3mA
OLP1
OLP2
OLP3
OLP4
REF
4 Output
Pulses
Counter
Min. & Max.
max. 2V
Detector
/Full Wave
Rectifier
OLP
min. 0.5V
-
BCT
OLP min.
-
150μs
Delay
52μA burst
sink current on
1V/0.5V
Striking/normal
+
+
BDIM
Figure 1. Internal Block Diagram
© 2007 Fairchild Semiconductor Corporation
FAN7317 • 1.0.2
www.fairchildsemi.com
2
Pin Configuration
Figure 2. Package Diagram
© 2007 Fairchild Semiconductor Corporation
FAN7317 • 1.0.2
www.fairchildsemi.com
3
Pin Definitions
Pin #
Name
Description
This pin is 5V reference output. Typically, resistors are connected to this pin from CT pin
and BCT pin.
1
REF
This pin is the input for burst dimming. The voltage range of 0.5 to 2V at this pin controls
burst mode duty cycle from 0% to 100%.
2
3
BDIM
BCT
This pin is for programming the frequency of the burst dimming. Typically, a capacitor is
connected to this pin from ground and a resistor is connected to this pin from the REF pin.
This pin is for open-lamp protection and feedback control of lamp currents. It has the same
functions as other OLP pins and is connected to the full-wave rectifier internally. In striking
mode, if the minimum of rectified OLP inputs is less than 1V for 1.6s; or in normal mode, if
the minimum of rectified OLP inputs is less than 0.5V for 10ms; the IC shuts down to protect
the system in open lamp condition. The maximum of rectified OLP inputs is inputted to the
negative of the error amplifier for feedback control of lamp current.
4
OLP1
This pin is for open-lamp regulation. It has the same functions as other OLR pins and is
connected to the full-wave rectifier internally. When the maximum of rectified OLR inputs is
between 1.8V and 2V, the error amplifier output current is limited to 1µA; and when the
maximum of rectified OLR inputs reaches 2V, the error amplifier output current is 0A and its
output voltage maintains constant. The maximum of rectified OLR inputs is inputted to the
negative of another error amplifier for feedback control of lamp voltage. When the maximum
of rectified OLR inputs is more than 2.2V, another error amplifier for OLR is operating and
lamp voltage is regulated.
5
6
OLR1
OLP2
This pin is for open-lamp protection and feedback control of lamp currents. Its functions are
the same as the OLP1 pin.
7
OLR2
GND
This pin is for open-lamp regulation. Its functions are the same as the OLR1 pin.
This pin is the ground.
8
9
OUTB
OUTA
OUTC
OUTD
VIN
This pin is NMOS gate-drive output.
10
11
12
13
14
This pin is PMOS gate-drive output.
This pin is PMOS gate-drive output.
This pin is NMOS gate-drive output.
This pin is the supply voltage of the IC.
OLR3
This pin is for open-lamp regulation. Its functions are the same as the OLR1 pin.
This pin is for open-lamp protection and feedback control of lamp currents. Its functions are
the same as the OLP1 pin.
15
16
17
18
19
OLP3
OLR4
OLP4
ENA
This pin is for open-lamp regulation. Its functions are the same as the OLR1 pin.
This pin is for open-lamp protection and feedback control of lamp currents. Its functions are
the same as the OLP1 pin.
This pin is for turning on/off the IC.
Error amplifier output. Typically, a compensation capacitor is connected to this pin from the
ground.
CMP
This pin is for programming the switching frequency. Typically, a capacitor is connected to
this pin from ground and a resistor is connected to this pin from the REF pin.
20
CT
© 2007 Fairchild Semiconductor Corporation
FAN7317 • 1.0.2
www.fairchildsemi.com
4
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In
addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
VIN
Parameter
Min.
6
Max.
24
Unit
V
IC Supply Voltage
TA
Operating Temperature Range
Operating Junction Temperature
Storage Temperature Range
Thermal Resistance Junction-Air(1,2)
Power Dissipation
-25
+85
+150
+150
90
°C
TJ
°C
TSTG
θJA
-65
°C
°C/W
W
PD
1.4
Notes:
1. Thermal resistance test board. Size: 76.2mm x 114.3mm x 1.6mm (1S0P); JEDEC standard: JESD51-2, JESD51-3.
2. Assume no ambient airflow.
Pin Breakdown Voltage
Pin #
Name
REF
Value
7
Unit
Pin #
11
Name
OUTC
OUTD
VIN
Value
24
7
Unit
1
2
BDIM
BCT
7
12
3
7
13
24
±7
±7
±7
±7
7
4
OLP1
OLR1
OLP2
OLR2
GND
±7
±7
±7
±7
7
14
OLR3
OLP3
OLR4
OLP4
ENA
5
15
V
V
6
16
7
17
8
18
9
OUTB
OUTA
7
19
CMP
CT
7
10
24
20
7
© 2007 Fairchild Semiconductor Corporation
FAN7317 • 1.0.2
www.fairchildsemi.com
5
Electrical Characteristics
For typical values, TA = 25°C, VIN = 15V, and -25°C ≤ TA ≤ 85°C, unless otherwise specified. Specifications to -25°C ~
85°C are guaranteed by design based on final characterization results.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
Under-Voltage Lockout Section (UVLO)
Vth
Vthhys
Ist
Start Threshold Voltage
Start Threshold Voltage Hysteresis
Start-up Current
4.9
5.2
0.45
70
5.5
0.60
100
3.5
V
V
0.20
VIN = 4.5V
µA
mA
Iop
Operating Supply Current
VIN = 15V, Not switching
2.0
ON/OFF Section
Von
Voff
On State Input Voltage
2
5
V
V
Off Stage Input Voltage
Stand-by Current
0.7
170
270
Isb
VIN = 15V, ENA = Low
120
200
µA
kΩ
RENA
Pull-down Resistor
130
4.9
Reference Section (Recommend 1µF X7R Capacitor)
V5
5V Regulation Voltage
5V Line Regulation
5V Load Regulation
5.0
5.1
50
50
V
0 ≤ I5 ≤ 3mA
6 ≤ VIN ≤ 24V
I5 = 3mA
V5line
V5load
mV
mV
Oscillator Section (Main)
TA = 25°C, CT = 220pF,
RT = 100kΩ
93.9
93
97.0
97
100.5
101
fosc
Oscillation Frequency
kHz
kHz
CT = 220pF, RT =
100kΩ
TA = 25°C, CT = 220pF,
RT = 100kΩ
120
119
124
124
129
fstr
Oscillator Frequency in Striking Mode
CT Discharge Current
CT = 220pF, RT =
100kΩ
129
Ictdcs
Ictdc
Ictcs
Vcth
Vctl
Striking
Normal
Striking
0.99
740
-15
1.14
840
-12
2
1.29
940
-9
mA
μA
μA
V
CT Charge Current
CT High Voltage
CT Low Voltage
0.4
V
Oscillator Section (Burst)
TA = 25°C, BCT = 4.7nF,
BRT = 1.4MΩ
303
314
314
326
foscb
Burst Oscillation Frequency
Hz
BCT = 4.7nF, BRT =
1.4MΩ
302
14
326
38
Ibctdc
Vbcth
Vbctl
BCT Discharge Current
BCT High Voltage
BCT Low Voltage
26
2
μA
V
0.5
V
© 2007 Fairchild Semiconductor Corporation
FAN7317 • 1.0.2
www.fairchildsemi.com
6
Electrical Characteristics (Continued)
For typical values, TA = 25°C, VIN = 15V, and -25°C ≤ TA ≤ 85°C, unless otherwise specified. Specifications to -25°C ~
85°C are guaranteed by design based on final characterization results.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
Error Amplifier Section
AV
Gm
lsin
Open-loop Gain(3)
37
40
dB
µmho
µA
Error Amplifier Trans-conductance
Output Sink Current
20
-50
12
60
-20
32
OLP = 2.25V
-35
22
lsur
Output Source Current
OLP = 0.8V
µA
Ibsin
Burst CMP Sink Current
38
52
66
µA
TA = 25°C
1.275
1.255
-1
1.350
1.350
0
1.421
1.444
1
V135p
1.35V Regulation Voltage
V
Iolpi
Iolpo
Volpr
OLP Input Current
OLP = 2V
OLP = -2V
µA
µA
V
OLP Output Current
OLP Input Voltage Range(3)
-30
-4
-20
-10
4
Open-Lamp Regulation Section
Striking, OLR =
Iolr1
-2.0
-1.0
-0.1
µA
Error Amplifier Source Current for
Open-Lamp Regulation
Volr1+0.05
Iolr2
Volr1
Volr2
Volr3
OLR = 2.1V
Striking
0
µA
V
Open-Lamp Regulation Voltage 1
Open-Lamp Regulation Voltage 2
Open-Lamp Regulation Voltage 3
1.65
1.95
2.1
1.80
2.05
2.2
1.95
2.15
2.3
Striking
V
V
OLR Error Amplifier Trans-
conductance
GmOLR
200
350
500
µmho
Iolrsi
Iolri
OLR Error Amplifier Sink Current
OLR Input Current
Normal, OLR = 2.5V
OLR = 1.5V
50
10
-25
-4
70
17
90
24
-7
4
µA
µA
µA
V
Iolro
Volrr
OLR Output Current
OLR Input Voltage Range(3)
OLR = -1.5V
-15
Note:
3. These parameters, although guaranteed, are not 100% tested in production.
© 2007 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN7317 • 1.0.2
7
Electrical Characteristics (Continued)
For typical values, TA = 25°C, VIN = 15V, and -25°C ≤ TA ≤ 85°C, unless otherwise specified. Specifications to -25°C ~
85°C are guaranteed by design based on final characterization results.
Protection Section
Volp0
Volp1
Vcmpr
Varcp
Vhfbp
Vslp
Open-Lamp Protection Voltage 0(4)
Open-Lamp Protection Voltage 1
CMP-High Protection Voltage
Arc Protection Voltage
Open Lamp in Striking
Open Lamp
0.95
0.44
2.95
2.90
3.4
1.00
0.51
3.05
3.05
3.5
1.05
0.58
3.15
3.20
3.6
V
V
V
V
High-FB Protection Voltage(4)
V
Short Lamp Protection Voltage
0.24
0.32
1.6
0.40
V
Tolps
Tolpn
Tcmprs
Tcmprn
Tolr
Striking, foscb = 330Hz
Normal, fosc = 100kHz
Striking, foscb = 330Hz
Normal, fosc = 100kHz
Normal, fosc = 100kHz
Normal, fosc = 100kHz
s
Open-Lamp Protection Delay(4)
High-CMP Protection Delay(4)
10
ms
s
1.6
10
ms
µs
ms
°C
Open-Lamp Regulation Delay(4)
Short Lamp Protection Delay(4)
Thermal Shutdown(4)
320
1
Tslp
TSD
150
Output Section
Vpdhv
Vphlv
Vndhv
Vndlv
PMOS Gate High Voltage(4)
VIN = 15V
VIN = 15V
VIN = 15V
VIN = 15V
VIN
VIN-7
7.0
0
V
V
V
V
PMOS Gate Low Voltage
NMOS Gate High Voltage
NMOS Gate Low Voltage(4)
VIN-6.5
6.5
VIN-7.5
7.5
PMOS Gate Voltage with UVLO
Activated
NMOS Gate Voltage with UVLO
Activated
Vpuv
Vnuv
VIN = 4.5V
VIN = 4.5V
VIN-0.3
V
V
0.3
Ipdsur
Ipdsin
Indsur
Indsin
tr
PMOS Gate Drive Source Current(4)
PMOS Gate Drive Sink Current(4)
NMOS Gate Drive Source Current(4)
NMOS Gate Drive Sink Current(4)
Rising Time(4)
VIN = 15V
-200
300
200
-300
70
mA
mA
mA
mA
ns
VIN = 15V
VIN = 15V
VIN = 15V
VIN = 15V, Cload = 2nF
VIN = 15V, Cload = 2nF
tf
Falling Time(4)
70
ns
Maximum / Minimum Overlap
Minimum Overlap Between Diagonal
fosc = 100kHz
fosc = 100kHz
0
%
%
Switches(4)
Maximum Overlap Between Diagonal
86
90
Switches(4)
Dead Time
Note:
PDR_A/NDR_B(4)
PDR_C/NDR_D(4)
150
150
200
200
250
250
ns
ns
4. These Parameters, although guaranteed, are not 100% tested in production.
© 2007 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN7317 • 1.0.2
8
Typical Performance Characteristics
Figure 3. Start Threshold Voltage vs. Temp.
Figure 4. Start Threshold Voltage Hys. vs. Temp.
Figure 5. Start-up Current vs. Temp.
Figure 6. Operating Current vs. Temp.
Figure 7. Standby Current vs. Temp.
Figure 8. Pull-down Resistor vs. Temp.
© 2007 Fairchild Semiconductor Corporation
FAN7317 • 1.0.2
www.fairchildsemi.com
9
Typical Performance Characteristics (Continued)
Figure 9. 5V Regulation Voltage vs. Temp.
Figure 10. Oscillation Frequency vs. Temp.
Figure 11. Oscillation Frequency in Striking vs. Temp.
Figure 12. CT Discharge Current in Striking vs. Temp.
Figure 13. CT Discharge Current vs. Temp.
Figure 14. CT Charge Current vs. Temp.
© 2007 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN7317 • 1.0.2
10
Typical Performance Characteristics (Continued)
Figure 15. CT High Voltage vs. Temp.
Figure 16. CT Low Voltage vs. Temp.
Figure 17. Burst Dimming Frequency vs. Temp.
Figure 18. BCT Discharge Current vs. Temp.
Figure 19. BCT High Voltage vs. Temp.
Figure 20. BCT Low Voltage vs. Temp.
© 2007 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN7317 • 1.0.2
11
Typical Performance Characteristics (Continued)
Figure 21. Error Amp. GM vs. Temp.
Figure 22. Error Amp. Sink Current vs. Temp.
Figure 24. Burst CMP Sink Current vs. Temp.
Figure 26. OLP Input Current vs. Temp.
Figure 23. Error Amp. Source Current vs. Temp.
Figure 25. 1.35V Regulation Voltage vs. Temp.
© 2007 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN7317 • 1.0.2
12
Typical Performance Characteristics (Continued)
Figure 27. OLP Output Current vs. Temp.
Figure 28. Error Amp. Source Current 1 vs. Temp.
Figure 30. OLR Error Amp. GM vs. Temp.
Figure 32. OLR Input Current vs. Temp.
Figure 29. Error Amp. Source Current 2 vs. Temp.
Figure 31. OLR Error Amp. Sink Current vs. Temp.
© 2007 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN7317 • 1.0.2
13
Typical Performance Characteristics (Continued)
Figure 33. OLR Output Current vs. Temp.
Figure 34. Open-Lamp Protection Voltage1 vs. Temp.
Figure 35. High-CMP Protection Voltage vs. Temp.
Figure 36. Arc Protection Voltage vs. Temp.
Figure 37. Short Lamp Protection Voltage vs. Temp.
Figure 38. PMOS Gate Low Voltage vs. Temp.
© 2007 Fairchild Semiconductor Corporation
FAN7317 • 1.0.2
www.fairchildsemi.com
14
Functional Description
UVLO: The under-voltage lockout (UVLO) circuit
guarantees the stable operation of the IC’s control circuit
by stopping and starting it as a function of the VIN value.
The UVLO circuit turns on the control circuit when VIN
exceeds 5.2V. When VIN is lower than 4.75V, the IC
start-up current is less than 100µA.
Burst Dimming Oscillator: The burst dimming timing
capacitor (BCT) is charged by the current flowing from
the reference voltage source, which is formed by the
burst dimming timing resistor (BRT) and the burst
dimming timing capacitor (BCT). The sawtooth waveform
charges up to 2V. Once the BCT voltage reaches 2V, the
capacitor begins discharging down to 0.5V. Next, the
BCT starts charging again and a new burst dimming
cycle begins, as shown in Figure 40. The burst dimming
frequency is programmed by adjusting the BCT and BRT
values. The burst dimming frequency is calculated as:
ENA: Applying voltage higher than 2V to the ENA pin
enables the IC. Applying voltage lower than 0.7V to the
ENA pin disables the IC.
1
fOSCB
=
[Hz
]
(3)
0.039⋅ BRT − 4500
0.026⋅ BRT − 4500
⎛
⎜
⎞
⎟
Main Oscillator: In normal mode, the external timing
capacitor (CT) is charged by the current flowing from the
reference voltage source, which is formed by the timing
resistor (RT) and the timing capacitor (CT). The sawtooth
waveform charges up to 2V. Once CT voltage reaches
2V, the CT begins discharging down to 0.4V. Next, the
CT starts charging again and a new switching cycle
begins, as shown in Figure 39. The main frequency is
programmed by adjusting the RT and CT value. The
main frequency is calculated as:
BRT ⋅ BCT ⋅ln
⎝
⎠
To avoid visible flicker, the burst dimming frequency
should be greater than 120Hz.
1
fOSC
=
[Hz
]
(1)
3.864⋅RT −13800
2.52⋅RT −13800
⎛
⎜
⎞
⎟
RT ⋅CT ⋅ln
⎝
⎠
Figure 40. Burst Dimming Oscillator Circuit
Analog Dimming: For analog dimming, the lamp
intensity is controlled with the external dimming signal
(VADIM) and resistors. Figure 41 shows how to implement
an analog dimming circuit. The polarity of OLP1 should
be reversed with respect to OLP2.
Figure 39. Main Oscillator Circuit
In striking mode, the external timing capacitor (CT) is
charged by the current flowing from the reference
voltage source and 12μA current source, which
increases the frequency. If the product of RT and CT
value is constant, the striking frequency is depending on
CT and is calculated as:
1
fstr
=
[Hz
]
⎛
⎜
⎞
⎟
13.8+
(
3I1 − 4.6I2
)
RT
2
⎜
⎜
⎜
⎟
⎟
⎟
− I1 ⋅I2 ⋅RT
13.8+
RT⋅CT⋅ln
(2)
(4.6I1 −3I2 RT
)
2
⎜
⎟
⎠
− I1 ⋅I2 ⋅RT
QI1 =12×10-6 A, I2 =1.128×10-3 A
⎝
© 2007 Fairchild Semiconductor Corporation
FAN7317 • 1.0.2
www.fairchildsemi.com
15
Burst Dimming: Lamp intensity is controlled with the
BDIM signal over a wide range. When BDIM voltage is
lower than BCT voltage, the lamp current is turned on;
so, 0V on BDIM commands full brightness. The duty
cycle of the PWM pulse determines the lamp brightness.
The lamp intensity is inversely proportional to BDIM
voltage. As BDIM voltage increases, the lamp intensity
decreases. Figure 43 shows the lamp current waveform
vs. DIM in negative analog dimming mode.
T1
R1
R2
Full-
bridge
output
RS2
R2
R1
RS2
2V
T2
VBDIM
BCT
0.5V
0
RS1
CMP
0.5V
0
0
iLamp
RS1
Figure 41. Analog Implementation Circuit
VIN(V)
OUTA
In full brightness, the maximum rms value of the lamp
current is calculated as:
VIN-7(V)
7V
OUTB
π
0
max
rms
i
=1.35
[A
]
(4)
V
IN(V)
2 2RS1
OUTC
V
IN-7(V)
7V
The lamp intensity is inversely proportional to VADIM. As
VADIM increases, the lamp intensity decreases and the
rms value of the lamp current is calculated as:
OUTD
0
Figure 43. Burst Dimming Waveforms
R1
π
max
rms
irms = i
Q RS2
−
VADIM
[A]
Burst dimming can be implemented not only DC voltage,
but also using PWM pulse as the BDIM signal. Figure 44
shows how to implement burst dimming using PWM
pulse as BDIM signal.
RS2R2
2 2
(5)
R1 + R2
=
RS1
[ ]
Ω
R2
Figure 42 shows the lamp current waveform vs. VADIM in
an analog dimming mode.
tdch
tch
b
b
max
Lamp
i
min
Lamp
i
Figure 42. Analog Dimming Waveforms
Figure 44. Burst Dimming Using an External Pulse
During striking mode, burst dimming operation is
disabled to guarantee continuous striking time. Figure 45
shows burst dimming is disabled during striking mode.
© 2007 Fairchild Semiconductor Corporation
FAN7317 • 1.0.2
www.fairchildsemi.com
16
Open-Lamp Regulation: When the maximum of the
2V
max
rectified OLR input voltages ( V ) is more than 2V, the
OLR
VBDIM
BCT
IC enters regulation mode and controls CMP voltage.
0.5V
0
The IC limits the lamp voltage by decreasing CMP
max
OLR
source current. If V
is between 1.8V and 2V, CMP
CMP
source current decreases from 22µA to 1µA. Then, if
0.5V
0
max
V
reaches 2V, CMP source current decreases to
OLR
Striking
mode
0µA, so CMP voltage remains constant and the lamp
1V
0
voltage also remains constant, as shown in Figure 47.
OLP
max
OLR
Finally, if V
is more than 2.2V, the error amplifier for
-1V
OLR is operating and CMP sink current increases, so
CMP voltage decreases and the lamp voltage maintains
the determined value.
VIN(V)
OUTA
VIN-7(V)
7V
max
OLR
OUTB
At the same time, while V
is more than 2V, the
0
counter starts counting 32 rectified OLR pulses in normal
mode, then the IC enters shutdown, as shown in Figure
49. This counter is reset by detecting the positive edge
of BCT. This protection is disabled in striking mode to
ignite lamps reliably.
VIN(V)
OUTC
V
IN-7(V)
7V
OUTD
0
Figure 45. Burst Dimming During Striking Mode
Output Drives: FAN7317 uses the new phase-shift
method for full-bridge Cold Cathode Fluorescent Lighting
(CCFL) drive. As a result, the temperature difference
between the left and the right leg is almost zero,
because ZVS occurs in both of the legs by turns. The
detail timing is shown in Figure 46.
Figure 47. Open-Lamp Regulation in Striking Mode
CMP
OLR
2V OLR
2.2V OLR
0
2.2V
2V
0
-2V
-2.2V
0
iCMP
Figure 46. MOSFETs Gate Drive Signal
Figure 48. Open-Lamp Regulation in Normal Mode
Protections: The FAN7317 provides the following latch-
mode protections: Open-Lamp Regulation (OLR), Arc
Protection, Open-Lamp Protection (OLP), Short-Lamp
Protection (SLP), CMP-High Protection, and Thermal
Shutdown (TSD). The latch is reset when VIN falls to the
UVLO voltage or ENA is pulled down to GND.
© 2007 Fairchild Semiconductor Corporation
FAN7317 • 1.0.2
www.fairchildsemi.com
17
5V
0
CMP
CMP
1.6s
Shut down
0
1V
0
2V
0
OLP
-1V
OLR
BCT
VIN(V)
OUTA
-2V
VIN-7(V)
7V
32 pulses counting
Shut down
OUTB
0
V
IN(V)
Counter reset
0
0
0
OUTC
VIN-7(V)
OUTA
OUTB
7V
OUTD
0
OUTC
OUTD
Figure 51. Open-Lamp Protection in Striking Mode
5V
Figure 49. Over-Voltage Protection in Normal Mode
CMP
0
10ms
Shut down
Arc Protection: If the maximum of the rectified OLR
max
input voltages ( V ) is higher than 3V, the IC enters
0.5V
0
-0.5V
OLR
OLP
shutdown mode without delay, as shown in Figure 50.
VIN(V)
CMP
OUTA
VIN-7(V)
0
7V
OUTB
3V
0
VIN(V)
OLR
OUTC
0
VIN-7(V)
7V
OUTD
Shut down
0
OUTA
Figure 52. Open-Lamp Protection in Normal Mode
OUTB
0
Short-Lamp Protection: If the minimum of the rectified
OUTC
min
OLR voltages ( V ) is less than 0.3V in normal mode,
OLR
OUTD
0
the IC is shut down after a delay of 1ms, as shown in
Figure 53. This protection is disabled in striking mode to
ignite lamps reliably.
Figure 50. Arc Protection
Open-Lamp Protection: If the minimum of the rectified
min
OLP
OLP voltages ( V
) is less than 1V during initial
operation, the IC operates in striking mode only for 1.6s,
min
OLP
as shown in Figure 51. After ignition, if V
is less than
0.5V in normal mode, the IC is shut down after a delay of
10ms, as shown in Figure 52.
Figure 53. Short-Lamp Protection
© 2007 Fairchild Semiconductor Corporation
FAN7317 • 1.0.2
www.fairchildsemi.com
18
CMP-High Protection: If CMP is more than 3V in
normal mode, the IC is shut down after a delay of 10ms,
as shown in Figure 54. This protection is disabled in
striking mode to ignite lamps reliably.
Figure 54. CMP-High Protection
High-FB Protection: If the minimum of the rectified OLP
max
OLP
voltages( V
) is more than 3.5V, the counter starts
counting eight rectified OLP pulses in normal mode, then
the IC enters shutdown, as shown in Figure 55. This
counter is reset by detecting the positive edge of BCT.
This protection is disabled in striking mode to ignite
lamps reliably.
CMP
0
3.5V
0
OLP
-3.5V
8 pulses counting
Shut down
BCT
Counter reset
0
0
0
OUTA
OUTB
OUTC
OUTD
Figure 55. High-FB Protection
Thermal Shutdown: The IC provides the function to
detect the abnormal over-temperature. If the IC
temperature exceeds approximately 150°C, the thermal
shutdown triggers.
© 2007 Fairchild Semiconductor Corporation
FAN7317 • 1.0.2
www.fairchildsemi.com
19
Typical Application Circuit (LCD Backlight Inverter)
Application
Device
Input Voltage Range
Number of lamps
22-Inch LCD Monitor
FAN7317
13±10%
4
1. Features
High-Efficiency Single-Stage Power Conversion
P-N Full-Bridge Topology
Reduces Required External Components
Enhanced System Reliability through Protection Functions
Figure 56. Typical Application Circuit
2. Transformer Schematic Diagram
Figure 57. Transformer Schematic Diagram
3. Core & Bobbin
Core: EFD2126
Material: PL7
Bobbin: EFD2126
© 2007 Fairchild Semiconductor Corporation
FAN7317 • 1.0.2
www.fairchildsemi.com
20
4. Winding Specification
Pin No.
Wire
Turns
Inductance
250µH
Leakage Inductance
Remarks
16µH
5 Æ 2
17
1kHz, 1V
1 UEW 0.4φ
2256( =
0+0+376•6)
4.2H
290mH
7 Æ 9
1kHz, 1V
1 UEW 0.04φ
5. BOM of the Application Circuit
Part Ref.
Value
Fuse
Description
Part Ref.
Value
Description
C14
C15
C17
C18
C19
C21
3.3n
100n
1µ
50V 1608 K
50V 1608 K
50V 2012 K
50V 1608 K
50V 1608 K
50V 1608 K
F1
24V 3A
FUSE
Resistor (SMD)
R1
R2
10k
10k
1608 J
1608 J
1608 F
1608 F
1608 J
1608 F
1608 J
1608 J
1608 J
1608 J
1608 F
1608 F
1608 J
1608 F
4.7n
3.3n
3.3n
R3
200
R5
100k
10k
Capacitor (DIP)
R6
C4
3p
3KV
3KV
3KV
3KV
R7
200
C13
C16
C20
3p
R8
75k
3p
R9
10k
3p
R10
R12
R13
R14
R15
R16
8.2k
10k
Electrolytic capacitor
220µ
C1
C2
25V
25V
200
220µ
1.5M
10k
MOSFET (SMD)
M1
M2
FDD8424H
FDD8424H
Fairchild Semiconductor
Fairchild Semiconductor
200
Capacitor (SMD)
1µ
Wafer (SMD)
C3
C5
50V 2012 K
50V 2012 K
50V 1608 K
16V 3216
CN1
CN2
CN3
CN4
CN5
12505WR-10
35001WR-02A
35001WR-02A
35001WR-02A
35001WR-02A
1µ
C6
3.3n
10µ
C7
C8
10n
50V 1608 K
16V 3216
C9
10µ
Transformer (DIP)
C10
C11
C12
220p
10n
50V 1608 K
50V 1608 K
50V 2012 K
TX1
TX2
EFD2126
EFD2126
1µ
© 2007 Fairchild Semiconductor Corporation
FAN7317 • 1.0.2
www.fairchildsemi.com
21
Physical Dimensions
13.00
12.60
A
11.43
20
11
B
9.50
10.65 7.60
10.00 7.40
2.25
1
PIN ONE
INDICATOR
10
0.65
0.51
0.35
1.27
1.27
M
0.25
C B A
LAND PATTERN RECOMMENDATION
SEE DETAIL A
2.65 MAX
0.33
0.20
C
0.10
C
0.30
0.10
SEATING PLANE
0.75
0.25
X 45°
NOTES: UNLESS OTHERWISE SPECIFIED
(R0.10)
(R0.10)
A) THIS PACKAGE CONFORMS TO JEDEC
MS-013, VARIATION AC, ISSUE E
GAGE PLANE
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
0.25
8°
0°
D) CONFORMS TO ASME Y14.5M-1994
1.27
0.40
SEATING PLANE
E) LANDPATTERN STANDARD: SOIC127P1030X265-20L
F) DRAWING FILENAME: MKT-M20BREV3
(1.40)
DETAIL A
SCALE: 2:1
Figure 58. 20-SOIC Package
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
© 2007 Fairchild Semiconductor Corporation
FAN7317 • 1.0.2
www.fairchildsemi.com
22
© 2007 Fairchild Semiconductor Corporation
FAN7317 • 1.0.2
www.fairchildsemi.com
23
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