FAN73711MX [FAIRCHILD]
High-Current, High-Side Gate Drive IC; 大电流，高边栅极驱动器IC
| 型号： | FAN73711MX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | High-Current, High-Side Gate Drive IC |
| 文件： | 总11页 (文件大小：1246K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 2009
FAN73711
High-Current, High-Side Gate Drive IC
Features
Description
Floating Channel for Bootstrap Operation to +600V
4A/4A Sourcing/Sinking Current Driving Capability
Common-Mode dv/dt Noise Canceling Circuit
3.3V and 5V Input Logic Compatible
Output In-phase with Input Signal
The FAN73711 is a monolithic high-side gate drive IC
that can drive high-speed MOSFETs and IGBTs operat-
ing up to +600V. It has a buffered output stage with all
NMOS transistors designed for high pulse current driving
capability and minimum cross-conduction.
Fairchild’s high-voltage process and common-mode
noise canceling techniques provide stable operation of
the high-side driver under high dv/dt noise circum-
stances. An advanced level-shift circuit offers high-side
gate driver operation up to VS=-9.8V (typical) for
Under-Voltage Lockout for VBS
Built-In Shunt Regulator on VDD and VBS
8-Lead Small Outline Package (SOP)
V
V
BS=15V. The UVLO circuit prevents malfunction when
BS is lower than the specified threshold voltage.
Applications
The high-current and low-output voltage drop feature
makes this device suitable for sustain and energy-
recovery circuit switches driver in the plasma display
panel application, motor drive inverter, switching power
supply, and high-power DC-DC converter applications.
High-Speed Gate Driver
Sustain Switch Driver in PDP Application
Energy Recovery Circuit Switch Driver in
PDP Application
High-Power Buck Converter
Motor Drive Inverter
8-SOP
Ordering Information
Operating
Part Number
Package
Eco Status
Packing Method
Temperature Range
FAN73711M
40°C ~ 125°C
FAN73711MX
Tube
8-SOP
RoHS
Tape and Reel
For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
© 2009 Fairchild Semiconductor Corporation
FAN73711 • Rev. 1.0.0
www.fairchildsemi.com
Typical Application Diagrams
15V
DBOOT3
RBOOT3
VS
15V
FAN73711
VDD
RBOOT1
DBOOT1
VB
1
2
3
4
8
7
6
5
Q3
R3
HO
VS
IN
IN3
D3
D4
FAN73711
CBOOT3
R4
NC
1
2
3
4
VDD
VB
HO
VS
8
7
6
5
L1
NC
GND
IN
IN1
CBOOT1
D1
D2
NC
R1
GND
NC
To Panel
DBOOT2
R2
Q1
FAN73711
FAN73711
VDD
1
2
3
4
VB
HO
VS
VB
1
2
3
4
VDD
IN
8
7
6
5
8
7
6
5
Q2
Q4
R5
CBOOT2
R7
R8
HO
VS
IN
IN2
IN4
NC
R6
NC
C1
C3
GND
NC
NC
GND
C2
Energy Recovery System
Sustain Drive Part
FAN73711 Rev.01
Figure 1. Floated Bi-Directional Switch and Half-Bridge Driver: PDP Application
15V
VIN
RBOOT
DBOOT
FAN73711
VB
VDD
1
2
3
4
8
R1
CBOOT
HO
IN
PWM
7
6
L1
R2
NC
VS
C1
GND
NC
C2
VOUT
5
D1
FAN73711 Rev.01
Figure 2. Step-Down (Buck) DC-DC Converter Application
© 2009 Fairchild Semiconductor Corporation
FAN73711 • Rev. 1.0.0
www.fairchildsemi.com
2
Internal Block Diagram
VDD
VDD
1
4
8
7
6
VB
HO
VS
UVLO
R
GND
R
NOISE
CANCELLER
IN
2
S
Q
110K
Pin 3 and 5 are no connection.
FAN73711 Rev.01
Figure 3. Functional Block Diagram
Pin Configuration
VDD
IN
1
2
3
4
8
7
6
5
VB
HO
VS
FAN73711
NC
GND
NC
FAN73711 Rev.01
Figure 4. Pin Configuration (Top View)
Pin Definitions
Pin #
Name
Description
1
2
3
4
5
6
7
8
VDD
IN
Supply Voltage
Logic Input for High-Side Gate Driver Output
No Connection
NC
GND
NC
VS
Ground
No Connection
High-Voltage Floating Supply Return
High-Side Driver Output
High-Side Floating Supply
HO
VB
© 2009 Fairchild Semiconductor Corporation
FAN73711 • Rev. 1.0.0
www.fairchildsemi.com
3
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be opera-
ble above the recommended operating conditions and stressing the parts to these levels is not recommended. In addi-
tion, extended exposure to stresses above the recommended operating conditions may affect device reliability. The
absolute maximum ratings are stress ratings only. TA=25°C unless otherwise specified.
Symbol
VS
Characteristics
High-Side Floating Offset Voltage(1)
High-Side Floating Supply Voltage
High-Side Floating Output Voltage
Low-Side and Logic Supply Voltage(1)
Logic Input Voltage
Min.
VB-VSHUNT
-0.3
Max.
VB+0.3
625.0
VB+0.3
VSHUNT
VDD+0.3
± 50
Unit
V
VB
V
VHO
VDD
VIN
VS-0.3
-0.3
V
V
-0.3
V
dVS/dt
PD
Allowable Offset Voltage Slew Rate
Power Dissipation(2, 3, 4)
V/ns
W
0.625
200
θJA
Thermal Resistance
°C/W
°C
°C
TJ
Junction Temperature
-55
-55
+150
TSTG
Storage Temperature
+150
Notes:
1.
This IC contains a shunt regulator on VDD and VBS . This supply pin should not be driven by a low-impedance
voltage source greater than the VSHUNT specified in the electrical characteristics section.
2.
3.
Mounted on 76.2 x 114.3 x 1.6mm PCB (FR-4 glass epoxy material).
Refer to the following standards:
JESD51-2: Integral circuits thermal test method environmental conditions, natural convection, and
JESD51-3: Low effective thermal conductivity test board for leaded surface-mount packages.
4.
Do not exceed power dissipation (PD) under any circumstances.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
VB
Parameter
High-Side Floating Supply Voltage
High-Side Floating Supply Offset Voltage
High-Side Output Voltage
Min.
VS+10
6-VDD
VS
Max.
VS+20
600
Unit
V
VS
V
VHO
VIN
VB
V
Logic Input Voltage
GND
10
VDD
20
V
VDD
TA
Supply Voltage
V
Operating Ambient Temperature
-40
+125
°C
© 2009 Fairchild Semiconductor Corporation
FAN73711 • Rev. 1.0.0
www.fairchildsemi.com
4
Electrical Characteristics
VBIAS(VDD, VBS)=15.0V, TA = 25°C, unless otherwise specified. The VIN and IIN parameters are referenced to GND.
The VO and IO parameters are relative to VS and are applicable to the respective output HO.
Symbol
Power Supply Section
Quiescent VDD Supply Current
Operating VDD Supply Current
Bootstrapped Supply Section
Characteristics
Test Condition
Min. Typ. Max. Unit
VIN=0V or 5V
fIN=20KHz, No Load
IQDD
IPDD
25
35
70
μA
μA
100
VBS Supply Under-Voltage Positive-Going
Threshold Voltage
V
BS=Sweep
VBSUV+
VBSUV-
VBSHYS
8.0
7.3
9.0 10.0
V
V
V
VBS Supply Under-Voltage Negative-Going
Threshold Voltage
VBS=Sweep
VBS=Sweep
8.3
0.7
9.3
VBS Supply Under-Voltage Lockout
Hysteresis Voltage
VB=VS=625V
VIN=0V or 5V
ILK
Offset Supply Leakage Current
Quiescent VBS Supply Current
10
μA
μA
μA
IQBS
60
120
C
LOAD=1000pF, fIN=20KHz, rms
Operating VBS Supply Current
IPBS
470 800
Value
Shung Regulator Section
VDD and VBS Shunt Regulator Clamping
V
DD=Sweep or VBS=Sweep
VSHUNT
21
23
25
V
Voltage
ISHUNT=5mA
Input Logic Section
VIH
VIL
IIN+
Logic “1” Input Voltage
2.5
V
V
Logic “0” Input Voltage
0.8
65
2
VIN=5V
VIN=0V
Logic Input High Bias Current
Logic Input Low Bias Current
Input Pull-Down Resistance
40
μA
IIN-
μA
RIN
90
110
KΩ
Gate Driver Output Section
High Level Output Voltage (VBIAS - VO)
VOH
VOL
IO+
No Load
No Load
1.2
30
V
mV
A
Low Level Output Voltage
Output High, Short-Circuit Pulsed Current(5)
Output Low, Short-Circuit Pulsed Current(5)
VHO=0V, VIN=5V, PW ≤10µs
3
3
4
4
VHO=15V,VIN=0V, PW ≤10µs
IO-
VS
A
V
Allowable Negative VS Pin Voltage for IN
Signal Propagation to HO
-9.8 -7.0
Note:
5.
These parameters guaranteed by design.
Dynamic Electrical Characteristics
VDD=VBS=15V, GND=0V, CLOAD=1000pF, TA=25°C, unless otherwise specified.
Symbol
Parameter
Turn-On Propagation Delay Time
Turn-Off Propagation Delay Time
Turn-On Rise Time
Conditions
Min. Typ. Max. Unit
ton
toff
tr
VS=0V
VS=0V
150
150
25
210
210
50
ns
ns
ns
ns
tf
Turn-Off Fall Time
15
40
© 2009 Fairchild Semiconductor Corporation
FAN73711 • Rev. 1.0.0
www.fairchildsemi.com
5
Typical Characteristics
200
180
160
140
120
100
200
180
160
140
120
100
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 5. Turn-On Propagation Delay
vs. Temperature
Figure 6. Turn-Off Propagation Delay
vs. Temperature
50
40
30
20
10
0
50
40
30
20
10
0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 7. Turn-On Rise Time
vs. Temperature
Figure 8. Turn-Off Fall Time
vs. Temperature
100
75
50
25
0
100
75
50
25
0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 9. Quiescent VDD Supply Current
vs. Temperature
Figure 10. Quiescent VBS Supply Current
vs. Temperature
© 2009 Fairchild Semiconductor Corporation
FAN73711 • Rev. 1.0.0
www.fairchildsemi.com
6
Typical Characteristics (Continued)
100
80
60
40
20
0
800
600
400
200
0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 11. Operating VDD Supply Current
vs. Temperature
Figure 12. Operating VBS Supply Current
vs. Temperature
10.0
9.5
9.0
8.5
8.0
9.5
9.0
8.5
8.0
7.5
7.0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 13. VBS UVLO+ vs. Temperature
Figure 14. VBS UVLO- vs. Temperature
1.2
0.9
0.6
0.3
0.0
30
25
20
15
10
5
0
-40
-40
-20
0
20
40
60
80
100
120
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 15. High-Level Output Voltage
vs. Temperature
Figure 16. Low-Level Output Voltage
vs. Temperature
© 2009 Fairchild Semiconductor Corporation
FAN73711 • Rev. 1.0.0
www.fairchildsemi.com
7
Typical Characteristics (Continued)
2.5
2.0
1.5
1.0
0.5
2.5
2.0
1.5
1.0
0.5
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 17. Logic High Input Voltage
vs. Temperature
Figure 18. Logic Low Input Voltage
vs. Temperature
-7
-8
60
50
40
30
20
10
0
-9
-10
-11
-12
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 19. Logic Input High Bias Current
vs. Temperature
Figure 20. Allowable Negative VS Voltage
vs. Temperature
25
24
23
22
21
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Figure 21. Shunt Regulator Clamping Voltage
vs. Temperature
© 2009 Fairchild Semiconductor Corporation
FAN73711 • Rev. 1.0.0
www.fairchildsemi.com
8
Switching Time Definitions
Timing Diagram
15V
50%
50%
VDD
VB
IN
15V
10nF
10µF
10µF
0.1µF
VS
ton
tr
toff
tf
GND
IN
FAN73711
1000pF
90%
90%
HO
OUT
10%
10%
FAN73711 Rev.01
Figure 22. Switching Time Test Circuit and Waveform Definitions
© 2009 Fairchild Semiconductor Corporation
FAN73711 • Rev. 1.0.0
www.fairchildsemi.com
9
Package Dimensions
5.00
4.80
A
0.65
3.81
8
5
B
1.75
6.20
5.80
4.00
3.80
5.60
1
4
PIN ONE
INDICATOR
1.27
1.27
(0.33)
M
0.25
C B A
LAND PATTERN RECOMMENDATION
SEE DETAIL A
0.25
0.10
0.25
0.19
C
1.75 MAX
0.10
C
0.51
0.33
OPTION A - BEVEL EDGE
0.50
x 45°
GAGE PLANE
0.25
R0.10
R0.10
OPTION B - NO BEVEL EDGE
0.36
NOTES: UNLESS OTHERWISE SPECIFIED
8°
0°
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AA, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) LANDPATTERN STANDARD: SOIC127P600X175-8M.
E) DRAWING FILENAME: M08AREV13
SEATING PLANE
0.90
(1.04)
0.406
DETAIL A
SCALE: 2:1
Figure 23. 8-Lead Small Outline Package (SOP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2009 Fairchild Semiconductor Corporation
FAN73711 • Rev. 1.0.0
www.fairchildsemi.com
10
© 2009 Fairchild Semiconductor Corporation
FAN73711 • Rev. 1.0.0
www.fairchildsemi.com
11
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