FAN7387V [FAIRCHILD]

Ballast Control IC for Compact Fluorescent Lamp; 镇流器控制IC,适用于紧凑型荧光灯
FAN7387V
型号: FAN7387V
厂家: FAIRCHILD SEMICONDUCTOR    FAIRCHILD SEMICONDUCTOR
描述:

Ballast Control IC for Compact Fluorescent Lamp
镇流器控制IC,适用于紧凑型荧光灯

接口集成电路 光电二极管 驱动
文件: 总12页 (文件大小:2098K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
July 2009  
FAN7387V  
Ballast Control IC for Compact Fluorescent Lamp  
Features  
Description  
The FAN7387V, developed using Fairchild’s unique  
high-voltage process and system-in-package (SiP)  
concept, is a ballast-control integrated circuit (IC) for a  
compact fluorescent lamp (CFL). The FAN7387V has a  
simple oscillating circuit using an external resistor and  
capacitor so the frequency variation is stable across the  
temperature range. FAN7387V has a external pin for  
dead time control and shutdown. By using this resistor, a  
designer can choose the optimum dead time to reduce  
the power loss on internal switching devices (MOSFETs).  
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
Integrated Half-Bridge MOSFET  
Internal Clock Using RCT  
Enable External Sync Function Using RCT  
Dead-Time Control by using Resistor  
Shut Down (Disable Mode)  
Internal Shunt Regulator  
UVLO Function High and Low Side  
Applications  
ƒ
Compact Fluorescent Lamp Ballast  
8-DIP  
Ordering Information  
Part Number  
Operating Temperature  
Package  
Packing Method  
Eco Status  
8-Lead, Dual-In-line  
Package (DIP)  
FAN7387VN  
-40 to +125°C  
RoHS  
Tube  
For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.  
© 2008 Fairchild Semiconductor Corporation  
FAN7387V • 1.0.0  
www.fairchildsemi.com  
Typical Applications Diagrams  
Figure 1. Typical Application Circuit for Fluorescent Lamp (Rapid Starting Method without PTC)  
Figure 2. Typical Application Circuit for Fluorescent Lamp (Rapid Starting Method with PTC)  
© 2008 Fairchild Semiconductor Corporation  
FAN7387V • 1.0.0  
www.fairchildsemi.com  
2
Internal Block Diagram  
HIGH- SIDE DRIVER  
VB  
UVLO  
UVLO  
Q
Noise  
Canceller  
S
Q
R
S
R
Q
Internal CLK  
Frequency Divide)r  
SET  
D
Q
(
Q
RESET  
External  
Sync  
HIN  
IN  
VDD  
Logic Detection Level  
DT  
LIN  
DELAY  
SHUTDOWN  
LOW- SIDE GATE DRIVER  
Always LIN  
First  
HIN  
LIN  
Figure 3.  
Functional Block Diagram  
Pin Configuration  
OUT PGND GND  
DT/SD  
8
7
6
5
FAN7387V  
YWW  
( YWW: Work Week Code)  
1
2
3
4
VDC VB VDD RCT  
Figure 4.  
Pin Configurations (Top View)  
Pin Definitions  
Pin #  
Name  
VDC  
VB  
Description  
1
2
3
4
5
6
7
8
High-voltage Supply  
High-Side Floating Supply  
Supply Voltage  
VDD  
RCT  
Oscillator Frequency Set Resistor and Capacitor  
Dead Time Set Resistor  
DT/SD  
GND  
PGND  
OUT  
Signal Ground  
Power Ground  
High-Side Floating Supply Return  
© 2008 Fairchild Semiconductor Corporation  
FAN7387V • 1.0.0  
www.fairchildsemi.com  
3
Absolute Maximum Ratings  
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be  
operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In  
addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.  
The absolute maximum ratings are stress ratings only. TA=25°C unless otherwise specified.  
Symbol  
VB  
Parameter  
High-Side Floating Supply  
Min.  
-0.3  
-0.3  
Typ.  
Max.  
465.0  
440.0  
Unit  
V
VOUT  
VRCT  
ICL  
High-Side Floating Supply Return  
RCT Pins Input Voltage  
V
VDD  
50  
V
Clamping Current Level(1)  
25  
mA  
V/ns  
°C  
dVOUT/dt  
TA  
Allowable Offset Voltage Slew Rate  
Operating Temperature Range  
Storage Temperature Range  
Power Dissipation  
-40  
-65  
+125  
+150  
TSTG  
PD  
°C  
2.1  
70  
W
Thermal Resistance (Junction-to-Air)  
°C/W  
ΘJA  
Note:  
1. Do not supply a low-impedance voltage source to the internal clamping Zener diode between the GND and the  
VDD pin of this device.  
© 2008 Fairchild Semiconductor Corporation  
FAN7387V • 1.0.0  
www.fairchildsemi.com  
4
Electrical Characteristics  
VBIAS (VDD, VB -VOUT)=14.0V, TA=25°C, unless otherwise specified.  
Symbol  
Parameter  
Test Conditions  
Min.  
Typ.  
Max.  
Unit  
High Voltage Supply Section  
VDC  
High Voltage Supply Voltage  
440  
V
Low-Side Supply Characteristics (VDD  
)
VDDUV+ VDD UVLO Positive-Going Threshold  
VDDUV- VDD UVLO Negative-Going Threshold  
VDDUHY VDD-Side UVLO Hysteresis  
VDD Increasing  
VDD Decreasing  
9
11  
8.8  
2.2  
15.4  
60  
13  
7.8  
9.8  
V
VCL  
IST  
Supply Camping Voltage  
IDD=10mA  
14.4  
Startup Supply Current  
VDD=9V  
90  
µA  
IQDD  
IDD  
Low-Side Quiescent Supply Current  
Dynamic Operating Supply Current  
230  
0.6  
380  
RDT=100kΩ  
20kHz, CL=1nF  
mA  
High-Side Supply Characteristics (VB-VOUT  
)
VHSUV+ High-Side UVLO Positive-Going Threshold  
VHSUV- High-Side UVLO Negative-Going Threshold  
VHSUHY VBS Supply UVLO Hysteresis  
VB-VOUT Increasing  
VB-VOUT Decreasing  
8
9
10  
7.5  
8.5  
0.5  
50  
9.5  
V
IQHS  
IPBS  
High-Side Quiescent Supply Current  
90  
µA  
High-Side Dynamic Operating Supply Current  
20kHz, CL=1nF  
130  
180  
Oscillator Characteristics  
fosc  
D
Oscillation Frequency  
Duty Cycle  
18  
20  
49.0  
22  
kHz  
%
RT=50kΩ, CT=330pF  
Running Mode  
Running Mode  
Running Mode  
Running Mode  
Running Mode  
47.5  
VRCT+ Upper Threshold Voltage of RCT  
VDD  
VRCT-  
VIH  
Lower Threshold Voltage of RCT  
Logic “1” Input Voltage of RCT  
Logic “0” Input Voltage of RCT  
Dead Time  
VDD/4  
3/4 VDD  
V
VIL  
3/5 VDD  
640  
tD  
440  
280  
540  
400  
RDT=100kΩ  
ns  
tDMIN  
Minimum Dead Time  
VDT/SD=VDD  
520  
Protection Characteristics  
VSD+  
VSD-  
ISD  
Shutdown “1” Input Voltage  
2.5  
V
VSD/DT=0 After Run  
Mode  
Shutdown “0” Input Voltage  
Shutdown Current  
1
350  
µA  
Ns  
tSD  
Shutdown Propagation Delay  
180  
Internal MOSFET Section  
ILKMOS Internal MOSFET Leakage Current  
VDS=400V  
50  
µA  
RON  
Static Drain-Source On-Resistance  
VGS=10V, ID=190mA  
4.6  
6.0  
Maximum Continuous Drain-Source Diode  
Forward Current  
IS  
0.38  
A
Maximum Pulsed Continuous Drain-Source  
Diode Forward Current  
ISM  
3.04  
A
V
VSD  
Drain-Source Diode Forward Voltage  
VGS=0V, IS=0.38A  
1.2  
© 2008 Fairchild Semiconductor Corporation  
FAN7387V • 1.0.0  
www.fairchildsemi.com  
5
Typical Performance Characteristics  
200  
150  
100  
50  
12.5  
12.0  
11.5  
11.0  
10.5  
10.0  
9.5  
0
-40  
-40  
-20  
0
20  
40  
60  
80  
100  
120  
-20  
0
20  
40  
60  
80  
100  
120  
Temperature [°C]  
Temperature [°C]  
Figure 5. Startup Current vs. Temperature  
Figure 6. VDD UVLO+ vs. Temperature  
10.5  
10.0  
9.5  
10.0  
9.6  
9.2  
8.8  
8.4  
8.0  
7.6  
7.2  
9.0  
8.5  
8.0  
7.5  
-40  
-20  
0
20  
40  
60  
80  
100  
120  
-40  
-20  
0
20  
40  
60  
80  
100  
120  
Temperature [°C]  
Temperature [°C]  
Figure 7. VDD UVLO- vs. Temperature  
Figure 8. VB-VOUT UVLO+ vs. Temperature  
10.0  
16.0  
15.8  
15.6  
15.4  
15.2  
15.0  
14.8  
9.6  
9.2  
8.8  
8.4  
8.0  
7.6  
7.2  
-40  
-20  
0
20  
40  
60  
80  
100  
120  
-40  
-20  
0
20  
40  
60  
80  
100  
120  
Temperature [°C]  
Temperature [°C]  
Figure 9. VB-VOUT UVLO- vs. Temperature  
Figure 10. VCL vs. Temperature  
© 2008 Fairchild Semiconductor Corporation  
FAN7387V • 1.0.0  
www.fairchildsemi.com  
6
Typical Performance Characteristics (Continued)  
2.5  
2.0  
1.5  
1.0  
0.5  
0.0  
500  
400  
300  
200  
100  
0
-40  
-20  
0
20  
40  
60  
80  
100  
120  
-40  
-20  
0
20  
40  
60  
80  
100 120  
Temperature [°C]  
Temperature [°C]  
Figure 11. IPDD vs. Temperature  
Figure 12. IQDD vs. Temperature  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0.0  
500  
400  
300  
200  
100  
0
-40  
-20  
0
20  
40  
60  
80  
100  
120  
-40  
-20  
0
20  
40  
60  
80  
100  
120  
Temperature [°C]  
Temperature [°C]  
Figure 13. ISD vs. Temperature  
Figure 14. VSD+ vs. Temperature  
23  
3.0  
2.5  
2.0  
1.5  
1.0  
22  
21  
20  
19  
18  
17  
-40  
-20  
0
20  
40  
60  
80  
100  
120  
-40  
-20  
0
20  
40  
60  
80  
100  
120  
Temperature [°C]  
Temperature [°C]  
Figure 15. VSD- vs. Temperature  
Figure 16. Operating Frequency vs. Temperature  
© 2008 Fairchild Semiconductor Corporation  
FAN7387V • 1.0.0  
www.fairchildsemi.com  
7
Typical Performance Characteristics (Continued)  
50  
40  
30  
20  
10  
0
500  
475  
450  
425  
400  
375  
350  
325  
300  
-40  
-20  
0
20  
40  
60  
80  
100  
120  
-40  
-20  
0
20  
40  
60  
80  
100  
120  
Temperature [°C]  
Temperature [°C]  
Figure 17. tDMIN vs. Temperature  
Figure 18. Dead-Time Mismatch vs. Temperature  
52  
51  
50  
49  
48  
52  
51  
50  
49  
48  
-40  
-20  
0
20  
40  
60  
80  
100  
120  
-40  
-20  
0
20  
40  
60  
80  
100  
120  
Temperature [°C]  
Temperature [°C]  
Figure 19. High-Side Duty Ratio vs. Temperature  
Figure 20. Low-Side Duty Ratio vs. Temperature  
Figure 21. Frequency vs. RT  
Figure 22. On-Region Characteristics  
© 2008 Fairchild Semiconductor Corporation  
FAN7387V • 1.0.0  
www.fairchildsemi.com  
8
Typical Performance Characteristics (Continued)  
Figure 23. On-Resistance Variation vs.  
Drain Current and Gate Voltage  
Figure 24. Body Diode Forward Voltage Variation vs.  
Source Current and Temperature  
Figure 25. Breakdown Voltage Variation vs. Temperature Figure 26. On-Resistance Variation vs. Temperature  
Figure 27. Maximum Safe Operating Area  
Figure 28. Maximum Drain-Current  
vs. Case Temperature  
© 2008 Fairchild Semiconductor Corporation  
FAN7387V • 1.0.0  
www.fairchildsemi.com  
9
Application Information  
1. Under-Voltage Lockout (UVLO) Function  
RCT  
LO  
FAN7387V has a UVLO circuit for a low-side and high-  
side block. When VDD reaches to the VDDUV+, the UVLO  
circuit is released and the FAN7387V operates normally.  
At UVLO condition, the FAN7387V has a low supply  
current of less than 130µA. Once UVLO is released,  
FAN7387V operates normally until VDD goes below  
VDDUV-, the UVLO hysteresis. FAN7387V also has a  
high-side gate driver. The supply for the high-side driver  
is applied between VB and VOUT. To prevent malfunction  
at low supply voltage between VB and VOUT, FAN7387V  
provides an additional UVLO circuit. If VB-VOUT is under  
t
Tfix  
Tfix  
HO  
DT  
DT  
VHSUV+, the driver holds LOW state to turn off the high-  
side switch. Once the voltage of VB-VOUT is higher than  
VHSUV+, after VB-VOUT exceeds VHSUV-, the operation of  
driver resumes.  
T
Figure 30. Typical Waveforms of RCT and Internal  
Signal (LO, HO) of IC  
2. Oscillator  
The running frequency is determined by an external  
timing resistor (RT) and timing capacitor (CT). The charge  
time of capacitor CT from 1/4 VDD to VDD determines the  
running frequency of gate driver output (VOUT).  
t = 1.38 RT CT  
(2)  
The running frequency of IC is determined by 1/t and is  
approximately given as:  
1
t
1
frunning  
=
=
(3)  
2(  
t + tfix  
)
where t is the discharging time of the RCT voltage and tfix  
is constant value about 450ns of IC.  
3. Programming Dead Time Control /  
Shutdown  
A multi-function pin controls dead time using an external  
resistor (RDT) and protects abnormal condition using an  
external switch. This pin should be connected to an  
external capacitor to maintain stable operation.  
Figure 29. Typical Connection Method  
If the voltage of DT/SD is decreased to under 1V by an  
external switch, such as the TR or MOSFET, the  
FAN7387V enters shutdown mode. In this mode, the  
FAN7387V doesn’t have any output signal.  
Figure 30 shows the typical waveforms of RCT and  
internal signals (LO and HO) of IC. From the circuit  
analysis, the discharging time of RCT, t, is given by:  
t  
RT CT  
VRCT (t) = VDD ×In  
(1)  
From Equation 1, it is possible to calculate the  
discharging time, t, from VDD to one quarter (1/4) of VDD  
by substituting VRCT(t) with 1/4 VDD  
.
Figure 31. External Shutdown Circuit  
© 2008 Fairchild Semiconductor Corporation  
FAN7387V • 1.0.0  
www.fairchildsemi.com  
10  
Physical Dimensions  
.400 10.15  
.373 9.46  
A
[
]
.036 [0.9 TYP]  
(.092) [Ø2.337]  
PIN #1  
(.032) [R0.813]  
PIN #1  
.250±.005 [6.35±0.13]  
B
TOP VIEW  
OPTION 1  
TOP VIEW  
OPTION 2  
.070 1.78  
.310±.010 [7.87±0.25]  
.045  
[ ]  
1.14  
.130±.005 [3.3±0.13]  
.210 MAX  
[5.33]  
7° TYP  
7° TYP  
C
.015 MIN  
[0.38]  
.021 0.53  
.015 0.37  
.300  
[7.62]  
[
]
.140 3.55  
.125 3.17  
[
]
.001[.025]  
C
.100  
[2.54]  
.430 MAX  
[10.92]  
.060 MAX  
[1.52]  
NOTES:  
A. CONFORMS TO JEDEC REGISTRATION MS-001,  
VARIATIONS BA  
B. CONTROLING DIMENSIONS ARE IN INCHES  
+.005  
-.000  
+0.127  
-0.000  
.010  
0.254  
[
]
REFERENCE DIMENSIONS ARE IN MILLIMETERS  
C. DOES NOT INCLUDE MOLD FLASH OR PROTRUSIONS.  
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED  
.010 INCHES OR 0.25MM.  
D. DOES NOT INCLUDE DAMBAR PROTRUSIONS.  
DAMBAR PROTRUSIONS SHALL NOT EXCEED  
.010 INCHES OR 0.25MM.  
E. DIMENSIONING AND TOLERANCING  
PER ASME Y14.5M-1994.  
N08EREVG  
Figure 32. 8-Lead Dual Inline Package (DIP)  
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner  
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or  
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,  
specifically the warranty therein, which covers Fairchild products.  
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:  
http://www.fairchildsemi.com/packaging/.  
© 2008 Fairchild Semiconductor Corporation  
FAN7387V • 1.0.0  
www.fairchildsemi.com  
11  
© 2008 Fairchild Semiconductor Corporation  
FAN7387V • 1.0.0  
www.fairchildsemi.com  
12  

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