FDC6306PL99Z [FAIRCHILD]

Small Signal Field-Effect Transistor, 1.9A I(D), 20V, 2-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, SUPERSOT-6;
FDC6306PL99Z
型号: FDC6306PL99Z
厂家: FAIRCHILD SEMICONDUCTOR    FAIRCHILD SEMICONDUCTOR
描述:

Small Signal Field-Effect Transistor, 1.9A I(D), 20V, 2-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, SUPERSOT-6

文件: 总5页 (文件大小:61K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
February 1999  
FDC6306P  
Dual P-Channel 2.5V Specified PowerTrench MOSFET  
Features  
General Description  
These P-Channel 2.5V specified MOSFETs are produced  
using Fairchild Semiconductor's advanced PowerTrench  
process that has been especially tailored to minimize  
on-state resistance and yet maintain low gate charge for  
superior switching performance.  
-1.9 A, -20 V. RDS(on) = 0.170 @ VGS = -4.5 V  
RDS(on) = 0.250@ VGS = -2.5 V  
Low gate charge (3 nC typical).  
Fast switching speed.  
These devices have been designed to offer exceptional  
power dissipation in a very small footprint for applications  
where the bigger more expensive SO-8 and TSSOP-8  
packages are impractical.  
High performance trench technology for extremely  
low RDS(ON)  
.
TM  
SuperSOT -6 package: small footprint (72% smaller  
than standard SO-8); low profile (1mm thick).  
Applications  
Load switch  
Battery protection  
Power management  
D2  
S1  
3
2
1
4
5
6
D1  
G2  
S2  
SuperSOTTM-6  
G1  
TA = 25°C unless otherwise noted  
Absolute Maximum Ratings  
Symbol  
Parameter  
Ratings  
Units  
VDSS  
VGSS  
ID  
Drain-Source Voltage  
Gate-Source Voltage  
-20  
V
V
A
8
±
(Note 1a)  
Drain Current - Continuous  
- Pulsed  
-1.9  
-5  
(Note 1a)  
(Note 1b)  
PD  
Power Dissipation for Single Operation  
0.96  
0.9  
W
(Note 1c)  
0.7  
TJ, Tstg  
Operating and Storage Junction Temperature Range  
-55 to +150  
C
°
Thermal Characteristics  
θ
(Note 1a)  
(Note 1)  
R
R
Thermal Resistance, Junction-to-Ambient  
Thermal Resistance, Junction-to-Case  
130  
60  
C/W  
C/W  
JA  
°
°
JC  
θ
Package Outlines and Ordering Information  
Device Marking  
306  
Device  
Reel Size  
Tape Width  
Quantity  
3000 units  
FDC6306P  
7’’  
8mm  
.
1999 Fairchild Semiconductor Corporation  
FDC6306P Rev. C  
TA = 25°C unless otherwise noted  
Electrical Characteristics  
Symbol  
Parameter  
Test Conditions  
Min Typ Max Units  
Off Characteristics  
BVDSS  
Drain-Source Breakdown Voltage  
VGS = 0 V, ID = -250  
A
-20  
V
µ
DSS  
Breakdown Voltage Temperature  
Coefficient  
ID = -250 A, Referenced to 25 C  
-18  
mV/ C  
BV  
µ
°
°
TJ  
IDSS  
Zero Gate Voltage Drain Current  
VDS = -16 V, VGS = 0 V  
-1  
A
µ
IGSSF  
IGSSR  
Gate-Body Leakage Current, Forward VGS = 8 V, VDS = 0 V  
Gate-Body Leakage Current, Reverse VGS = -8 V, VDS = 0 V  
100  
-100  
nA  
nA  
(Note 2)  
On Characteristics  
VGS(th)  
Gate Threshold Voltage  
VDS = VGS, ID = -250  
A
-0.4  
-0.9  
3
-1.5  
V
µ
GS(th)  
Gate Threshold Voltage  
Temperature Coefficient  
ID = -250 A, Referenced to 25 C  
mV/ C  
V
µ
°
°
TJ  
RDS(on)  
Static Drain-Source  
On-Resistance  
VGS = -4.5 V, ID = -1.9 A  
0.127 0.170  
0.182 0.270  
0.194 0.250  
V
V
GS = -4.5 V, ID = -1.9 A @125 C  
GS = -2.5 V, ID = -1.7 A  
°
ID(on)  
gFS  
On-State Drain Current  
VGS = -4.5 V, VDS =- 5 V  
-5  
A
S
Forward Transconductance  
VDS = -5 V, ID = -1.9 A  
4
Dynamic Characteristics  
Ciss  
Coss  
Crss  
Input Capacitance  
V
DS = -10 V, VGS = 0 V,  
441  
127  
67  
pF  
pF  
pF  
f = 1.0 MHz  
Output Capacitance  
Reverse Transfer Capacitance  
(Note 2)  
Switching Characteristics  
td(on)  
tr  
td(off)  
tf  
Turn-On Delay Time  
Turn-On Rise Time  
Turn-Off Delay Time  
Turn-Off Fall Time  
Total Gate Charge  
Gate-Source Charge  
Gate-Drain Charge  
V
V
DD = -10 V, ID = -1 A,  
GS = -4.5 V, RGEN = 6  
6
9
12  
18  
25  
9
ns  
ns  
14  
3
ns  
ns  
Qg  
Qgs  
Qgd  
V
V
DS = -10 V, ID = -1.9 A,  
GS = -4.5 V  
3
4.2  
nC  
nC  
nC  
0.7  
0.8  
Drain-Source Diode Characteristics and Maximum Ratings  
IS  
Maximum Continuous Drain-Source Diode Forward Current  
-0.8  
-1.2  
A
V
(Note 2)  
VSD  
Drain-Source Diode Forward Voltage VGS = 0 V, IS = -0.8 A  
-0.8  
Notes:  
1.  
RθJA is the sum of the junction-to-case and case-to-ambient resistance where the case thermal reference is defined as the solder mounting surface  
of the drain pins. RθJC is guaranteed by design while RθJA is determined by the user's board design.Both devices are assumed to be operating and  
sharing the dissipated heat energy equally.  
a) 130 °C/W when  
b) 140 °C/W when  
c) 180 °C/W when  
mounted on a 0.125 in2  
pad of 2 oz. copper.  
mounted on a 0.005 in2  
pad of 2 oz. copper.  
mounted on a 0.0015 in2  
pad of 2 oz. copper.  
Scale  
1 : 1 on letter size paper  
2. Pulse Test: Pulse Width 300 µs, Duty Cycle 2.0%  
FDC6306P Rev. C  
Typical Characteristics  
2
1.8  
1.6  
1.4  
1.2  
1
12  
V GS= -4 .5 V  
-4.0V  
10  
-3 .5 V  
VGS = -2.5 V  
8
6
4
2
0
-3 .0 V  
-3.0V  
-2 .5 V  
-3.5V  
-4.0V  
6
-4.5V  
-2 .0 V  
0.8  
0
2
4
8
10  
0
1
2
3
4
5
- I , DRAIN CURRENT (A)  
D
-V , DRAIN-SOURCE VOLTAGE (V)  
DS  
Figure 1. On-Region Characteristics.  
Figure 2. On-Resistance Variation  
with Drain Current and Gate Voltage.  
1.6  
1.4  
1.2  
1
0.5  
ID = -1 .9 A  
ID = -1A  
VGS= -4.5V  
0.4  
0.3  
0.2  
0.1  
0
T
= 125°C  
J
0.8  
0.6  
25°C  
1
2
3
4
5
-50  
-25  
0
25  
50  
75  
100  
125  
150  
-V  
, GATE TO SOURCE VOLT AG E (V)  
T , JUNCTION TEMPERATURE (°C)  
GS  
J
Figure 3. On-Resistance Variation  
with Temperature.  
Figure 4. On-Resistance Variation  
with Gate-to-Source Voltage.  
10  
10  
VDS = -5V  
VGS = 0V  
T = -55°C  
J
25°C  
125°C  
8
6
4
2
0
1
T = 125°C  
J
25 °C  
0.1  
-55°C  
0.01  
0.001  
0.0001  
0
1
2
3
4
5
0
0.2  
0.4  
0.6  
0.8  
1
1.2  
1.4  
-V , GATE TOSOURCE VOLTAGE (V)  
GS  
-V , BODY DI ODE FORWARD VOLT AGE (V )  
SD  
Figure 5. Transfer Characteristics.  
Figure 6. Body Diode Forward Voltage  
Variation with Source Current  
and Temperature.  
FDC6306P Rev. C  
Typical Characteristics (continued)  
1000  
5
I D = -1.9A  
VDS = -5V  
4
-10V  
C
iss  
300  
100  
-15V  
3
2
1
0
C
oss  
C
rss  
f = 1 MHz  
VGS = 0 V  
30  
0.1  
0
1
2
3
4
0.2  
0.5  
1
2
5
10  
20  
Q
, GAT E CHARGE (nC)  
g
-V , DRAIN TOSOURCE VOLTAGE (V)  
DS  
Figure 7. Gate-Charge Characteristics.  
Figure 8. Capacitance Characteristics.  
5
4
3
2
1
30  
10  
SINGLE PULSE  
RθJA=180°C/W  
TA= 25°C  
3
1
0.3  
0.1  
VGS = -4.5V  
SINGLE PULSE  
Rθ  
= 180°C/W  
JA  
0.03  
0.01  
TA = 25°C  
0
0.01  
0.1  
1
10  
100  
300  
0.1  
0.2  
0.5  
1
2
5
10  
20  
50  
SINGLE PULSE TIME (SEC)  
-V , DRAIN-SOURCE VOLTAGE (V)  
DS  
Figure 9. Maximum Safe Operating Area.  
Figure 10. Single Pulse Maximum  
Power Dissipation.  
1
D = 0.5  
0.5  
R
(t) = r(t) * R  
JA  
θ
JA  
θ
R
=180°C/W  
JA  
θ
0.2  
0.2  
0.1  
P(pk)  
0.1  
0.05  
t
1
0.05  
t
2
0.02  
0.01  
T
- T = P * R  
(t)  
JA  
J
A
θ
Single Pulse  
0.02  
Duty Cycle, D = t / t  
2
1
0.01  
0.0001  
0.001  
0.01  
0.1  
, TIME (sec)  
1
10  
100  
300  
t
1
Figure 11. Transient Thermal Response Curve.  
Thermal characterization performed using the conditions described in Note 1c.  
Transient themal response will change depending on the circuit board design.  
FDC6306P Rev. C  
TRADEMARKS  
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is  
not intended to be an exhaustive list of all such trademarks.  
ACEx™  
CoolFET™  
ISOPLANAR™  
MICROWIRE™  
POP™  
PowerTrench  
QFET™  
SyncFET™  
TinyLogic™  
UHC™  
CROSSVOLT™  
E2CMOSTM  
VCX™  
FACT™  
FACT Quiet Series™  
QS™  
FAST®  
Quiet Series™  
SuperSOT™-3  
SuperSOT™-6  
SuperSOT™-8  
FASTr™  
GTO™  
HiSeC™  
DISCLAIMER  
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER  
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD  
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT  
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT  
RIGHTS, NOR THE RIGHTS OF OTHERS.  
LIFE SUPPORT POLICY  
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT  
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.  
As used herein:  
1. Life support devices or systems are devices or  
systems which, (a) are intended for surgical implant into  
the body, or (b) support or sustain life, or (c) whose  
failure to perform when properly used in accordance  
with instructions for use provided in the labeling, can be  
reasonably expected to result in significant injury to the  
user.  
2. A critical component is any component of a life  
support device or system whose failure to perform can  
be reasonably expected to cause the failure of the life  
support device or system, or to affect its safety or  
effectiveness.  
PRODUCT STATUS DEFINITIONS  
Definition of Terms  
Datasheet Identification  
Product Status  
Definition  
Advance Information  
Formative or  
In Design  
This datasheet contains the design specifications for  
product development. Specifications may change in  
any manner without notice.  
Preliminary  
First Production  
This datasheet contains preliminary data, and  
supplementary data will be published at a later date.  
Fairchild Semiconductor reserves the right to make  
changes at any time without notice in order to improve  
design.  
No Identification Needed  
Obsolete  
Full Production  
This datasheet contains final specifications. Fairchild  
Semiconductor reserves the right to make changes at  
any time without notice in order to improve design.  
Not In Production  
This datasheet contains specifications on a product  
that has been discontinued by Fairchild semiconductor.  
The datasheet is printed for reference information only.  
Rev. D  

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