FDD13AN06A0_10 [FAIRCHILD]
N-Channel PowerTrench® MOSFET 60V, 50A, 13.5mΩ; N沟道MOSFET PowerTrench® 60V ， 50A ， 13.5mÎ ©
| 型号： | FDD13AN06A0_10 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | N-Channel PowerTrench® MOSFET 60V, 50A, 13.5mΩ |
| 文件： | 总11页 (文件大小：210K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 2010
FDD13AN06A0_F085
N-Channel PowerTrench® MOSFET
60V, 50A, 13.5mΩ
Features
Applications
•
•
•
•
•
rDS(ON) = 11.5mΩ(Typ.), VGS = 10V, ID = 50A
Qg(tot) = 22nC (Typ.), VGS = 10V
Low Miller Charge
•
•
•
•
•
•
•
Motor / Body Load Control
ABS Systems
Powertrain Management
Injection Systems
Low QRR Body Diode
UIS Capability (Single Pulse and Repetitive Pulse)
DC-DC converters and Off-line UPS
•
•
Qualified to AEC Q101
RoHS Compliant
Distributed Power Architectures and VRMs
Primary Switch for 12V and 24V systems
Formerly developmental type 82555
DRAIN
(FLANGE)
D
GATE
G
SOURCE
S
TO-252AA
FDD SERIES
MOSFET Maximum Ratings TC = 25°C unless otherwise noted
Symbol
VDSS
VGS
Parameter
Ratings
60
Units
V
V
Drain to Source Voltage
Gate to Source Voltage
Drain Current
20
Continuous (TC < 80oC, VGS = 10V)
Continuous (TA = 25oC, VGS = 10V, RθJA = 52oC/W)
Pulsed
Single Pulse Avalanche Energy ( Note 1)
Power dissipation
50
A
ID
9.9
Figure 4
56
115
0.77
A
A
mJ
W
EAS
PD
Derate above 25oC
W/o
C
TJ, TSTG
Operating and Storage Temperature
-55 to 175
oC
Thermal Characteristics
oC/W
oC/W
oC/W
RθJC
RθJA
RθJA
Thermal Resistance Junction to Case TO-252
1.3
100
52
Thermal Resistance Junction to Ambient TO-252
Thermal Resistance Junction to Ambient TO-252, 1in2 copper pad area
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a
copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/
Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.
All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems
certification.
©2010 Fairchild Semiconductor Corporation
FDD13AN06A0_F085 Rev. A
Package Marking and Ordering Information
Device Marking
Device
Package
Reel Size
Tape Width
Quantity
FDD13AN06A0
FDD13AN06A0_F085
TO-252AA
330mm
16mm
2500 units
Electrical Characteristics TC = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
ID = 250μA, VGS = 0V
60
-
-
-
-
-
-
-
1
250
100
V
V
DS = 50V
IDSS
μA
nA
VGS = 0V
TC = 150oC
IGSS
VGS = 20V
-
On Characteristics
VGS(TH)
Gate to Source Threshold Voltage
VGS = VDS, ID = 250μA
D = 50A, VGS = 10V
ID = 25A, VGS = 6V
2
-
-
-
4
V
I
0.0115 0.0135
0.022 0.034
rDS(ON)
Drain to Source On Resistance
Ω
I
D = 50A, VGS = 10V,
-
0.026 0.030
TJ = 175oC
Dynamic Characteristics
CISS
Input Capacitance
Output Capacitance
-
-
-
1350
260
90
-
-
-
pF
pF
pF
nC
nC
nC
nC
nC
VDS = 25V, VGS = 0V,
f = 1MHz
COSS
CRSS
Qg(TOT)
Qg(TH)
Qgs
Reverse Transfer Capacitance
Total Gate Charge at 10V
Threshold Gate Charge
Gate to Source Gate Charge
Gate Charge Threshold to Plateau
Gate to Drain “Miller” Charge
VGS = 0V to 10V
22
29
3.4
-
-
-
VGS = 0V to 2V
-
-
-
-
2.6
8.2
5.6
6.4
VDD = 30V
ID = 50A
Ig = 1.0mA
Qgs2
Qgd
Switching Characteristics (VGS = 10V)
tON
td(ON)
tr
td(OFF)
tf
Turn-On Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
-
-
-
-
-
-
-
9
77
26
25
-
130
-
-
-
-
ns
ns
ns
ns
ns
ns
VDD = 30V, ID = 50A
VGS = 10V, RGS = 12Ω
tOFF
Turn-Off Time
77
Drain-Source Diode Characteristics
I
I
SD = 50A
SD = 25A
-
-
-
-
-
-
-
-
1.25
1.0
24
V
V
ns
nC
VSD
Source to Drain Diode Voltage
trr
QRR
Reverse Recovery Time
Reverse Recovered Charge
ISD = 50A, dISD/dt = 100A/μs
ISD = 50A, dISD/dt = 100A/μs
15
Notes:
1: Starting T = 25°C, L = 45μH, I = 50A.
J
AS
©2010 Fairchild Semiconductor Corporation
FDD13AN06A0_F085 Rev. A
Typical Characteristics TC = 25°C unless otherwise noted
1.2
80
1.0
CURRENT LIMITED
BY PACKAGE
60
0.8
0.6
0.4
0.2
0
40
20
0
25
50
75
100
125
150
175
150
0
25
50
75
100
175
125
o
o
T
, CASE TEMPERATURE ( C)
C
T
, CASE TEMPERATURE ( C)
C
Figure 1. Normalized Power Dissipation vs
Ambient Temperature
Figure 2. Maximum Continuous Drain Current vs
Case Temperature
2
DUTY CYCLE - DESCENDING ORDER
0.5
1
0.2
0.1
0.05
0.02
0.01
P
DM
0.1
t
1
t
2
NOTES:
DUTY FACTOR: D = t /t
1
2
SINGLE PULSE
0.01
PEAK T = P x Z
x R
+ T
J
DM
θJC
θJC C
-5
-4
-3
-2
-1
0
1
10
10
10
10
t, RECTANGULAR PULSE DURATION (s)
10
10
10
Figure 3. Normalized Maximum Transient Thermal Impedance
800
o
T
= 25 C
C
FOR TEMPERATURES
o
ABOVE 25 C DERATE PEAK
CURRENT AS FOLLOWS:
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
175 - T
150
C
I = I
25
V
= 10V
GS
100
30
-5
-4
-3
-2
-1
0
1
10
10
10
10
t, PULSE WIDTH (s)
10
10
10
Figure 4. Peak Current Capability
©2010 Fairchild Semiconductor Corporation
FDD13AN06A0_F085 Rev. A
Typical Characteristics TC = 25°C unless otherwise noted
100
1000
If R = 0
= (L)(I )/(1.3*RATED BV
t
- V
)
AV
If R
AS
DSS
DD
10μs
≠
0
t
AV
= (L/R)ln[(I *R)/(1.3*RATED BV
AS
- V ) +1]
DD
DSS
100
o
100μs
STARTING T = 25 C
J
1ms
10
OPERATION IN THIS
AREA MAY BE
10
1
o
LIMITED BY r
DS(ON)
STARTING T = 150 C
J
10ms
SINGLE PULSE
DC
T
T
= MAX RATED
= 25 C
J
o
C
1
0.01
0.1
1
10
, DRAIN TO SOURCE VOLTAGE (V)
100
0.1
1
10
100
V
t
, TIME IN AVALANCHE (ms)
DS
AV
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 6. Unclamped Inductive Switching
Capability
Figure 5. Forward Bias Safe Operating Area
100
100
PULSE DURATION = 80μs
o
V
= 20V
= 10V
T
= 25 C
GS
C
DUTY CYCLE = 0.5% MAX
V
= 15V
DD
80
60
40
20
0
80
60
40
20
0
V
GS
V
= 6V
GS
o
T
= 175 C
J
o
o
T
= -55 C
T
J
= 25 C
J
PULSE DURATION = 80μs
DUTY CYCLE = 0.5% MAX
V
= 5V
GS
0
0.5
1.0
1.5
2.0
3
4
5
6
7
V
, GATE TO SOURCE VOLTAGE (V)
V
, DRAIN TO SOURCE VOLTAGE (V)
GS
DS
Figure 7. Transfer Characteristics
Figure 8. Saturation Characteristics
2.5
2.0
1.5
1.0
0.5
30
PULSE DURATION = 80μs
PULSE DURATION = 80μs
DUTY CYCLE = 0.5% MAX
DUTY CYCLE = 0.5% MAX
25
20
15
10
V
= 6V
GS
V
= 10V
GS
V
= 10V, I =50A
D
GS
0
10
20
30
40
50
-80
-40
0
40
80
120
160
200
o
T , JUNCTION TEMPERATURE ( C)
J
I , DRAIN CURRENT (A)
D
Figure 9. Drain to Source On Resistance vs Drain
Current
Figure 10. Normalized Drain to Source On
Resistance vs Junction Temperature
©2010 Fairchild Semiconductor Corporation
FDD13AN06A0_F085 Rev. A
Typical Characteristics TC = 25°C unless otherwise noted
1.4
1.2
1.0
0.8
0.6
0.4
1.2
V
= V , I = 250μA
I
= 250μA
GS
DS
D
D
1.1
1.0
0.9
-80
-40
0
40
80
120
160
200
-80
-40
0
40
80
120
160
200
o
o
T , JUNCTION TEMPERATURE ( C)
T , JUNCTION TEMPERATURE ( C)
J
J
Figure 11. Normalized Gate Threshold Voltage vs
Junction Temperature
Figure 12. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
3000
10
V
= 30V
DD
8
6
4
2
0
C
= C + C
GS GD
1000
ISS
C
≅ C + C
DS GD
OSS
C
= C
GD
RSS
WAVEFORMS IN
DESCENDING ORDER:
100
40
I
I
= 50A
= 25A
D
D
V
= 0V, f = 1MHz
1
GS
0.1
10
60
0
5
10
15
20
25
Q , GATE CHARGE (nC)
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
g
Figure 13. Capacitance vs Drain to Source
Voltage
Figure 14. Gate Charge Waveforms for Constant
Gate Current
©2010 Fairchild Semiconductor Corporation
FDD13AN06A0_F085 Rev. A
Test Circuits and Waveforms
V
DS
BV
DSS
t
P
L
V
DS
I
VARY t TO OBTAIN
P
AS
+
-
V
DD
R
REQUIRED PEAK I
G
AS
V
DD
V
GS
DUT
t
P
I
0V
AS
0
0.01Ω
t
AV
Figure 15. Unclamped Energy Test Circuit
Figure 16. Unclamped Energy Waveforms
V
DS
V
Q
DD
g(TOT)
V
L
DS
V
GS
V
= 10V
GS
V
GS
+
-
Q
gs2
V
DD
DUT
V
= 2V
GS
I
g(REF)
0
Q
g(TH)
Q
Q
gs
gd
I
g(REF)
0
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveforms
V
DS
t
t
ON
OFF
t
d(OFF)
t
d(ON)
R
t
t
f
L
r
V
DS
90%
90%
+
V
GS
V
DD
10%
10%
-
0
DUT
90%
50%
R
GS
V
GS
50%
PULSE WIDTH
V
10%
GS
0
Figure 19. Switching Time Test Circuit
Figure 20. Switching Time Waveforms
©2010 Fairchild Semiconductor Corporation
FDD13AN06A0_F085 Rev. A
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PDM, in an
125
R
= 33.32+ 23.84/(0.268+Area) EQ.2
JA = 33.32+ 154/(1.73+Area) EQ.3
θJA
R
θ
application.
Therefore the application’s ambient
100
75
temperature, TA (oC), and thermal resistance RθJA (oC/W)
must be reviewed to ensure that TJM is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
(T
– T )
JM
A
(EQ. 1)
P
= -----------------------------
50
DM
RθJA
In using surface mount devices such as the TO-252
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of PDM is
complex and influenced by many factors:
25
0.01
0.1
(0.645)
1
10
(64.5)
(0.0645)
(6.45)
2
2
AREA, TOP COPPER AREA in (cm )
Figure 21. Thermal Resistance vs Mounting
Pad Area
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
defines the RθJA for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2 or 3. Equation 2 is used for copper area defined
in inches square and equation 3 is for area in centimeters
square. The area, in square inches or square centimeters is
the top copper area including the gate and source pads.
23.84
R
= 33.32 + ------------------------------------
(EQ. 2)
θJA
θJA
(0.268 + Area)
Area in Inches Squared
154
= 33.32 + ---------------------------------
(1.73 + Area)
R
(EQ. 3)
Area in Centimeters Squared
©2010 Fairchild Semiconductor Corporation
FDD13AN06A0_F085 Rev. A
PSPICE Electrical Model
.SUBCKT FDD13AN06A0 2 1 3 ; rev August 2002
Ca 12 8 5.1e-10
Cb 15 14 5.8e-10
LDRAIN
DPLCAP
DRAIN
2
5
Cin 6 8 1.3e-9
10
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
RLDRAIN
RSLC1
51
DBREAK
11
+
RSLC2
5
ESLC
51
Ebreak 11 7 17 18 65.40
Eds 14 8 5 8 1
-
+
50
-
17
Egs 13 8 6 8 1
DBODY
RDRAIN
16
6
8
EBREAK 18
-
ESG
Esg 6 10 6 8 1
EVTHRES
+
Evthres 6 21 19 8 1
21
+
-
19
MWEAK
Evtemp 20 6 18 22 1
It 8 17 1
LGATE
EVTEMP
8
RGATE
GATE
1
6
+
-
18
22
MMED
9
20
MSTRO
8
RLGATE
Lgate 1 9 5.2e-9
Ldrain 2 5 1.0e-9
Lsource 3 7 2.14e-9
LSOURCE
CIN
SOURCE
3
7
RSOURCE
RLSOURCE
RLgate 1 9 52
RLdrain 2 5 10
RLsource 3 7 21.4
S1A
S2A
RBREAK
12
15
13
14
17
18
8
13
RVTEMP
19
S1B
S2B
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
13
CB
+
CA
IT
14
-
+
VBAT
6
8
5
8
EGS
EDS
+
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 3.1e-3
Rgate 9 20 3.71
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
-
-
8
22
RVTHRES
Rsource 8 7 RsourceMOD 5.5e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*160),6))}
.MODEL DbodyMOD D (IS=1.0E-11 N=1.08 RS=3.5e-3 TRS1=2.2e-3 TRS2=2.5e-9
+ CJO=.9e-9 M=5.1e-1 TT=1e-9 XTI=3.9)
.MODEL DbreakMOD D (RS=1.5e-1 TRS1=1e-3 TRS2=-8.9e-6)
.MODEL DplcapMOD D (CJO=4.1e-10 IS=1e-30 N=10 M=0.45)
.MODEL MmedMOD NMOS (VTO=3.5 KP=6 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=3.71)
.MODEL MstroMOD NMOS (VTO=4.3 KP=50 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MweakMOD NMOS (VTO=2.91 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=3.71e+1 RS=0.1)
.MODEL RbreakMOD RES (TC1=9e-4 TC2=-5e-7)
.MODEL RdrainMOD RES (TC1=1.3e-2 TC2=5.2e-5)
.MODEL RSLCMOD RES (TC1=1.8e-3 TC2=1.7e-5)
.MODEL RsourceMOD RES (TC1=1e-3 TC2=1e-6)
.MODEL RvthresMOD RES (TC1=-5.3e-3 TC2=-1.0e-5)
.MODEL RvtempMOD RES (TC1=-2.5e-3 TC2=1e-6)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-5 VOFF=-2)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2 VOFF=-5)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.5 VOFF=.5)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=.5 VOFF=-1.5)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
©2010 Fairchild Semiconductor Corporation
FDD13AN06A0_F085 Rev. A
SABER Electrical Model
rev August 2002
template FDD13AN06A0 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=1.0e-11,nl=1.08,rs=3.5e-3,trs1=2.2e-3,trs2=2.5e-9,cjo=.9e-9,m=5.1e-1,tt=1e-9,xti=3.9)
dp..model dbreakmod = (rs=1.5e-1,trs1=1e-3,trs2=-8.9e-6)
dp..model dplcapmod = (cjo=4.1e-10,isl=10e-30,nl=10,m=0.45)
m..model mmedmod = (type=_n,vto=3.5,kp=6,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=4.3,kp=50,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=2.91,kp=0.05,is=1e-30, tox=1,rs=0.1)
LDRAIN
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-5,voff=-2)
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-2,voff=-5)
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-1.5,voff=.5)
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=.5,voff=-1.5)
c.ca n12 n8 = 5.1e-10
DPLCAP
5
DRAIN
2
10
RLDRAIN
RSLC1
51
RSLC2
c.cb n15 n14 = 5.8e-10
ISCL
c.cin n6 n8 = 1.3e-9
DBREAK
11
50
-
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
RDRAIN
6
8
ESG
DBODY
dp.dplcap n10 n5 = model=dplcapmod
EVTHRES
+
16
21
+
-
19
MWEAK
LGATE
EVTEMP
8
spe.ebreak n11 n7 n17 n18 = 65.40
RGATE
GATE
+
6
-
18
EBREAK
+
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
MMED
1
22
9
20
MSTRO
8
17
RLGATE
18
LSOURCE
CIN
-
SOURCE
3
7
RSOURCE
RLSOURCE
i.it n8 n17 = 1
S1A
S2A
RBREAK
12
15
13
14
l.lgate n1 n9 = 5.2e-9
l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 2.14e-9
17
18
8
13
RVTEMP
19
S1B
S2B
13
CB
+
CA
IT
14
-
+
res.rlgate n1 n9 = 52
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 21.4
VBAT
6
8
5
8
EGS
EDS
+
-
-
8
22
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
RVTHRES
res.rbreak n17 n18 = 1, tc1=9e-4,tc2=-5e-7
res.rdrain n50 n16 = 3.1e-3, tc1=1.3e-2,tc2=5.2e-5
res.rgate n9 n20 = 3.71
res.rslc1 n5 n51 = 1e-6, tc1=1.8e-3,tc2=1.7e-5
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 5.5e-3, tc1=1e-3,tc2=1e-6
res.rvthres n22 n8 = 1, tc1=-5.3e-3,tc2=-1.0e-5
res.rvtemp n18 n19 = 1, tc1=-2.5e-3,tc2=1e-6
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/160))** 6))
}}
©2010 Fairchild Semiconductor Corporation
FDD13AN06A0_F085 Rev. A
PSPICE Thermal Model
JUNCTION
th
REV 22 August 2002
FDD13AN06A0T
CTHERM1 TH 6 9.7e-4
CTHERM2 6 5 6.2e-3
CTHERM3 5 4 4.6e-3
CTHERM4 4 3 4.9e-3
CTHERM5 3 2 8e-3
RTHERM1
RTHERM2
RTHERM3
RTHERM4
RTHERM5
RTHERM6
CTHERM1
CTHERM6 2 TL 4.2e-2
6
RTHERM1 TH 6 5.24e-2
RTHERM2 6 5 10.08e-2
RTHERM3 5 4 4.28e-1
RTHERM4 4 3 1.8e-1
RTHERM5 3 2 1.9e-1
RTHERM6 2 TL 2.1e-1
CTHERM2
CTHERM3
CTHERM4
CTHERM5
CTHERM6
5
SABER Thermal Model
SABER thermal model FDD13AN06A0T
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 =9.7e-4
ctherm.ctherm2 6 5 =6.2e-3
ctherm.ctherm3 5 4 =4.6e-3
ctherm.ctherm4 4 3 =4.9e-3
ctherm.ctherm5 3 2 =8e-3
ctherm.ctherm6 2 tl =4.2e-2
4
3
2
rtherm.rtherm1 th 6 =5.24e-2
rtherm.rtherm2 6 5 =10.08e-2
rtherm.rtherm3 5 4 =4.28e-1
rtherm.rtherm4 4 3 =1.8e-1
rtherm.rtherm5 3 2 =1.9e-1
rtherm.rtherm6 2 tl =2.1e-1
}
tl
CASE
©2010 Fairchild Semiconductor Corporation
FDD13AN06A0_F085 Rev. A
TRADEMARKS
The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not
intended to be an exhaustive list of all such trademarks.
®
*
AccuPowerA
Auto-SPMA
Build it NowA
CorePLUSA
CorePOWERA
CROSSVOLTA
CTLA
F-PFSA
Power-SPMA
PowerTrench®
PowerXS™
FRFET®
The Power Franchise®
Global Power ResourceSM
Green FPSA
Green FPSA e-SeriesA
GmaxA
GTOA
IntelliMAXA
Programmable Active DroopA
QFET®
QSA
Quiet SeriesA
RapidConfigureA
A
TinyBoostA
TinyBuckA
TinyCalcA
Current Transfer LogicA
DEUXPEED®
Dual Cool™
TinyLogic®
ISOPLANARA
MegaBuckA
MICROCOUPLERA
MicroFETA
TINYOPTOA
TinyPowerA
TinyPWMA
TinyWireA
TriFault DetectA
TRUECURRENTA*
ꢀSerDesA
Saving our world, 1mW/W/kW at a time™
SignalWiseA
EcoSPARK®
EfficientMaxA
SmartMaxA
ESBCA
MicroPakA
SMART STARTA
®
SPM®
MicroPak2A
MillerDriveA
MotionMaxA
Motion-SPMA
OptoHiT™
Fairchild®
STEALTHA
Fairchild Semiconductor®
FACT Quiet SeriesA
FACT®
SuperFETA
SuperSOTA-3
SuperSOTA-6
SuperSOTA-8
SupreMOSA
OPTOLOGIC®
UHC®
FAST®
OPTOPLANAR®
Ultra FRFETA
UniFETA
VCXA
FastvCoreA
®
SyncFETA
Sync-Lock™
FETBenchA
FlashWriter®
*
PDP SPM™
VisualMaxA
XS™
FPSA
* Trademarks of System General Corporation, used under license by Fairchild Semiconductor.
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE
RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR
CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE
SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN,
WHICH COVERS THESE PRODUCTS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE
EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems which, (a) are
intended for surgical implant into the body or (b) support or sustain life,
and (c) whose failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be reasonably
expected to result in a significant injury of the user.
2. A critical component in any component of a life support, device, or
system whose failure to perform can be reasonably expected to
cause the failure of the life support device or system, or to affect its
safety or effectiveness.
ANTI-COUNTERFEITING POLICY
Fairchild Semiconductor Corporation's Anti-Counterfeiting Policy. Fairchild's Anti-Counterfeiting Policy is also stated on our external website, www.fairchildsemi.com,
under Sales Support.
Counterfeiting of semiconductor parts is a growing problem in the industry. All manufacturers of semiconductor products are experiencing counterfeiting of their parts.
Customers who inadvertently purchase counterfeit parts experience many problems such as loss of brand reputation, substandard performance, failed applications,
and increased cost of production and manufacturing delays. Fairchild is taking strong measures to protect ourselves and our customers from the proliferation of
counterfeit parts. Fairchild strongly encourages customers to purchase Fairchild parts either directly from Fairchild or from Authorized Fairchild Distributors who are
listed by country on our web page cited above. Products customers buy either from Fairchild directly or from Authorized Fairchild Distributors are genuine parts, have
full traceability, meet Fairchild's quality standards for handling and storage and provide access to Fairchild's full range of up-to-date technical and product information.
Fairchild and our Authorized Distributors will stand behind all warranties and will appropriately address any warranty issues that may arise. Fairchild will not provide
any warranty coverage or other assistance for parts bought from Unauthorized Sources. Fairchild is committed to combat this global problem and encourage our
customers to do their part in stopping this practice by buying direct or from authorized distributors.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status
Definition
Datasheet contains the design specifications for product development. Specifications may change in
any manner without notice.
Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild
Semiconductor reserves the right to make changes at any time without notice to improve design.
Datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes
at any time without notice to improve the design.
Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor.
The datasheet is for reference information only.
Advance Information
Preliminary
Formative / In Design
First Production
Full Production
Not In Production
No Identification Needed
Obsolete
Rev. I48
© Fairchild Semiconductor Corporation
www.fairchildsemi.com
相关型号：
FDD13AN06A0_F085
Power Field-Effect Transistor, 9.9A I(D), 60V, 0.0135ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-252AA, ROHS COMPLIANT PACKAGE-3
FAIRCHILD
©2020 ICPDF网 联系我们和版权申明