FDP10AN06A0_技术文档

July 2002

FDB10AN06A0 / FDP10AN06A0

N-Channel PowerTrench^®MOSFET

60V, 75A, 10.5mΩ

Features

Applications

•

r_DS(ON)= 9.5mΩ (Typ.), V_GS= 10V, I_D= 75A

Q_g(tot) = 28nC (Typ.), V_GS= 10V

Low Miller Charge

•

Motor / Body Load Control

ABS Systems

Powertrain Management

Low Qrr Body Diode

Injection Systems

UIS Capability (Single Pulse and Repetitive Pulse)

Qualified to AEC Q101

DC-DC converters and Off-line UPS

Distributed Power Architectures and VRMs

Primary Switch for 12V and 24V systems

Formerly developmental type 82560

D

S

DRAIN

(FLANGE)

GATE

SOURCE

DRAIN

GATE

G

DRAIN

SOURCE

(FLANGE)

TO-263AB

FDB SERIES

TO-220AB

FDP SERIES

MOSFET Maximum Ratings T_C= 25°C unless otherwise noted

Symbol

V_DSS

V_GS

Parameter

Ratings

Units

Drain to Source Voltage

Gate to Source Voltage

Drain Current

60

V

±20

Continuous (T_C= 25^oC, V_GS= 10V)

Continuous (T_C= 100^oC, V_GS= 10V)

Continuous (T_amb= 25^oC, V_GS= 10V) with R_θJA= 43^oC/W)

Pulsed

75

A

I_D

54

12

A

Figure 4

429

A

E_AS

Single Pulse Avalanche Energy (Note 1)

Power dissipation

mJ

W

135

P_D

Derate above 25^oC

0.9

W/^oC

^oC

T_J, T_STG

Operating and Storage Temperature

-55 to 175

Thermal Characteristics

R_θJC

R_θJA

Thermal Resistance Junction to Case TO-220, TO-263

1.11

62

^oC/W

Thermal Resistance Junction to Ambient TO-220, TO-263 (Note 2)

Thermal Resistance Junction to Ambient TO-263, 1in²copper pad area

43

This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a

copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/

Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.

All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems

certification.

FDB10AN06A0 / FDP10AN06A0 Rev. A

Package Marking and Ordering Information

Device Marking

FDB10AN06A0

FDP10AN06A0

Device

Package

TO-263AB

TO-220AB

Reel Size

330mm

Tube

Tape Width

24mm

Quantity

800 units

50 units

FDB10AN06A0

FDP10AN06A0

N/A

Electrical Characteristics ^T_C= 25°C unless otherwise noted

Symbol

Parameter

Test Conditions

Min

Typ

Max

Units

Off Characteristics

B_VDSS

Drain to Source Breakdown Voltage

Zero Gate Voltage Drain Current

Gate to Source Leakage Current

I_D= 250µA, V_GS= 0V

60

-

V

_DS= 50V

1

I_DSS

µA

nA

V_GS= 0V

T_C= 150^oC

-

250

±100

I_GSS

V_GS= ±20V

-

On Characteristics

V_GS(TH)

Gate to Source Threshold Voltage

V_GS= V_DS, I_D= 250µA

2

-

4

V

I

_D= 75A, V_GS= 10V

_D= 37A, V_GS= 6V

0.0095 0.0105

0.017 0.027

-

r_DS(ON)

Drain to Source On Resistance

Ω

I_D= 75A, V_GS= 10V,

T_J= 175^oC

-

0.021 0.023

Dynamic Characteristics

C_ISS

Input Capacitance

-

1840

340

110

28

-

pF

nC

V_DS= 25V, V_GS= 0V,

f = 1MHz

C_OSS

C_RSS

Q_g(TOT)

Q_g(TH)

Q_gs

Output Capacitance

Reverse Transfer Capacitance

Total Gate Charge at 10V

Threshold Gate Charge

-

V_GS= 0V to 10V

37

4.6

-

V_GS= 0V to 2V

-

3.5

V_DD= 30V

_D= 75A

I_g= 1.0mA

Gate to Source Gate Charge

Gate Charge Threshold to Plateau

Gate to Drain “Miller” Charge

I

11.7

8.2

Q_gs2

-

Q_gd

7.4

-

Switching Characteristics (V_GS= 10V)

t_ON

t_d(ON)

t_r

Turn-On Time

Turn-On Delay Time

Rise Time

-

8

206

ns

-

128

27

36

-

V

_DD= 30V, I_D= 75A

_GS= 10V, R_GS= 10Ω

t_d(OFF)

t_f

Turn-Off Delay Time

Fall Time

-

t_OFF

Turn-Off Time

94

Drain-Source Diode Characteristics

I

_SD= 75A

_SD= 40A

-

1.25

1.0

27

V

V_SD

Source to Drain Diode Voltage

t_rr

Reverse Recovery Time

I_SD= 75A, dI_SD/dt = 100A/µs

ns

nC

Q_RR

Reverse Recovered Charge

23

Notes:

1: Starting T = 25°C, L = 8.58mH, I = 10A.

J

AS

2: Pulse Width = 100s

FDB10AN06A0 / FDP10AN06A0 Rev. A

Typical Characteristics T_C= 25°C unless otherwise noted

1.2

80

1.0

60

0.8

0.6

40

0.4

20

0.2

0

150

0

25

50

75

100

175

125

o

25

50

75

100

125

150

175

o

T

, CASE TEMPERATURE ( C)

C

T

, CASE TEMPERATURE ( C)

C

Figure 1. Normalized Power Dissipation vs

Ambient Temperature

Figure 2. Maximum Continuous Drain Current vs

Case Temperature

2

DUTY CYCLE - DESCENDING ORDER

0.5

0.2

1

0.1

0.05

0.02

0.01

P

DM

0.1

t

1

t

2

NOTES:

DUTY FACTOR: D = t /t

1

2

SINGLE PULSE

0.01

PEAK T = P

x Z

x R

+ T

J

DM

θJC

θJC C

-5

-4

-3

-2

-1

0

1

10

t, RECTANGULAR PULSE DURATION (s)

10

Figure 3. Normalized Maximum Transient Thermal Impedance

1000

o

T

= 25 C

C

FOR TEMPERATURES

TRANSCONDUCTANCE

MAY LIMIT CURRENT

IN THIS REGION

o

ABOVE 25 C DERATE PEAK

CURRENT AS FOLLOWS:

175 - T

150

C

I = I

25

V

= 10V

GS

100

70

-5

-4

-3

-2

-1

0

1

10

t, PULSE WIDTH (s)

10

Figure 4. Peak Current Capability

FDB10AN06A0 / FDP10AN06A0 Rev. A

Typical Characteristics T_C= 25°C unless otherwise noted

500

100

500

If R = 0

= (L)(I )/(1.3*RATED BV

t

AV

- V

DD

)

10µs

AS

DSS

If R ≠ 0

= (L/R)ln[(I *R)/(1.3*RATED BV

t

- V ) +1]

DD

100µs

AV

AS

DSS

100

1ms

o

STARTING T = 25 C

J

OPERATION IN THIS

AREA MAY BE

10

1

LIMITED BY r

10ms

DS(ON)

10

DC

SINGLE PULSE

o

STARTING T = 150 C

J

T

= MAX RATED

J

o

T

= 25 C

C

0.1

1

10

, DRAIN TO SOURCE VOLTAGE (V)

100

0.1

t , TIME IN AVALANCHE (ms)

AV

1

10

0.01

V

DS

NOTE: Refer to Fairchild Application Notes AN7514 and AN7515

Figure 6. Unclamped Inductive Switching

Capability

Figure 5. Forward Bias Safe Operating Area

150

PULSE DURATION = 80µs

V

= 10V

GS

V

= 7V

GS

DUTY CYCLE = 0.5% MAX

125

100

75

50

25

0

125

100

75

50

25

0

V

= 15V

DD

o

T

= 25 C

J

V

= 6V

GS

o

T

= 25 C

C

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

o

T

= 175 C

J

o

T

= -55 C

J

V

= 5V

GS

4

5

6

7

8

0

1

V , DRAIN TO SOURCE VOLTAGE (V)

DS

2

3

4

V

, GATE TO SOURCE VOLTAGE (V)

GS

Figure 7. Transfer Characteristics

Figure 8. Saturation Characteristics

25

20

15

10

5

2.5

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

2.0

1.5

1.0

0.5

V

= 6V

GS

V

= 10V

GS

V

= 10V, I = 75A

GS

D

0

20

40

I , DRAIN CURRENT (A)

60

80

-80

-40

0

40

80

120

160

200

o

T , JUNCTION TEMPERATURE ( C)

D

J

Figure 9. Drain to Source On Resistance vs Drain

Current

Figure 10. Normalized Drain to Source On

Resistance vs Junction Temperature

FDB10AN06A0 / FDP10AN06A0 Rev. A

Typical Characteristics T_C= 25°C unless otherwise noted

1.2

1.0

0.8

0.6

0.4

1.2

1.1

1.0

0.9

V

= V , I = 250µA

DS D

GS

I

= 250µA

D

-80

-40

0

40

80

120

o

160

200

-80

-40

0

40

80

120

160

200

o

T , JUNCTION TEMPERATURE ( C)

J

Figure 11. Normalized Gate Threshold Voltage vs

Junction Temperature

Figure 12. Normalized Drain to Source

Breakdown Voltage vs Junction Temperature

3000

10

V

= 30V

DD

C

= C + C

GS GD

ISS

8

6

4

2

0

1000

C

+ C

OSS

DS GD

C

= C

GD

RSS

WAVEFORMS IN

DESCENDING ORDER:

100

50

I

= 75A

= 12A

D

V

= 0V, f = 1MHz

GS

0

5

10

15

20

25

30

0.1

1

10

60

V

, DRAIN TO SOURCE VOLTAGE (V)

Q , GATE CHARGE (nC)

g

DS

Figure 13. Capacitance vs Drain to Source

Voltage

Figure 14. Gate Charge Waveforms for Constant

Gate Currents

FDB10AN06A0 / FDP10AN06A0 Rev. A

Test Circuits and Waveforms

V

DS

BV

DSS

t

P

L

V

DS

I

VARY t TO OBTAIN

P

AS

+

-

V

DD

R

REQUIRED PEAK I

G

AS

V

DD

V

GS

DUT

t

P

I

0V

AS

0

0.01Ω

t

AV

Figure 15. Unclamped Energy Test Circuit

Figure 16. Unclamped Energy Waveforms

V

DS

V

Q

DD

g(TOT)

V

L

DS

V

GS

V

= 10V

GS

V

GS

+

Q

gs2

V

DD

-

DUT

V

= 2V

GS

I

g(REF)

0

Q

g(TH)

Q

gs

gd

I

g(REF)

0

Figure 17. Gate Charge Test Circuit

Figure 18. Gate Charge Waveforms

V

DS

t

ON

OFF

t

d(OFF)

t

d(ON)

R

t

f

L

r

V

DS

90%

+

V

GS

V

DD

10%

-

0

DUT

90%

50%

R

GS

V

GS

50%

PULSE WIDTH

V

10%

GS

0

Figure 19. Switching Time Test Circuit

Figure 20. Switching Time Waveforms

FDB10AN06A0 / FDP10AN06A0 Rev. A

Thermal Resistance vs. Mounting Pad Area

The maximum rated junction temperature, T_JM, and the

thermal resistance of the heat dissipating path determines

the maximum allowable device power dissipation, P_DM, in an

80

60

40

20

R

= 26.51+ 19.84/(0.262+Area) EQ.2

θJA

R

= 26.51+ 128/(1.69+Area) EQ.3

θJA

application.

Therefore the application’s ambient

temperature, T_A(^oC), and thermal resistance R_θJA(^oC/W)

must be reviewed to ensure that T_JMis never exceeded.

Equation 1 mathematically represents the relationship and

serves as the basis for establishing the rating of the part.

(T

– T )

JM

A

(EQ. 1)

P

= -----------------------------

DM

R_{θ JA}

In using surface mount devices such as the TO-263

package, the environment in which it is applied will have a

significant influence on the part’s current and maximum

power dissipation ratings. Precise determination of P_DMis

complex and influenced by many factors:

0.1

(0.645)

1

10

(6.45)

(64.5)

2

AREA, TOP COPPER AREA in (cm )

Figure 21. Thermal Resistance vs Mounting

Pad Area

1. Mounting pad area onto which the device is attached and

whether there is copper on one side or both sides of the

board.

2. The number of copper layers and the thickness of the

board.

3. The use of external heat sinks.

4. The use of thermal vias.

5. Air flow and board orientation.

6. For non steady state applications, the pulse width, the

duty cycle and the transient thermal response of the part,

the board and the environment they are in.

Fairchild provides thermal information to assist the

designer’s preliminary application evaluation. Figure 21

defines the R_θJAfor the device as a function of the top

copper (component side) area. This is for a horizontally

positioned FR-4 board with 1oz copper after 1000 seconds

of steady state power with no air flow. This graph provides

the necessary information for calculation of the steady state

junction temperature or power dissipation. Pulse

applications can be evaluated using the Fairchild device

Spice thermal model or manually utilizing the normalized

maximum transient thermal impedance curve.

Thermal resistances corresponding to other copper areas

can be obtained from Figure 21 or by calculation using

Equation 2 or 3. Equation 2 is used for copper area defined

in inches square and equation 3 is for area in centimeters

square. The area, in square inches or square centimeters is

the top copper area including the gate and source pads.

19.84

(0.262 + Area)

R

= 26.51 + ------------------------------------

(EQ. 2)

θ JA

Area in Inches Squared

128

R

= 26.51 + ---------------------------------

(EQ. 3)

(1.69 + Area)

Area in Centimeters Squared

FDB10AN06A0 / FDP10AN06A0 Rev. A

PSPICE Electrical Model

.SUBCKT FDP10AN06A0 2 1 3 ;

Ca 12 8 7e-10

rev July 2002

Cb 15 14 7e-10

Cin 6 8 1.8e-9

LDRAIN

DPLCAP

DRAIN

2

5

10

Dbody 7 5 DbodyMOD

Dbreak 5 11 DbreakMOD

Dplcap 10 5 DplcapMOD

RLDRAIN

RSLC1

51

DBREAK

+

RSLC2

5

ESLC

11

51

Ebreak 11 7 17 18 68.4

Eds 14 8 5 8 1

Egs 13 8 6 8 1

Esg 6 10 6 8 1

Evthres 6 21 19 8 1

Evtemp 20 6 18 22 1

-

+

50

-

17

DBODY

RDRAIN

6

8

EBREAK 18

-

ESG

EVTHRES

+

16

21

+

-

19

8

MWEAK

LGATE

EVTEMP

RGATE

GATE

1

6

+

-

18

22

MMED

It 8 17 1

9

20

MSTRO

8

RLGATE

Lgate 1 9 7e-9

Ldrain 2 5 1.0e-9

LSOURCE

CIN

SOURCE

3

7

Lsource 3 7 3e-9

RSOURCE

RLSOURCE

RLgate 1 9 70

RLdrain 2 5 10

RLsource 3 7 30

S1A

S2A

RBREAK

12

15

13

14

13

17

18

8

RVTEMP

19

-

S1B

S2B

Mmed 16 6 8 8 MmedMOD

Mstro 16 6 8 8 MstroMOD

Mweak 16 21 8 8 MweakMOD

Rbreak 17 18 RbreakMOD 1

Rdrain 50 16 RdrainMOD 1.6e-3

Rgate 9 20 3.6

13

CB

CA

IT

14

+

VBAT

6

8

5

8

EGS

EDS

+

-

8

22

RVTHRES

RSLC1 5 51 RSLCMOD 1e-6

RSLC2 5 50 1e3

Rsource 8 7 RsourceMOD 6e-3

Rvthres 22 8 RvthresMOD 1

Rvtemp 18 19 RvtempMOD 1

S1a 6 12 13 8 S1AMOD

S1b 13 12 13 8 S1BMOD

S2a 6 15 14 13 S2AMOD

S2b 13 15 14 13 S2BMOD

Vbat 22 19 DC 1

ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*250),7))}

.MODEL DbodyMOD D (IS=9E-12 N=1.06 RS=2.7e-3 TRS1=2.4e-3 TRS2=1.1e-6

+ CJO=1.25e-9 M=5.3e-1 TT=4e-9 XTI=3.9)

.MODEL DbreakMOD D (RS=2.7e-1 TRS1=1e-3 TRS2=-8.9e-6)

.MODEL DplcapMOD D (CJO=4.7e-10 IS=1e-30 N=10 M=0.44)

.MODEL MmedMOD NMOS (VTO=3.6 KP=5.5 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=3.6)

.MODEL MstroMOD NMOS (VTO=4.4 KP=80 IS=1e-30 N=10 TOX=1 L=1u W=1u)

.MODEL MweakMOD NMOS (VTO=3.06 KP=0.03 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=36 RS=0.1)

.MODEL RbreakMOD RES (TC1=9e-4 TC2=5e-7)

.MODEL RdrainMOD RES (TC1=2.5e-2 TC2=7.8e-5)

.MODEL RSLCMOD RES (TC1=1e-3 TC2=3.5e-5)

.MODEL RsourceMOD RES (TC1=1e-3 TC2=1e-6)

.MODEL RvthresMOD RES (TC1=-5.9e-3 TC2=-1.3e-5)

.MODEL RvtempMOD RES (TC1=-2.3e-3 TC2=1.3e-6)

.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-8 VOFF=-5)

.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-5 VOFF=-8)

.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2 VOFF=-1.5)

.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.5 VOFF=-2)

.ENDS

Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global

Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank

Wheatley.

FDB10AN06A0 / FDP10AN06A0 Rev. A

SABER Electrical Model

REV July 2002

template FDP10AN06A0 n2,n1,n3

electrical n2,n1,n3

{

var i iscl

dp..model dbodymod = (isl=9e-12,nl=1.06,rs=2.7e-3,trs1=2.4e-3,trs2=1.1e-6,cjo=1.25e-9,m=5.3e-1,tt=4e-9,xti=3.9)

dp..model dbreakmod = (rs=2.7e-1,trs1=1e-3,trs2=-8.9e-6)

dp..model dplcapmod = (cjo=4.7e-10,isl=10e-30,nl=10,m=0.44)

m..model mmedmod = (type=_n,vto=3.6,kp=5.5,is=1e-30, tox=1)

m..model mstrongmod = (type=_n,vto=4.4,kp=80,is=1e-30, tox=1)

m..model mweakmod = (type=_n,vto=3.06,kp=0.03,is=1e-30, tox=1,rs=0.1)

LDRAIN

sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-8,voff=-5)

sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-5,voff=-8)

sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-2,voff=-1.5)

sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=-1.5,voff=-2)

c.ca n12 n8 = 7e-10

DPLCAP

DRAIN

2

5

10

RLDRAIN

RSLC1

51

RSLC2

c.cb n15 n14 = 7e-10

c.cin n6 n8 = 1.8e-9

ISCL

DBREAK

11

50

-

dp.dbody n7 n5 = model=dbodymod

dp.dbreak n5 n11 = model=dbreakmod

dp.dplcap n10 n5 = model=dplcapmod

RDRAIN

6

8

ESG

DBODY

EVTHRES

+

16

21

+

-

19

8

MWEAK

LGATE

EVTEMP

spe.ebreak n11 n7 n17 n18 = 68.4

RGATE

GATE

1

+

6

-

18

22

EBREAK

+

spe.eds n14 n8 n5 n8 = 1

spe.egs n13 n8 n6 n8 = 1

spe.esg n6 n10 n6 n8 = 1

spe.evthres n6 n21 n19 n8 = 1

spe.evtemp n20 n6 n18 n22 = 1

MMED

9

20

MSTRO

8

17

18

-

RLGATE

LSOURCE

CIN

SOURCE

3

7

RSOURCE

RLSOURCE

i.it n8 n17 = 1

S1A

S2A

RBREAK

12

15

13

8

14

13

17

18

l.lgate n1 n9 = 7e-9

l.ldrain n2 n5 = 1.0e-9

l.lsource n3 n7 = 3e-9

RVTEMP

19

S1B

S2B

13

CB

CA

IT

14

-

+

res.rlgate n1 n9 = 70

res.rldrain n2 n5 = 10

res.rlsource n3 n7 = 30

VBAT

6

8

5

8

EGS

EDS

+

-

8

22

RVTHRES

m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u

m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u

m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u

res.rbreak n17 n18 = 1, tc1=9e-4,tc2=5e-7

res.rdrain n50 n16 = 1.6e-3, tc1=2.5e-2,tc2=7.8e-5

res.rgate n9 n20 = 3.6

res.rslc1 n5 n51 = 1e-6, tc1=1e-3,tc2=3.5e-5

res.rslc2 n5 n50 = 1e3

res.rsource n8 n7 = 6e-3, tc1=1e-3,tc2=1e-6

res.rvthres n22 n8 = 1, tc1=-5.9e-3,tc2=-1.3e-5

res.rvtemp n18 n19 = 1, tc1=-2.3e-3,tc2=1.3e-6

sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod

sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod

sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod

sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod

v.vbat n22 n19 = dc=1

equations {

i (n51->n50) +=iscl

iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/250))** 7))

FDB10AN06A0 / FDP10AN06A0 Rev. A

SPICE Thermal Model

JUNCTION

th

REV 23 July 2002

FDP10AN06A0T

CTHERM1 TH 6 3.2e-3

CTHERM2 6 5 3.3e-3

CTHERM3 5 4 3.4e-3

CTHERM4 4 3 3.5e-3

CTHERM5 3 2 6.4e-3

CTHERM6 2 TL 1.9e-2

RTHERM1

RTHERM2

RTHERM3

RTHERM4

RTHERM5

RTHERM6

CTHERM1

6

RTHERM1 TH 6 5.5e-4

RTHERM2 6 5 5.0e-3

RTHERM3 5 4 4.5e-2

RTHERM4 4 3 1.5e-1

RTHERM5 3 2 3.37e-1

RTHERM6 2 TL 3.5e-1

CTHERM2

CTHERM3

CTHERM4

CTHERM5

CTHERM6

5

SABER Thermal Model

SABER thermal model FDP10AN06A0T

template thermal_model th tl

thermal_c th, tl

{

4

3

2

ctherm.ctherm1 th 6 =3.2e-3

ctherm.ctherm2 6 5 =3.3e-3

ctherm.ctherm3 5 4 =3.4e-3

ctherm.ctherm4 4 3 =3.5e-3

ctherm.ctherm5 3 2 =6.4e-3

ctherm.ctherm6 2 tl =1.9e-2

rtherm.rtherm1 th 6 =5.5e-4

rtherm.rtherm2 6 5 =5.0e-3

rtherm.rtherm3 5 4 =4.5e-2

rtherm.rtherm4 4 3 =1.5e-1

rtherm.rtherm5 3 2 =3.37e-1

rtherm.rtherm6 2 tl =3.5e-1

}

tl

CASE

FDB10AN06A0 / FDP10AN06A0 Rev. A

TRADEMARKS

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not

intended to be an exhaustive list of all such trademarks.

ACEx™

FACT™

ImpliedDisconnect™ PACMAN™

SPM™

ActiveArray™

Bottomless™

CoolFET™

CROSSVOLT™ FRFET™

DOME™

FACT Quiet Series™ ISOPLANAR™

POP™

Stealth™

®

FAST

FASTr™

LittleFET™

MicroFET™

MicroPak™

Power247™

PowerTrench

QFET™

SuperSOT™-3

SuperSOT™-6

SuperSOT™-8

SyncFET™

®

GlobalOptoisolator™ MICROWIRE™

QS™

EcoSPARK™

E CMOS™

EnSigna™

GTO™

MSX™

MSXPro™

OCX™

OCXPro™

OPTOLOGIC

OPTOPLANAR™

QT Optoelectronics™ TinyLogic™

2

HiSeC™

Quiet Series™

TruTranslation™

2

I C™

RapidConfigure™

RapidConnect™

SILENT SWITCHER VCX™

SMART START™

UHC™

UltraFET

®

Across the board. Around the world.™

The Power Franchise™

®

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY

PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY

LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;

NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR

CORPORATION.

As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the body,

or (b) support or sustain life, or (c) whose failure to perform

when properly used in accordance with instructions for use

provided in the labeling, can be reasonably expected to

result in significant injury to the user.

2. A critical component is any component of a life support

device or system whose failure to perform can be

reasonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification

Product Status

Definition

Advance Information

Formative or In

Design

This datasheet contains the design specifications for

product development. Specifications may change in

any manner without notice.

Preliminary

First Production

This datasheet contains preliminary data, and

supplementary data will be published at a later date.

Fairchild Semiconductor reserves the right to make

changes at any time without notice in order to improve

design.

No Identification Needed

Obsolete

Full Production

This datasheet contains final specifications. Fairchild

Semiconductor reserves the right to make changes at

any time without notice in order to improve design.

Not In Production

This datasheet contains specifications on a product

that has been discontinued by Fairchild semiconductor.

The datasheet is printed for reference information only.

Rev. I


型号：	FDP10AN06A0
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	N-Channel PowerTrench MOSFET 60V, 75A, 10.5mз N沟道PowerTrench MOSFET的60V ， 75A ， 10.5mз
文件：	总11页 (文件大小：259K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

FDP10AN06A0 [FAIRCHILD]

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