FDPF20N50F [FAIRCHILD]

Power Field-Effect Transistor, N-Channel, Metal-oxide Semiconductor FET;
FDPF20N50F
型号: FDPF20N50F
厂家: FAIRCHILD SEMICONDUCTOR    FAIRCHILD SEMICONDUCTOR
描述:

Power Field-Effect Transistor, N-Channel, Metal-oxide Semiconductor FET

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中文:  中文翻译
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August 2007  
TM  
UniFET  
FDP20N50F / FDPF20N50F  
tm  
N-Channel MOSFET  
500V, 20A, 0.26Ω  
Features  
Description  
RDS(on) = 0.21Ω ( Typ.)@ VGS = 10V, ID = 10A  
Low gate charge ( Typ. 51.7nC)  
Low Crss ( Typ. 33.5pF)  
Fast switching  
These N-Channel enhancement mode power field effect transis-  
tors are produced using Fairchild’s proprietary, planar stripe,  
DMOS technology.  
This advance technology has been especially tailored to mini-  
mize on-state resistance, provide superior switching perfor-  
mance, and withstand high energy pulse in the avalanche and  
commutation mode. These devices are well suited for high effi-  
cient switching mode power supplies and active power factor  
correction.  
100% avalanche tested  
Improve dv/dt capability  
RoHS compliant  
D
G
TO-220  
FDP Series  
TO-220F  
FDPF Series  
G
S
D
G D S  
S
MOSFET Maximum Ratings TC = 25oC unless otherwise noted  
Symbol  
VDSS  
VGSS  
Parameter  
FDP20N50F FDPF20N50F  
Units  
Drain to Source Voltage  
Gate to Source Voltage  
500  
±30  
V
V
-Continuous (TC = 25oC)  
-Continuous (TC = 100oC)  
- P uls ed  
20  
12.9  
80  
20*  
12.9*  
80*  
ID  
D r a in C u r r e n t  
A
IDM  
D rai n Cur rent  
(Note 1)  
(Note 2)  
(Note 1)  
(Note 1)  
(Note 3)  
A
mJ  
A
EAS  
IAR  
Single Pulsed Avalanche Energy  
Avalanche Current  
1110  
20  
EAR  
dv/dt  
Repetitive Avalanche Energy  
Peak Diode Recovery dv/dt  
25  
mJ  
V/ns  
W
W/oC  
oC  
4.5  
(TC = 25oC)  
- Derate above 25oC  
250  
2.0  
38.5  
0.3  
PD  
Power Dissipation  
TJ, TSTG  
TL  
Operating and Storage Temperature Range  
-55 to +150  
Maximum Lead Temperature for Soldering Purpose,  
1/8” from Case for 5 Seconds  
300  
oC  
*Drain current limited by maximum junction temperature  
Thermal Characteristics  
Symbol  
Parameter  
Thermal Resistance, Junction to Case  
FDP20N50F FDPF20N50F  
Units  
RθJC  
RθCS  
RθJA  
0.5  
0.5  
3.3  
-
Thermal Resistance, Case to Sink Typ.  
Thermal Resistance, Junction to Ambient  
oC/W  
62.5  
62.5  
©2007 Fairchild Semiconductor Corporation  
FDP20N50F / FDPF20N50F Rev. A  
1
www.fairchildsemi.com  
Package Marking and Ordering Information TC = 25oC unless otherwise noted  
Device Marking  
FDP20N50F  
Device  
Package  
TO-220  
Reel Size  
Tape Width  
Quantity  
FDP20N50F  
FDPF20N50F  
-
-
-
-
50  
50  
FDPF20N50F  
TO-220F  
Electrical Characteristics  
Symbol  
Parameter  
Test Conditions  
Min.  
Typ.  
Max.  
Units  
Off Characteristics  
BVDSS  
Drain to Source Breakdown Voltage  
ID = 250μA, VGS = 0V, TJ = 25oC  
500  
-
-
-
-
V
ΔBVDSS  
Breakdown Voltage Temperature  
Coefficient  
I
D = 250μA, Referenced to 25oC  
0.7  
V/oC  
/
ΔTJ  
V
DS = 500V, VGS = 0V  
-
-
-
-
-
-
1
IDSS  
Zero Gate Voltage Drain Current  
Gate to Body Leakage Current  
μA  
VDS = 400V, TC = 125oC  
10  
IGSS  
VGS = ±30V, VDS = 0V  
±100  
nA  
On Characteristics  
VGS(th)  
RDS(on)  
gFS  
Gate Threshold Voltage  
VGS = VDS, ID = 250μA  
VGS = 10V, ID = 10A  
VDS = 20V, ID = 10A  
3.0  
-
-
5.0  
0.26  
-
V
Ω
S
Static Drain to Source On Resistance  
Forward Transconductance  
0.21  
25  
(Note 4)  
-
Dynamic Characteristics  
Ciss  
Input Capacitance  
-
-
-
-
-
2550  
350  
27  
3390  
465  
40  
pF  
pF  
pF  
nC  
nC  
VDS = 25V, VGS = 0V  
f = 1MHz  
Coss  
Crss  
Qg(tot)  
Qgs  
Output Capacitance  
Reverse Transfer Capacitance  
Total Gate Charge at 10V  
Gate to Source Gate Charge  
50  
65  
V
V
DS = 400V, ID = 20A  
GS = 10V  
14  
-
Qgd  
Gate to Drain “Miller” Charge  
-
20  
-
nC  
(Note 4, 5)  
Switching Characteristics  
td(on)  
tr  
td(off)  
tf  
Turn-On Delay Time  
Turn-On Rise Time  
Turn-Off Delay Time  
Turn-Off Fall Time  
-
-
-
-
45  
120  
100  
60  
100  
250  
210  
130  
ns  
ns  
ns  
ns  
VDD = 250V, ID = 20A  
G = 25Ω  
R
(Note 4, 5)  
Drain-Source Diode Characteristics  
IS  
Maximum Continuous Drain to Source Diode Forward Current  
Maximum Pulsed Drain to Source Diode Forward Current  
-
-
-
-
-
-
-
20  
80  
1.5  
-
A
A
ISM  
VSD  
trr  
Drain to Source Diode Forward Voltage  
Reverse Recovery Time  
VGS = 0V, ISD = 20A  
-
V
154  
0.5  
ns  
μC  
VGS = 0V, ISD = 20A  
dIF/dt = 100A/μs  
(Note 4)  
Qrr  
Reverse Recovery Charge  
-
Notes:  
1. Repetitive Rating: Pulse width limited by maximum junction temperature  
2. L = 5mH, I = 20A, V = 50V, R = 25Ω, Starting T = 25°C  
AS  
DD  
G
J
3. I 20A, di/dt 200A/μs, V BV  
, Starting T = 25°C  
SD  
DD  
DSS  
J
4. Pulse Test: Pulse width 300μs, Duty Cycle 2%  
5. Essentially Independent of Operating Temperature Typical Characteristics  
www.fairchildsemi.com  
2
FDP20N50F / FDPF20N50F Rev. A  
Typical Performance Characteristics  
Figure 1. On-Region Characteristics  
Figure 2. Transfer Characteristics  
100  
80  
VGS = 15.0 V  
10.0 V  
8.0 V  
7.0 V  
6.5 V  
6.0 V  
150oC  
10  
5.5 V  
25oC  
10  
1
*Notes:  
*Notes:  
1. 250μs Pulse Test  
1. VDS = 20V  
2. TC = 25oC  
2. 250μs Pulse Test  
1
0.3  
0.1  
4
5
6
7
8
1
10  
20  
VGS,Gate-Source Voltage[V]  
VDS,Drain-Source Voltage[V]  
Figure 3. On-Resistance Variation vs.  
Drain Current and Gate Voltage  
Figure 4. Body Diode Forward Voltage  
Variation vs. Source Current  
and Temperature  
0.5  
400  
100  
0.4  
150oC  
25oC  
10  
VGS = 10V  
0.3  
VGS = 20V  
0.2  
*Notes:  
1. VGS = 0V  
*Note: TJ = 25oC  
50  
ID, Drain Current [A]  
2. 250μs Pulse Test  
1
0.0  
0.1  
0.5  
1.0  
1.5  
2.0  
2.5  
0
25  
75  
VSD, Body Diode Forward Voltage [V]  
Figure 5. Capacitance Characteristics  
Figure 6. Gate Charge Characteristics  
10  
6000  
4500  
3000  
1500  
0
C
C
C
= C + C (C = shorted)  
gs gd ds  
iss  
VDS = 125V  
VDS = 250V  
VDS = 400V  
= C + C  
ds gd  
= C  
gd  
oss  
rss  
Coss  
8
6
4
2
0
*Note:  
1. VGS = 0V  
2. f = 1MHz  
Ciss  
Crss  
*Note: ID = 20A  
40 50  
0.1  
1
10  
50  
0
10  
20  
30  
60  
Qg, Total Gate Charge [nC]  
VDS, Drain-Source Voltage [V]  
www.fairchildsemi.com  
3
FDP20N50F / FDPF20N50F Rev. A  
Typical Performance Characteristics (Continued)  
Figure 7. Breakdown Voltage Variation  
vs. Temperature  
Figure 8. Maximum Safe Operating Area  
- FDP20N50F  
200  
1.2  
1.1  
1.0  
100  
10 μs  
100 μs  
1 ms  
10  
1
10 ms  
100 ms  
Operation in This Area  
is Limited by R DS(on)  
DC  
*Notes:  
1. TC = 25oC  
2. TJ = 150oC  
0.9  
0.1  
0.01  
*Notes:  
1. VGS = 0V  
2. ID = 1mA  
3. Single Pulse  
0.8  
-100  
1
10  
100  
800  
-50  
0
50  
100  
150  
200  
TJ, Junction Temperature [oC]  
VDS, Drain-Source Voltage [V]  
Figure 9. Maximum Safe Operating Area  
- FDPF20N50F  
Figure 10. Maximum Drain Current  
vs. Case Temperature  
200  
100  
25  
20  
15  
10  
5
40μs  
100μs  
10  
1ms  
10ms  
1
Operation in This Area  
is Limited by R DS(on)  
DC  
*Notes:  
1. TC = 25oC  
0.1  
2. TJ = 150oC  
3. Single Pulse  
0.01  
0
25  
1
10  
100  
800  
50  
75  
100  
125  
150  
VDS, Drain-Source Voltage [V]  
TC, Case Temperature [oC]  
Figure 11. Transient Thermal Response Curve - FDP20N50F  
1
0.5  
0.2  
0.1  
0.1  
PDM  
0.05  
t1  
t2  
0.02  
0.01  
*Notes:  
0.01  
1. ZθJC(t) = 0.5oC/W Max.  
2. Duty Factor, D= t1/t2  
3. TJM - TC = PDM * ZθJC(t)  
single pulse  
0.002  
10-5  
10-4  
10-3  
10-2  
10-1  
100  
101  
Rectangular Pulse Duration [sec]  
www.fairchildsemi.com  
4
FDP20N50F / FDPF20N50F Rev. A  
Typical Performance Characteristics (Continued)  
Figure 12. Transient Thermal Response Curve - FDPF20N50F  
5
0.5  
1
0.2  
0.1  
PDM  
0.05  
t1  
t2  
0.1  
0.02  
0.01  
*Notes:  
1. ZθJC(t) = 3.3oC/W Max.  
2. Duty Factor, D= t1/t2  
3. TJM - TC = PDM * ZθJC(t)  
Single pulse  
0.01  
10-4  
10-3  
10-2  
10-1  
100  
101  
102  
103  
Rectangular Pulse Duration [sec]  
www.fairchildsemi.com  
5
FDP20N50F / FDPF20N50F Rev. A  
Gate Charge Test Circuit & Waveform  
Resistive Switching Test Circuit & Waveforms  
Unclamped Inductive Switching Test Circuit & Waveforms  
www.fairchildsemi.com  
6
FDP20N50F / FDPF20N50F Rev. A  
Peak Diode Recovery dv/dt Test Circuit & Waveforms  
+
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V
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www.fairchildsemi.com  
7
FDP20N50F / FDPF20N50F Rev. A  
Mechanical Dimensions  
TO-220  
4.50 ±0.20  
9.90 ±0.20  
(8.70)  
+0.10  
–0.05  
1.30  
ø3.60 ±0.10  
1.27 ±0.10  
1.52 ±0.10  
0.80 ±0.10  
+0.10  
–0.05  
0.50  
2.40 ±0.20  
2.54TYP  
2.54TYP  
[2.54 ±0.20]  
[2.54 ±0.20]  
10.00 ±0.20  
www.fairchildsemi.com  
8
FDP20N50F / FDPF20N50F Rev. A  
Mechanical Dimensions  
TO-220F  
2.54 ±0.20  
10.16 ±0.20  
ø3.18 ±0.10  
(7.00)  
(0.70)  
(1.00x45°)  
MAX1.47  
0.80 ±0.10  
(30  
°
)
#1  
0.35 ±0.10  
+0.10  
–0.05  
0.50  
2.76 ±0.20  
2.54TYP  
2.54TYP  
[2.54 ±0.20  
]
[2.54 ±0.20]  
9.40 ±0.20  
Dimensions in Millimeters  
www.fairchildsemi.com  
9
FDP20N50F / FDPF20N50F Rev. A  
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The following are registered and unregistered trademarks and service marks Fairchild Semiconductor owns or is authorized to use and is not  
intended to be an exhaustive list of all such trademarks.  
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SuperSOT-8  
POWEREDGE®  
Power-SPM™  
PowerTrench®  
Programmable Active Droop™  
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Build it Now™  
CorePLUS™  
CROSSVOLT™  
CTL™  
SyncFET™  
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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS  
HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE  
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS  
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As used herein:  
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which, (a) are intended for surgical implant into the body or  
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when properly used in accordance with instructions for use  
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result in a significant injury of the user.  
device, or system whose failure to perform can be  
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PRODUCT STATUS DEFINITIONS  
Definition of Terms  
Datasheet Identification  
Product Status  
Definition  
Advance Information  
Formative or In Design  
This datasheet contains the design specifications for product  
development. Specifications may change in any manner without notice.  
Preliminary  
First Production  
Full Production  
Not In Production  
This datasheet contains preliminary data; supplementary data will be  
published at a later date. Fairchild Semiconductor reserves the right to  
make changes at any time without notice to improve design.  
No Identification Needed  
Obsolete  
This datasheet contains final specifications. Fairchild Semiconductor  
reserves the right to make changes at any time without notice to improve  
design.  
This datasheet contains specifications on a product that has been  
discontinued by Fairchild Semiconductor. The datasheet is printed for  
reference information only.  
Rev. I31  
© 2007 Fairchild Semiconductor Corporation  
www.fairchildsemi.com  

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