FGB40N6S2S62Z [FAIRCHILD]
Insulated Gate Bipolar Transistor, 75A I(C), 600V V(BR)CES, N-Channel, TO-263AB;
| 型号： | FGB40N6S2S62Z |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Insulated Gate Bipolar Transistor, 75A I(C), 600V V(BR)CES, N-Channel, TO-263AB 栅 瞄准线 功率控制 晶体管 |
| 文件： | 总11页 (文件大小：190K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
July 2001
FGH40N6S2, FGP40N6S2, FGB40N6S2
600V, SMPS II Series N-Channel IGBT
General Description
Features
The FGH40N6S2, FGP40N6S2, and FGB40N6S2 are Low
Gate Charge, Low Plateau Voltage SMPS II IGBTs combin-
ing the fast switching speed of the SMPS IGBTs along with
lower gate charge and plateau voltage and avalanche capa-
bility (UIS). These LGC devices shorten delay times, and
reduce the power requirement of the gate drive. These de-
vices are ideally suited for high voltage switched mode pow-
er supply applications where low conduction loss, fast
switching times and UIS capability are essential. SMPS II
LGC devices have been specially designed for:
• 100kHz Operation at 390V,24A
• 200kHZ Operation at 390V, 18A
• 600V Switching SOA Capability
• Typical Fall Time. . . . . . . . . . . 85ns at TJ = 125oC
• Low Gate Charge . . . . . . . . . 35nC at VGE = 15V
• Low Plateau Voltage . . . . . . . . . . . . .6.5V Typical
• UIS Rated . . . . . . . . . . . . . . . . . . . . . . . . . 260mJ
• Low Conduction Loss
•
•
•
•
•
•
Power Factor Correction (PFC) circuits
Full bridge topologies
Half bridge topologies
Push-Pull circuits
Uninterruptible power supplies
Zero voltage and zero current switching circuits
Formerly Developmental Type TA49438.
Symbol
Package
JEDEC STYLE TO-247
JEDEC STYLE TO-220AB
JEDEC STYLE TO-263AB
C
E
C
E
C
G
G
C
G
G
E
E
Device Maximum Ratings T = 25°C unless otherwise noted
C
Symbol
BV
Parameter
Collector to Emitter Breakdown Voltage
Collector Current Continuous, T = 25°C
Ratings
Units
600
75
V
A
A
A
V
V
CES
I
C25
C
I
Collector Current Continuous, T = 110°C
35
C110
C
I
Collector Current Pulsed (Note 1)
Gate to Emitter Voltage Continuous
Gate to Emitter Voltage Pulsed
180
±20
±30
CM
V
GES
GEM
V
SSOA
Switching Safe Operating Area at T = 150°C, Figure 2
200A at 600V
260
J
E
Pulsed Avalanche Energy, I = 20A, L = 1.3mH, V = 50V
mJ
W
AS
CE
DD
P
Power Dissipation Total T = 25°C
290
D
C
Power Dissipation Derating T > 25°C
2.33
W/°C
°C
C
T
Operating Junction Temperature Range
Storage Junction Temperature Range
-55 to 150
-55 to 150
J
T
°C
STG
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. Pulse width limited by maximum junction temperature.
©2001 Fairchild Semiconductor Corporation
FGH40N6S2, FGP40N6S2, FGB40N6S2 Rev. A
Package Marking and Ordering Information
Device Marking
40N6S2
Device
Package
TO-247
Tape Width
Quantity
FGH40N6S2
FGP40N6S2
FGB40N6S2
-
-
40N6S2
TO-220AB
TO-263AB
40N6S2
Electrical Characteristics T = 25°C unless otherwise noted
J
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off State Characteristics
BV
BV
Collector to Emitter Breakdown Voltage
Emitter to Collector Breakdown Voltage
Collector to Emitter Leakage Current
I
I
= 250mA, V = 0
600
10
-
28
-
-
-
V
V
CES
ECS
C
C
GE
= 10mA, V = 0
GE
I
V
= 600V
T = 25°C
-
-
-
250
2.0
±250
mA
mA
nA
CES
CE
J
T = 125°C
-
J
I
Gate to Emitter Leakage Current
V
= ± 20V
-
GES
GE
On State Characteristics
V
Collector to Emitter Saturation Voltage
I
V
= 20A,
T = 25°C
-
-
1.9
1.7
2.7
2.0
V
V
CE(SAT)
C
J
= 15V
GE
T = 125°C
J
Dynamic Characteristics
Q
Gate Charge
I
V
= 20A,
V
V
= 15V
= 20V
-
-
35
45
42
55
nC
nC
V
G(ON)
C
GE
= 300V
CE
GE
V
Gate to Emitter Threshold Voltage
Gate to Emitter Plateau Voltage
I
I
= 250mA, V = 600V
3.5
-
4.3
6.5
5.0
8.0
GE(TH)
C
C
CE
V
= 20A, V = 300V
V
GEP
CE
Switching Characteristics
SSOA
Switching SOA
T = 150°C, R = 3W, V =
GE
200
-
-
A
J
G
15V, L = 100mH, V = 600V
CE
t
Current Turn-On Delay Time
Current Rise Time
IGBT and Diode at T = 25°C,
-
-
-
-
-
-
-
-
-
-
-
-
-
-
8
-
ns
ns
ns
ns
mJ
mJ
mJ
ns
ns
ns
ns
mJ
mJ
mJ
d(ON)I
J
I
= 20A,
t
CE
10
-
rI
d(OFF)I
V
V
R
= 390V,
= 15V,
= 3W
CE
GE
t
Current Turn-Off Delay Time
Current Fall Time
35
-
t
55
-
-
fI
G
E
E
E
Turn-On Energy (Note 2)
Turn-On Energy (Note 2)
Turn-Off Energy (Note 3)
Current Turn-On Delay Time
Current Rise Time
115
200
195
14
ON1
ON2
OFF
L = 200mH
Test Circuit - Figure 20
-
260
-
t
IGBT and Diode at T = 125°C
J
d(ON)I
I
= 20A,
t
CE
18
-
rI
d(OFF)I
V
V
R
= 390V,
= 15V,
= 3W
CE
GE
t
Current Turn-Off Delay Time
Current Fall Time
68
85
105
-
t
85
fI
G
E
E
E
Turn-On Energy (Note 2)
Turn-On Energy (Note 2)
Turn-Off Energy (Note 3)
115
380
375
ON1
ON2
OFF
L = 200mH
Test Circuit - Figure 20
450
600
Thermal Characteristics
R
Thermal Resistance Junction-Case
-
-
0.43
°C/W
qJC
NOTE:
2. Values for two Turn-On loss conditions are shown for the convenience of the circuit designer. E
is the turn-on loss
ON1
of the IGBT only. E
is the turn-on loss when a typical diode is used in the test circuit and the diode is at the same T
J
ON2
as the IGBT. The diode type is specified in figure 20.
3. Turn-Off Energy Loss (E
) is defined as the integral of the instantaneous power loss starting at the trailing edge of
OFF
the input pulse and ending at the point where the collector current equals zero (I = 0A). All devices were tested per
CE
JEDEC Standard No. 24-1 Method for Measurement of Power Device Turn-Off Switching Loss. This test method produc-
es the true total Turn-Off Energy Loss.
©2001 Fairchild Semiconductor Corporation
FGH40N6S2, FGP40N6S2, FGB40N6S2 Rev. A
Typical Performance Curves
250
200
90
80
70
60
50
40
30
20
10
0
o
T
= 150 C, R = 3
W
, V = 15V, L = 100mH
J
G
GE
150
100
50
0
25
50
75
100
125
150
0
100
200
300
400
500
600
700
TC, CASE TEMPERATURE (oC)
VCE, COLLECTOR TO EMITTER VOLTAGE (V)
Figure 1. DC Collector Current vs Case
Temperature
Figure 2. Minimum Switching Safe Operating Area
1000
9.5
9.0
8.5
8.0
7.5
7.0
900
800
700
600
500
400
300
200
V
= 390V, R = 3W
, T =125oC
J
CE
G
TC
VGE
15V
75oC
ISC
VGE = 10V
100
10
1
fMAX1 = 0.05 / (td(OFF)I + td(ON)I
)
fMAX2 = (PD - PC) / (EON2 + EOFF
)
tSC
PC = CONDUCTION DISSIPATION
(DUTY FACTOR = 50%)
R
ØJC = 0.49oC/W, SEE NOTES
TJ = 125oC, RG = 3
W, L = 200mH, VCE = 390V
10
11
12
13
14
15
1
10
30
60
ICE, COLLECTOR TO EMITTER CURRENT (A)
VGE, GATE TO EMITTER VOLTAGE (V)
Figure 3. Operating Frequency vs Collector to
Emitter Current
Figure 4. Short Circuit Withstand Time
40
40
DUTY CYCLE < 0.5%, VGE = 15V
DUTY CYCLE < 0.5%, VGE = 15V
PULSE DURATION = 20
PULSE DURATION = 20ms
ms
35
30
25
20
15
10
5
35
30
25
20
15
10
5
TJ = 125oC
TJ = 125oC
TJ = 25oC
TJ = 150oC
TJ = 150oC
TJ = 25oC
0
0
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
VCE, COLLECTOR TO EMITTER VOLTAGE (V)
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
CE, COLLECTOR TO EMITTER VOLTAGE (V)
V
Figure 5. Collector to Emitter On-State Voltage
Figure 6. Collector to Emitter On-State Voltage
©2001 Fairchild Semiconductor Corporation
FGH40N6S2, FGP40N6S2, FGB40N6S2 Rev. A
Typical Performance Curves (Continued)
1200
1000
800
600
400
200
0
1400
RG = 3W, L = 200mH, VCE = 390V
RG = 3W, L = 200mH, VCE = 390V
1200
1000
800
600
400
200
0
TJ = 125oC, VGE = 10V, VGE = 15V
TJ = 125oC, VGE = 10V, VGE = 15V
TJ = 25oC, VGE = 10V, VGE = 15V
TJ = 25oC, VGE = 10V, VGE = 15V
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
ICE, COLLECTOR TO EMITTER CURRENT (A)
ICE, COLLECTOR TO EMITTER CURRENT (A)
Figure 7. Turn-On Energy Loss vs Collector to
Emitter Current
Figure 8. Turn-Off Energy Loss vs Collector to
Emitter Current
60
20
RG = 3W, L = 200mH, VCE = 390V
RG = 3W, L = 200mH, VCE = 390V
50
16
12
8
TJ = 25oC, TJ = 125oC, VGE = 10V
40
30
20
10
0
TJ = 125oC, VGE = 15V, VGE = 10V
TJ = 25oC, TJ = 125oC, VGE = 15V
4
TJ = 25oC, VGE = 10V, VGE =15V
0
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
ICE, COLLECTOR TO EMITTER CURRENT (A)
I
CE, COLLECTOR TO EMITTER CURRENT (A)
Figure 9. Turn-On Delay Time vs Collector to
Emitter Current
Figure 10. Turn-On Rise Time vs Collector to
Emitter Current
80
100
RG = 3W, L = 200mH, VCE = 390V
RG = 3W, L = 200mH,
VCE = 390V
70
60
50
40
30
20
90
80
70
60
50
40
TJ = 125oC, VGE = 10V OR 15V
VGE = 10V, VGE = 15V, TJ = 125oC
TJ = 25oC, VGE = 10V OR 15V
VGE = 10V, VGE = 15V, TJ = 25oC
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
ICE, COLLECTOR TO EMITTER CURRENT (A)
I
CE, COLLECTOR TO EMITTER CURRENT (A)
Figure 11. Turn-Off Delay Time vs Collector to
Emitter Current
Figure 12. Fall Time vs Collector to Emitter
Current
©2001 Fairchild Semiconductor Corporation
FGH40N6S2, FGP40N6S2, FGB40N6S2 Rev. A
Typical Performance Curves (Continued)
16
14
12
10
8
200
DUTY CYCLE < 0.5%, VCE = 10V
PULSE DURATION = 250ms
175
150
125
100
75
V
= 600V
CE
V
= 400V
CE
6
TJ = 25oC
VCE = 200V
50
4
TJ = -55oC
TJ = 125oC
25
2
0
0
3
4
5
6
7
8
9
10
11
12
0
5
10
15
Q , GATE CHARGE (nC)
G
20
25
30
35
V
GE, GATE TO EMITTER VOLTAGE (V)
Figure 13. Transfer Characteristic
Figure 14. Gate Charge
100
10
1
2.4
2.0
1.6
1.2
0.8
0.4
0
o
T
= 125 C, L = 200
m
H, V = 390V, V = 15V
RG = 3
W, L = 200mH, VCE = 390V, VGE = 15V
J
CE
GE
ETOTAL = EON2 + EOFF
E
= E
+ E
TOTAL
ON2 OFF
ICE = 40A
I
= 40A
= 20A
CE
I
CE
ICE = 20A
ICE = 10A
I
= 10A
CE
0.1
1
2
5
10
20
50 100 200
500 1000
25
50
75
100
125
150
T
C, CASE TEMPERATURE (oC)
R
, GATE RESISTANCE (W)
G
Figure 15. Total Switching Loss vs Case
Temperature
Figure 16. Total Switching Loss vs Gate
Resistance
4.0
3.0
FREQUENCY = 1MHz
DUTY CYCLE < 0.5%
o
PULSE DURATION = 250
m
s, T = 25 C
J
3.6
3.2
2.8
2.4
2.0
1.6
2.5
2.0
C
IES
1.5
1.0
0.5
0.0
I
= 30A
CE
I
= 40A
CE
I
= 20A
CE
C
OES
C
I
= 10A
8
RES
CE
6
7
9
10
11
12
13
14
15
16
0
20
40
60
80
100
V
, COLLECTOR TO EMITTER VOLTAGE (V)
V
, GATE TO EMITTER VOLTAGE (V)
CE
GE
Figure 17. Capacitance vs Collector to Emitter
Voltage
Figure 18. Collector to Emitter On-State Voltage vs
Gate to Emitter Voltage
©2001 Fairchild Semiconductor Corporation
FGH40N6S2, FGP40N6S2, FGB40N6S2 Rev. A
Typical Performance Curves (Continued)
0
10
0.50
0.20
0.10
t
1
P
D
-1
10
t
2
0.05
DUTY FACTOR, D = t / t
1
2
0.02
0.01
PEAK T = (P X Zq X Rq ) + T
J
D
JC
JC
C
SINGLE PULSE
-2
10
-5
-4
-3
-2
-1
0
1
10
10
10
10
10
10
10
t , RECTANGULAR PULSE DURATION (s)
1
Figure 19. IGBT Normalized Transient Thermal Impedance, Junction to Case
Test Circuit and Waveforms
FGH50N6S2D
DIODE TA49392
90%
OFF
10%
V
GE
E
ON2
E
L = 200mH
V
CE
R
= 3W
G
90%
10%
+
I
CE
t
t
FGH50N6S2
d(OFF)I
V
= 390V
rI
DD
t
fI
-
t
d(ON)I
Figure 20. Inductive Switching Test Circuit
Figure 21. Switching Test Waveforms
©2001 Fairchild Semiconductor Corporation
FGH40N6S2, FGP40N6S2, FGB40N6S2 Rev. A
Handling Precautions for IGBTs
Operating Frequency Information
Operating frequency information for a typical device
(Figure 3) is presented as a guide for estimating
device performance for a specific application. Other
typical frequency vs collector current (ICE) plots are
possible using the information shown for a typical
unit in Figures 5, 6, 7, 8, 9 and 11. The operating
frequency plot (Figure 3) of a typical device shows
fMAX1 or fMAX2; whichever is smaller at each point.
The information is based on measurements of a
typical device and is bounded by the maximum rated
junction temperature.
Insulated Gate Bipolar Transistors are susceptible to
gate-insulation damage by the electrostatic
discharge of energy through the devices. When
handling these devices, care should be exercised to
assure that the static charge built in the handler’s
body capacitance is not discharged through the
device. With proper handling and application
procedures, however, IGBTs are currently being
extensively used in production by numerous
equipment manufacturers in military, industrial and
consumer applications, with virtually no damage
problems due to electrostatic discharge. IGBTs can
be handled safely if the following basic precautions
are taken:
fMAX1 is defined by fMAX1 = 0.05/(td(OFF)I+ td(ON)I).
Deadtime (the denominator) has been arbitrarily held
to 10% of the on-state time for a 50% duty factor.
Other definitions are possible. td(OFF)I and td(ON)I are
defined in Figure 21. Device turn-off delay can
establish an additional frequency limiting condition
for an application other than TJM. td(OFF)I is important
when controlling output ripple under a lightly loaded
condition.
1. Prior to assembly into a circuit, all leads should be
kept shorted together either by the use of metal
shorting springs or by the insertion into conduc-
tive material such as “ECCOSORBD™ LD26” or
equivalent.
2. When devices are removed by hand from their
carriers, the hand being used should be
grounded by any suitable means - for example,
with a metallic wristband.
fMAX2 is defined by fMAX2 = (PD - PC)/(EOFF + EON2).
The allowable dissipation (PD) is defined by
PD = (TJM - TC)/RqJC. The sum of device switching
and conduction losses must not exceed PD. A 50%
duty factor was used (Figure 3) and the conduction
losses (PC) are approximated by PC = (VCE x ICE)/2.
3. Tips of soldering irons should be grounded.
4. Devices should never be inserted into or removed
from circuits with power on.
EON2 and EOFF are defined in the switching
waveforms shown in Figure 21. EON2 is the integral
of the instantaneous power loss (ICE x VCE) during
turn-on and EOFF is the integral of the instantaneous
power loss (ICE x VCE) during turn-off. All tail losses
are included in the calculation for EOFF; i.e., the
collector current equals zero (ICE = 0)
5. Gate Voltage Rating - Never exceed the gate-
voltage rating of VGEM. Exceeding the rated VGE
can result in permanent damage to the oxide
layer in the gate region.
6. Gate Termination - The gates of these devices
are essentially capacitors. Circuits that leave the
gate open-circuited or floating should be avoided.
These conditions can result in turn-on of the
device due to voltage buildup on the input
capacitor due to leakage currents or pickup.
7. Gate Protection - These devices do not have an
internal monolithic Zener diode from gate to
emitter. If gate protection is required an external
Zener is recommended.
ECCOSORBDä is a Trademark of Emerson and Cumming, Inc.
©2001 Fairchild Semiconductor Corporation
FGH40N6S2, FGP40N6S2, FGB40N6S2 Rev. A
TO-247
3 LEAD JEDEC STYLE TO-247 PLASTIC PACKAGE
A
TERM. 4
ØP
INCHES
MILLIMETERS
E
ØS
SYMBOL
MIN
MAX
MIN
MAX
4.82
NOTES
A
b
0.180
0.046
0.060
0.095
0.020
0.800
0.605
0.190
0.051
0.070
0.105
0.026
0.820
0.625
4.58
1.17
-
Q
1.29
2, 3
ØR
b
b
1.53
1.77
1, 2
1
2
D
2.42
2.66
1, 2
c
0.51
0.66
1, 2, 3
D
E
e
20.32
15.37
20.82
15.87
-
-
L1
b1
b2
0.219 TYP
0.438 BSC
0.090
5.56 TYP
11.12 BSC
2.29
4
4
5
-
L
c
e
1
b
J
0.105
0.640
0.155
0.144
0.220
0.205
0.270
2.66
16.25
3.93
3.65
5.58
5.20
6.85
1
1
2
3
3
2
1
L
0.620
0.145
0.138
0.210
0.195
0.260
15.75
3.69
3.51
5.34
4.96
6.61
J1
e
BACK VIEW
L
1
-
1
e1
ØP
Q
-
ØR
-
ØS
-
NOTES:
1. Lead dimension and finish uncontrolled in L .
1
2. Lead dimension (without solder).
3. Add typically 0.002 inches (0.05mm) for solder coating.
4. Position of lead to be measured 0.250 inches (6.35mm) from bottom of dimen-
sion D.
5. Position of lead to be measured 0.100 inches (2.54mm) from bottom of dimen-
sion D.
6. Controlling dimension: Inch.
7. Revision 1 dated 1-93.
©2001 Fairchild Semiconductor Corporation
FGH40N6S2, FGP40N6S2, FGB40N6S2 Rev. A
TO-263AB
SURFACE MOUNT JEDEC TO-263AB PLASTIC PACKAGE
INCHES
MIN
MILLIMETERS
NOTE
S
-
4, 5
4, 5
4, 5
2
4, 5
-
-
7
7
-
SYMBOL
MAX
0.180
0.052
0.034
0.055
-
MIN
4.32
1.22
0.77
1.15
7.88
0.46
MAX
4.57
1.32
0.86
1.39
-
0.55
10.79
10.28
E
A
A
0.170
0.048
0.030
0.045
0.310
0.018
0.405
0.395
A1
A
1
H1
b
TERM. 4
b
b
1
D
L
2
c
0.022
0.425 10.29
0.405 10.04
D
E
e
L2
L1
0.100 TYP
0.200 BSC
2.54 TYP
5.08 BSC
1
3
e
1
H
0.045
0.095
0.175
0.090
0.050
0.315
0.055
1.15
1.39
2.66
4.95
2.79
1.77
-
1
b
b1
c
e
J
0.105
0.195
0.110
0.070
-
2.42
4.45
2.29
1.27
8.01
-
-
1
J1
e1
L
0.450
(11.43)
L
L
L
4, 6
3
2
TERM. 4
1
2
3
L3
NOTES:
0.350
(8.89)
1. These dimensions are within allowable dimensions of
Rev. C of JEDEC TO-263AB outline dated 2-92.
b
2
0.700
(17.78)
2. L and b dimensions established a minimum mounting
3
2
surface for terminal 4.
3. Solder finish uncontrolled in this area.
4. Dimension (without solder).
0.150
(3.81)
3
1
5. Add typically 0.002 inches (0.05mm) for solder plating.
0.080 TYP (2.03)
0.062 TYP (1.58)
6. L is the terminal length for soldering.
1
7. Position of lead to be measured 0.120 inches (3.05mm)
from bottom of dimension D.
8. Controlling dimension: Inch.
MINIMUM PAD SIZE RECOMMENDED FOR
SURFACE-MOUNTED APPLICATIONS
9. Revision 10 dated 5-99.
4.0mm
TO-263AB
24mm TAPE REEL
1.5mm
DIA. HOLE
1.75mm
USER DIRECTION OF FEED
2.0mm
C
L
24mm
16mm
COVER TAPE
40mm MIN.
ACCESS HOLE
30.4mm
13mm
330mm
100mm
GENERAL INFORMATION
1. 800 PIECES PER REEL.
2. ORDER IN MULTIPLES OF FULL REELS ONLY.
24.4mm
3. MEETS EIA-481 REVISION "A" SPECIFICATIONS.
©2001 Fairchild Semiconductor Corporation
FGH40N6S2, FGP40N6S2, FGB40N6S2 Rev. A
TO-220AB
3 LEAD JEDEC TO-220AB PLASTIC PACKAGE
A
INCHES
MILLIMETERS
MIN
E
ØP
SYMBOL
MIN
MAX
MAX
4.57
1.32
0.86
1.39
0.48
15.49
4.06
10.41
0.76
NOTES
A1
A
0.170
0.048
0.030
0.045
0.014
0.590
-
0.180
0.052
0.034
0.055
0.019
0.610
0.160
0.410
0.030
4.32
1.22
0.77
1.15
0.36
14.99
-
-
Q
H1
A
-
1
b
3, 4
TERM. 4
D
b
2, 3
1
E1
45o
c
2, 3, 4
D1
D
-
-
L1
D
1
b1
E
0.395
-
10.04
-
-
L
b
E
-
c
1
e
0.100 TYP
0.200 BSC
0.235
2.54 TYP
5.08 BSC
6.47
5
5
-
60o
e
1
2
e
3
1
J1
H
0.255
0.110
0.550
0.150
0.153
0.112
5.97
2.54
13.47
3.31
3.79
2.60
1
1
e1
J
0.100
0.530
0.130
0.149
0.102
2.79
13.97
3.81
6
-
L
L
2
-
1
ØP
Q
3.88
2.84
-
NOTES:
1. These dimensions are within allowable dimensions of Rev. J of JEDEC TO-
220AB outline dated 3-24-87.
2. Lead dimension and finish uncontrolled in L .
1
3. Lead dimension (without solder).
4. Add typically 0.002 inches (0.05mm) for solder coating.
5. Position of lead to be measured 0.250 inches (6.35mm) from bottom of dimen-
sion D.
6. Position of lead to be measured 0.100 inches (2.54mm) from bottom of dimen-
sion D.
7. Controlling dimension: Inch.
8. Revision 2 dated 7-97.
©2001 Fairchild Semiconductor Corporation
FGH40N6S2, FGP40N6S2, FGB40N6S2 Rev. A
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
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Bottomless™
CoolFET™
CROSSVOLT™
DenseTrench™
DOME™
EcoSPARK™
E2CMOS™
Ensigna™
FAST®
FASTr™
FRFET™
GlobalOptoisolator™
GTO™
OPTOPLANAR™
PACMAN™
POP™
STAR*POWER™
Stealth™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TinyLogic™
TruTranslation™
UHC™
Power247™
PowerTrench®
QFET™
HiSeC™
ISOPLANAR™
LittleFET™
MicroFET™
MICROWIRE™
OPTOLOGIC™
QS™
QTOptpelectronics™
Quiet Series™
SILENTSWITCHER®
SMART START™
FACT™
FACT Quiet Series™
UltraFET®
VCX™
STAR*POWER is used under license
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR
CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Obsolete
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. H3
©2001 Fairchild Semiconductor Corporation
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