FI1032MTC [FAIRCHILD]

Line Receiver, 4 Func, 4 Rcvr, PDSO16, 4.40 MM, MO-153, TSSOP-16;


型号：	FI1032MTC
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	Line Receiver, 4 Func, 4 Rcvr, PDSO16, 4.40 MM, MO-153, TSSOP-16 光电二极管接口集成电路
文件：	总6页 (文件大小：232K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Preliminary

November 2000

Revised December 2000

FI1032

3.3V LVDS Quad High Speed Differential Receiver

(Preliminary)

General Description

Features

This quad receiver is designed for high speed interconnect

utilizing Low Voltage Differential Signaling (LVDS) technol-

ogy. The receiver translates LVDS levels, with a typical dif-

ferential input threshold of 100mV, to LVTTL signal levels.

LVDS provides low EMI at ultra low power dissipation even

at high frequencies. This device is ideal for high speed

transfer of clock and data.

■ Greater than 400Mbs data rate

■ 3.3V power supply operation

■ 0.4ns maximum differential pulse skew

■ 2.5ns maximum propagation delay

■ Low power dissipation

■ Power OFF protection

The FI1032 can be paired with its companion driver, the

FI1031, or any other Fairchild LVDS driver.

■ Fail safe protection for open-circuit, shorted and termi-

nated conditions

■ Meets or exceeds the TIA/EIA-644 LVDS standard

■ Pin compatible with equivalent RS-422 and LVPECL

devices

■ 16-Lead SOIC and TSSOP packages save space

Ordering Code:

Order Number Package Number

Package Description

FI1032M

M16A

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

FI1032MTC

MTC16

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Function Table

Connection Diagram

Inputs

Outputs

Rin+

Rout−

Rout

Fail Safe Condition

H = HIGH Logic Level

Z = High Impedance

L = LOW Logic Level

Fail Safe = Open, Shorted, Terminated

X = Don’t Care

Pin Descriptions

Pin Name

Description

Rout1, Rout2, Rout3, Rout4 LVTTL Data Outputs

Rin1+, Rin2+, Rin3+, Rin4+ Non-Inverting LVDS Inputs

Rin1−, Rin2−, Rin3−, Rin4− Inverting LVDS Inputs

Driver Enable Pin

V_CC

GND

Inverting Driver Enable Pin

Power Supply

Ground

DS500508

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Print form created on December 11, 2000 10:59

Preliminary

Absolute Maximum Ratings(Note 1)

Recommended Operating

Conditions

Supply Voltage (V_CC

)

−0.5V to +4.6V

−0.5V to +4.7V

−0.5V to 6V

16 mA

DC Input Voltage (V_IN

)

Supply Voltage (V_CC

)

3.0V to 3.6V

DC Input Voltage (V_OUT

)

Magnitude of Differential Voltage

(|V_ID|)

DC Output Current (I_O)

100mV to V_CC

0.05V to 2.35V

0 to V_CC

Storage Temperature Range (T_STG

Max Junction Temperature (T_J)

Lead Temperature (T_L)

)

−65°C to +150°C

150°C

Common-Mode Input Voltage (V_IC

)

Input Voltage (V_IN

)

Operating Temperature (T_A)

−40°C to +85°C

(Soldering, 10 seconds)

260°C

≥ 8000V

≥ 600V

Note 1: The “Absolute Maximum Ratings”: are those values beyond which

damage to the device may occur. The databook specifications should be

met, without exception, to ensure that the system design is reliable over its

power supply, temperature and output/input loading variables. Fairchild

does not recommend operation of circuits outside databook specification.

ESD (Human Body Model)

ESD (Machine Model)

DC Electrical Characteristics

Over supply voltage and operating temperature ranges, unless otherwise specified

Min

Typ

Max

Symbol

V_TH

Parameter

Test Conditions

Units

(Note 2)

Differential Input Threshold HIGH

Differential Input Threshold LOW

Input Current

See Figure 1 and Table 1

100

µA

V_TL

−100

I_IN

_IN= 0V or V_CC

±20

I_I(OFF)

V_OH

Power-OFF Input Current

Output HIGH Voltage

_CC= 0V, V_IN= 0V or 3.6V

µA

_OH= −100 µA

_OH= −8 mA

_OH= 100 µA

_OL= 8 mA

EN = 0.8 and EN* = 2V, V_OUT= 6V or 0V

_IK= −18 mA

_CC−0.2

2.4

V_OL

Output LOW Voltage

0.2

0.5

±20

I_OZ

Disabled Output Leakage Current

Input Clamp Voltage

µA

V_IK

I_CCZ

I_CC

−1.5

Disabled Power Supply Current

Power Supply Current

Receiver Disabled

Receiver Enabled, (RI+ = 1V and RI− = 1.4V)

or (RI+= 1.4V and RI− = 1V)

C_IN

Input Capacitance

Output Capacitance

C_OUT

Note 2: All typical values are at T_A= 25°C and with V_CC= 3.3V.

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Preliminary

AC Electrical Characteristics

Over supply voltage and operating temperature ranges, unless otherwise specified

Min

Typ

Max

Symbol

Parameter

Test Conditions

Units

(Note 3)

t_PLH

t_PHL

t_TLH

Propagation Delay LOW-to-HIGH

Propagation Delay HIGH-to-LOW

Output Rise Time (20% to 80%)

Output Fall Time (80% to 20%)

1.0

2.5

|V_ID| = 400mV, C_L= 10 pF,

0.5

t_THL

t_SK(P)

t_SK(LH)

t_SK(HL)

t_SK(PP)

t_ZH

See Figure 1 and Figure 2

Pulse Skew |t_PLH- t_PHL

0.4

0.3

Channel-to-Channel Skew

(Note 4)

Part-to-Part Skew (Note 5)

1.0

5.0

LVTTL Output Enable Time from Z to HIGH

LVTTL Output Enable Time from Z to LOW

LVTTL Output Disable Time from HIGH to Z

LVTTL Output Disable Time from LOW to Z

t_ZL

R_L= 100Ω, C_L= 10 pF,

t_HZ

See Figure 3

t_LZ

Note 3: All typical values are at T_A= 25°C and with V_CC= 3.3V.

Note 4: t_SK(LH), t_SK(HL)is the skew between specified outputs of a single device when the outputs have identical loads and are switching in the same direc-

tion.

Note 5: t_SK(PP)is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction

(either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits.

Note A: All input pulses have frequency = 10MHz, t_Ror t_F= 1ns

Note B: C_Lincludes all probe and jig capacitances

FIGURE 1. Differential Receiver Voltage Definitions and Propagation Delay and Transition Time Test Circuit

TABLE 1. Receiver Minimum and Maximum Input Threshold Test Voltages

Applied Voltages (V)

Resulting Differential Input

Resulting Common Mode Input

Voltage (mA)

V_ID

Voltage (V)

V_IC

V_IA

V_IB

1.25

1.15

2.4

2.3

0.1

1.15

1.25

2.3

2.4

100

−100

100

1.2

2.35

0.05

1.2

−100

100

0.1

0.9

1.5

1.8

2.4

−100

600

1.5

0.9

2.4

1.8

0.6

−600

600

1.2

2.1

−600

600

2.1

0.3

0.6

−600

0.3

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Preliminary

FIGURE 2. LVDS Input to LVTTL Output AC Waveforms

Test Circuit for LVTTL Outputs

Voltage Waveforms Enable and Disable Times

FIGURE 3. LVTTL Outputs Test Circuit and AC Waveforms

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Preliminary

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

Package Number M16A

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Preliminary

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Package Number MTC16

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical component in any component of a life support

device or system whose failure to perform can be rea-

sonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

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