FIN24A_技术文档

Preliminary

April 2005

Revised May 2005

FIN24A

PSerDes

Low Voltage 24-Bit Bi-Directional Serializer/Deserializer

with Multiple Frequency Ranges (Preliminary)

General Description

Features

The FIN24A allows for a pair of SerDes to interleave data

from two different data sources going opposite directions or

standard bi-directional interface operation. The bi-direc-

tional data flow is controlled through use of a direction

(DIRI) control pin. The devices can be configured to oper-

ate in a unidirectional mode only by hardwiring the DIRI

pin. An internal PLL generates the required bit clock fre-

quency for transfer across the serial link. The FIN24A sup-

ports multiple input frequency ranges which are selected

by the S1 and S2 control pins. Options exist for dual or sin-

gle PLL operation dependent upon system operational

parameters. The device has been designed for low power

operation and utilizes Fairchild Low Power LVDS interface.

The device also supports an ultra low power Power-Down

mode for conserving power in battery operated applica-

tions.

■ Low power consumption

■ Low power standards based LVDS differential interface

■ LVCMOS parallel I/O interface

• 2 mA source/sink current

• Over-voltage tolerant control signals

■ I/O Power Supply range between 1.65V and 3.6V

■ Analog Power Supply range of 2.775V 5%

■ Multi-Mode operation allows for a single device to

operate as Serializer or Deserializer

■ Internal PLL with no external components

■ Standby Power-Down mode support

■ Small footprint 40-terminal MLP packaging

■ Built in differential termination

■ Supports external CKREF frequencies between 2MHz

and 30MHz

■ Serialized data rate up to 780Mb/s

Ordering Code:

Order Number Package Number

Package Description

FIN24AGFX

(Preliminary)

BGA042A

Pb-Free 42-Ball Ultra Small Scale Ball Grid Array (USS-BGA), JEDEC MO-195,

3.5mm Wide

FIN24AMLX

MLP040A

Pb-Free 40-Terminal Molded Leadless Package (MLP), Quad, JEDEC MO-220, 6mm

Square

Pb-Free package per JEDEC J-STD-020B.

BGX and MLP packages available in Tape and Reel only.

SerDes is a trademark of Fairchild Semiconductor Corporation.

DS500888

www.fairchildsemi.com

Preliminary

Functional Block Diagram

Connection Diagram

Terminal Assignments for MLP

(Top View)

www.fairchildsemi.com

2

Preliminary

Terminal Description

Number

of

Terminal Name I/O Type

Description of Signals

Terminals

DP[1:20]

DP[21:22]

DP[23:24]

CKREF

I/O

20

2

LVCMOS Parallel I/O. Direction controlled by DIRI pin

LVCMOS Parallel Unidirectional Inputs

I

O

2

LVCMOS Unidirectional Parallel Outputs

LVCMOS Clock Input and PLL Reference

LVCMOS Strobe Signal for Latching Data into the Serializer

LVCMOS Word Clock Output

IN

1

STROBE

CKP

IN

1

OUT

DIFF-I/O

1

DSO / DSI

2

LpLVDS Differential Serial I/O Data Signals (Note 1)

DSO: Refers to output signal pair

DSI: Refers to input signal pair

DSO(I) : Positive signal of DSO(I) pair

DSO(I) : Negative signal of DSO(I) pair

CKSI , SKSI

DIFF-IN

2

LpLVDS Differential Deserializer Input Bit Clock

CKSI: Refers to signal pair

CKSI : Positive signal of CKSI pair

CKSI : Negative signal of CKSI pair

CKSO , SKSO DIFF-OUT

LpLVDS Differential Serializer Output Bit Clock

CKSO: Refers to signal pair

CKSO : Positive signal of CKSO pair

CKSO : Negative signal of CKSO pair

S1

S2

IN

1

LVCMOS Mode Selection terminals used to select

Frequency Range for the RefClock, CKREF

DIRI

LVCMOS Control Input

Used to control direction of Data Flow:

DIRI “1” Serializer, DIRI “0” Deserializer

DIRO

OUT

1

LVCMOS Control Output

Inversion of DIRI

V_DDP

V_DDS

V_DDA

GND

Supply

1

0

Power Supply for Parallel I/O and Translation Circuitry

Power Supply for Core and Serial I/O

Power Supply for Analog PLL Circuitry

Use Bottom Ground Plane for Ground Signals

Note 1: The DSO/DSI serial port pins have been arranged such that when one device is rotated 180 degrees with respect to the other device the serial con-

nections will properly align without the need for any traces or cable signals to cross. Other layout orientations may require that traces or cables cross.

bits of data are ever serialized or deserialized. Regardless

of the mode of operation the serializer is always sending 24

Control Logic Circuitry

The FIN24A has the ability to be used as a 24-bit Serializer

bits of data plus 2 boundary bits and the deserializer is

or a 24-bit Deserializer. Pins S1 and S2 must be set to

always receiving 24 bits of data and 2 word boundary bits.

accommodate the clock reference input frequency range of

Bits 23 and 24 of the serializer will always contain the value

the serializer. The table below shows the pin programming

of zero and will be discarded by the deserializer. DP[21:22]

of these options based on the S1 and S2 control pins. The

input to the serializer will be deserialized to DP[23:24]

DIRI pin controls whether the device is a serializer or a

respectively.

deserializer. When DIRI is asserted LOW, the device is

configured as a deserializer. When the DIRI pin is asserted

HIGH, the device will be configured as a serializer. Chang-

ing the state on the DIRI signal will reverse the direction of

the I/O signals and generate the opposite state signal on

DIRO. For unidirectional operation the DIRI pin should be

hardwired to the HIGH or LOW state and the DIRO pin

should be left floating. For bi-directional operation the DIRI

of the master device will be driven by the system and the

DIRO signal of the master will be used to drive the DIRI of

the slave device.

Turn-Around Functionality

The device passes and inverts the DIRI signal through the

device asynchronously to the DIRO signal. Care must be

taken by the system designer to insure that no contention

occurs between the deserializer outputs and the other

devices on this port. Optimally the peripheral device driving

the serializer should be put into a HIGH Impedance state

prior to the DIRI signal being asserted.

When a device with dedicated data outputs turns from a

deserializer to a serializer the dedicated outputs will remain

at the last logical value asserted. This value will only

change if the device is once again turned around into a

deserializer and the values are overwritten.

Serializer/Deserializer

with Dedicated I/O Variation

The serialization and deserialization circuitry is setup for 24

bits. Because of the dedicated inputs and outputs only 22

3

www.fairchildsemi.com

Preliminary

TABLE 1. Control Logic Circuitry

S2 S1 DIRI Description

Power-Down Mode

Serializer Operation: (Figure 1)

Modes 1, 2, or 3

DIRI equals 1

Mode

Number

CKREF equals STROBE

0

1

0

1

x

The PLL must receive a stable CKREF signal in order to

achieve lock prior to any valid data being sent. The CKREF

signal can be used as the data STROBE signal provided

that data can be ignored during the PLL lock phase.

1

24-Bit Serializer

2MHz to 5MHz CKREF

0

1

0

1

24-Bit Deserializer

Once the PLL is stable and locked the device can begin to

capture and serialize data. Data will be captured on the ris-

ing edge of the STROBE signal and then serialized. The

serialized data stream is synchronized and sent source

synchronously with a bit clock with an embedded word

boundary. When operating in this mode the internal deseri-

alizer circuitry is disabled including the serial clock, serial

data input buffers, the bi-directional parallel outputs and the

CKP word clock. The CKP word clock will be driven HIGH.

2

3

24-Bit Serializer

5MHz to 15MHz CKREF

1

0

1

0

1

24-Bit Deserializer

24-Bit Serializer

10MHz to 30MHz CKREF

1

0

24-Bit Deserializer

Serializer Operation: (Figure 2)

DIRI equals 1

CKREF does not equal STROBE

Power-Down Mode: (Mode 0)

Mode 0 is used for powering down and resetting the

device. When both of the mode signals are driven to a

LOW state the PLL and references will be disabled, differ-

ential input buffers will be shut off, differential output buffers

will be placed into a HIGH impedance state, LVCMOS out-

puts will be placed into a HIGH impedance state and

LVCMOS inputs will be driven to a valid level internally.

Additionally all internal circuitry will be reset. The loss of

CKREF state is also enabled to insure that the PLL will only

power-up if there is a valid CKREF signal.

If the same signal is not used for CKREF and STROBE,

then the CKREF signal must be run at a higher frequency

than the STROBE rate in order to serialize the data cor-

rectly. The actual serial transfer rate will remain at 26 times

the CKREF frequency. A data bit value of zero will be sent

when no valid data is present in the serial bit stream. The

operation of the serializer will otherwise remain the same.

The exact frequency that the reference clock needs to run

at will be dependent upon the stability of the CKREF and

STROBE signal. If the source of the CKREF signal imple-

ments spread spectrum technology then the maximum fre-

quency of this spread spectrum clock should be used in

calculating the ratio of STROBE frequency to the CKREF

frequency. Similarly if the STROBE signal has significant

cycle-to-cycle variation then the maximum cycle-to-cycle

time needs to be factored into the selection of the CKREF

frequency.

In a typical application mode signals of the device will typi-

cally not change states other than between the desired fre-

quency range and the power-down mode. This allows for

system level power-down functionality to be implemented

via a single wire for a SerDes pair. The S1 and S2 selection

signals that have their operating mode driven to a “logic 0”

should be hardwired to GND. The S1 and S2 signals that

have their operating mode driven to a “logic 1” should be

connected to a system level power-down signal.

Serializer Operation: (Figure 3)

DIRI equals 1

No CKREF

Serializer Operation Mode

A third method of serialization can be done by providing a

free running bit clock on the CKSI signal. This mode is

enabled by grounding the CKREF signal and driving the

DIRI signal HIGH.

The serializer configurations are described in the following

sections. The basic serialization circuitry works essentially

identical in these modes but the actual data and clock

streams will differ dependent on if CKREF is the same as

the STROBE signal or not. When it is stated that

CKREF STROBE this means that the CKREF and

STROBE signals have an identical frequency of operation

but may or may not be phase aligned. When it is stated that

CKREF does not equal STROBE then each signal is dis-

tinct and CKREF must be running at a frequency high

enough to avoid any loss of data condition. CKREF must

never be a lower frequency than STROBE.

At power-up the device is configured to accept a serializa-

tion clock from CKSI. If a CKREF is received then this

device will enable the CKREF serialization mode. The

device will remain in this mode even if CKREF is stopped.

To re-enable this mode the device must be powered down

and then powered back up with a “logic 0” on CKREF.

www.fairchildsemi.com

4

Preliminary

Serializer Operation Mode (Continued)

FIGURE 1. Serializer Timing Diagram (CKREF equals STROBE)

FIGURE 2. Serializer Timing Diagram (CKREF does not equal STROBE)

FIGURE 3. Serializer Timing Diagram Using Provided Bit Clock (No CKREF)

5

www.fairchildsemi.com

Preliminary

Deserializer Operation Mode

The operation of the deserializer is only dependent upon

the data received on the DSI data signal pair and the CKSI

clock signal pair. The following two sections describe the

operation of the deserializer under two distinct serializer

source conditions. References to the CKREF and STROBE

signals refer to the signals associated with the serializer

device used in generating the serial data and clock signals

that are inputs to the deserializer.

of CKP will be generated approximately 13 bit times later.

When no embedded word boundary occurs then no pulse

on CKP will be generated and CKP will remain HIGH.

Deserializer Operation:

DIRI equals 0

(Serializer Source: CKREF does not equal STROBE)

The logical operation of the deserializer remains the same

regardless of if the CKREF is equal in frequency to the

STOBE or at a higher frequency than the STROBE. The

actual serial data stream presented to the deserializer will

however be different because it will have non-valid data

bits sent between words. The duty cycle of CKP will vary

based on the ratio of the frequency of the CKREF signal to

the STROBE signal. The frequency of the CKP signal will

be equal to the STROBE frequency. The falling edge of

CKP will occur 6 bit times after the data transition. The

LOW time of the CKP signal will be equal to ½ (13 bit

times) of the CKREF period. The CKP HIGH time will be

equal to STROBE period – ½ of the CKREF period. Figure

5 is representative of a waveform that could be seen when

CKREF is not equal to STROBE. If CKREF was signifi-

cantly faster then additional non-valid data bits would occur

between data words.

When operating in this mode the internal serializer circuitry

is disabled including the parallel data input buffers. If there

is a CKREF signal provided then the CKSO serial clock will

continue to transmit bit clocks.

Deserializer Operation:

DIRI equals 0

(Serializer Source: CKREF equals STROBE)

When the DIRI signal is asserted LOW the device will be

configured as a deserializer. Data will be captured on the

serial port and deserialized through use of the bit clock

sent with the data. The word boundary is defined in the

actual clock and data signal. Parallel data will be generated

at the time the word boundary is detected. The falling edge

of CKP will occur approximately 6 bit times after the falling

edge of CKSI. The rising edge of CKP will go high approxi-

mately 13 bit times after CKP goes LOW. The rising edge

FIGURE 4. Deserializer Timing Diagram

(Serializer Source: CKREF equals STROBE)

FIGURE 5. Deserializer Timing Diagram

(Serializer Source: CKREF does not equal STROBE)

www.fairchildsemi.com

6

Preliminary

mission. Bit 25 and Bit 26 are defined with-respect-to Bit

24. Bit 25 will always be the inverse of Bit 24, and Bit 26

will always be the same as Bit 24. This insures that a

Embedded Word Clock Operation

The FIN24A sends and receives serial data source syn-

chronously with a bit clock. The bit clock has been modified

to create a word boundary at the end of each data word.

The word boundary has been implemented by skipping a

low clock pulse. This appears in the serial clock stream as

3 consecutive bit times where signal CKSO remains HIGH.

In order to implement this sort of scheme two extra data

bits are required. During the word boundary phase the data

will toggle either HIGH-then-LOW or LOW-then-HIGH

dependent upon the last bit of the actual data word. Table 2

provides some examples showing the actual data word and

the data word with the word boundary bits added. Note that

a 24-bit word will be extended to 26-bits during serial trans-

“0”

“1” and a “1”

“0” transition will always occur during

the embedded word phase where CKSO is HIGH.

The serializer generates the word boundary data bits and

the boundary clock condition and embeds them into the

serial data stream. The deserializer looks for the end of the

word boundary condition to capture and transfer the data to

the parallel port. The deserializer only uses the embedded

word boundary information to find and capture the data.

These boundary bits are then stripped prior to the word

being sent out of the parallel port.

TABLE 2. Word Boundary Data Bits

24-Bit Data Words

Binary

24-Bit Data Word with Word Boundary

Hex

Binary

3FFFFFh 0011 1111 1111 1111 1111 1111b

1FFFFFFh 01 1111 1111 1111 1111 1111 1111b

1155555h 01 0101 0101 0101 0101 0101 0101b

1xxxxxxh 01 0xxx xxxx xxxx xxxx xxxx xxxxb

155555h

xxxxxxh

0101 0101 0101 0101 01010 0101b

0xxx xxxx xxxx xxxx xxxx xxxxb

LVCMOS Data I/O

Differential I/O Circuitry

The LVCMOS input buffers have a nominal threshold value

The differential I/O circuitry is a low power variant of LVDS.

The differential outputs operate in the same fashion as

LVDS by sourcing and sinking a balanced current through

the output pair. Like LVDS an input source termination

resistor is required to develop a voltage at the differential

input pair. The FIN24A device incorporates an internal ter-

mination resistor on the CKSI receiver and a gated internal

termination resistor on the DS input receiver. The gated ter-

mination resistor insures proper termination regardless of

direction of data flow.

equal to ½ of V_DDP. The input buffers are only operational

when the device is operating as a serializer. When the

device is operating as a deserializer the inputs are gated

off to conserve power.

The LVCMOS 3-STATE output buffers are rated for a

source/sink current of 2 mAs at 1.8V. The outputs are

active when the DIRI signal is asserted LOW. When the

DIRI signal is asserted HIGH the bi-directional LVCMOS

I/Os will be in a HIGH-Z state. Under purely capacitive load

During power-down mode the differential inputs will be dis-

abled and powered down and the differential outputs will be

placed in a HIGH-Z state.

conditions the output will swing between GND and V_DDP

.

The LVCMOS I/O buffers incorporate bushold functionality

to allow for pins to maintain state when they are not driven.

The bushold circuitry only consumes power during signal

transitions.

FIGURE 7. Bi-directional Differential I/O Circuitry

FIGURE 6. LVCMOS I/O

7

www.fairchildsemi.com

Preliminary

viding a CKREF signal the PLL will power-up and goes

through a lock sequence. One must wait the specified num-

ber of clock cycles prior to capturing valid data into the par-

allel port.

PLL Circuitry

The CKREF input signal is used to provide a reference to

the PLL. The PLL will generate internal timing signals

capable of transferring data at 26 times the incoming

CKREF signal. The output of the PLL is a Bit Clock that is

used to serialize the data. The bit clock is also sent source

synchronously with the serial data stream.

An alternate way of powering down the PLL is by stopping

the CKREF signal either HIGH or LOW. Internal circuitry

detects the lack of transitions and shuts the PLL and serial

I/O down. Internal references will not however be disabled

allowing for the PLL to power-up and re-lock in a lesser

number of clock cycles than when exiting Mode 0. When a

transition is seen on the CKREF signal the PLL will once

again be reactivated.

There are two ways to disable the PLL. The PLL can be

disabled by entering the Mode 0 state (S1 S2 0). The

PLL will disable immediately upon detecting a LOW on

both the S1 and S2 signals. When any of the other modes

are entered by asserting either S1 or S2 HIGH and by pro-

Application Mode Diagrams

Unidirectional Data Transfer

FIGURE 8. Simplified Block Diagram for Unidirectional Serializer and Deserializer

Figure 8 shows the basic operation diagram when a pair of

SerDes is configured in an unidirectional operation mode.

Slave Operation: The device will...

1. Be configured as a deserializer at power-up based on

the value of the DIRI signal.

Master Operation: The device will...

(Please refer to Figure 8)

2. Accept an embedded word boundary bit clock on CKSI.

1. During power-up the device will be configured as a

serializer based on the value of the DIRI signal.

3. Deserialize the DS Data stream using the CKSI input

clock.

2. Accept CKREF_M word clock and generate a bit clock

with embedded word boundary. This bit clock will be

sent to the slave device through the CKSO port.

4. Write parallel data onto the DP_S port and generate

the CKP_S. CKP_S will only be generated when a valid

data word occurs.

3. Receive parallel data on the rising edge of

STROBE_M.

4. Generate and transmit serialized data on the DS sig-

nals which is source synchronous with CKSO.

5. Generate an embedded word clock for each strobe sig-

nal.

www.fairchildsemi.com

8

Preliminary

Application Mode Diagrams (Continued)

FIGURE 9. Unidirectional Serializer and Deserializer

FIGURE 10. Multiple Units, Unidirectional Signals in Each Direction

Figure 10 shows a half duplex connectivity diagram. This

connectivity allows for two unidirectional data streams to

be sent across a single pair of SerDes devices. Data will be

sent on a frame by frame basis. For this mode of operation

to work there needs to be some synchronization between

when the Camera sends its data frame and when the LCD

sends its data. One option for this is to have the LCD send

data during the camera blanking period. External logic may

need to be provided in order for this mode of operation to

work.

the Camera interface at the base. When DIRI, on the right-

hand FIN24A goes LOW data will be sent from the base-

band process to the LCD. The direction is then changed at

DIRO on the right-hand FIN24A indicating to the left-hand

FIN24A to change direction. Data will be sent from the

Base LCD Unit to the LCD. The DIRO pin on the left-hand

FIN24A is used to indicate to the base control unit that the

signals are changing direction and the LCD is now avail-

able to be sent data. DIRI on the right-hand FIN24A could

typically use a timing reference signal such as VSYNC

from the camera interface to indicate direction change. A

derivative of this signal may be required in order to make

sure that no data is lost on the final data transfer.

Devices will alternate frames of data controlled by a direc-

tion control and a direction sense. When DIRI, on the right-

hand FIN24A is HIGH, data will be sent from the Camera to

9

www.fairchildsemi.com

Preliminary

Absolute Maximum Ratings(Note 2)

Recommended Operating

Conditions

Supply Voltage (V_DD

)

0.5V to 4.6V

Continuous

ALL Input/Output Voltage

Supply Voltage (V_DDA, V_DDS

Supply Voltage (V_DDP

Operating Temperature (T_A) (Note 2)

Supply Noise Voltage (V_DDA-PP

)

2.775V 5.0%V

1.65V to 3.6V

10 C to 70 C

100 mV_P-P

LVDS Output Short Circuit Duration

)

Storage Temperature Range (T_STG

Maximum Junction Temperature (T_J)

Lead Temperature (T_L)

)

65 C to 150 C

150 C

)

(Soldering, 4 seconds)

260 C

ESD Rating

Human Body Model, 1.5K , 100pF

Machine Model, 0 , 200pF

2kV

200V

Note 2: Absolute maximum ratings are DC values beyond which the device

may be damaged or have its useful life impaired. The datasheet specifica-

tions should be met, without exception, to ensure that the system design is

reliable over its power supply, temperature, and output/input loading vari-

ables. Fairchild does not recommend operation outside datasheet specifi-

cations.

DC Electrical Characteristics

Over supply voltage and operating temperature ranges, unless otherwise specified.

Min

Typ

Max

Symbol

Parameter

Test Conditions

Unit

(Note 3)

LVCMOS I/O

V

Input High Voltage

0.65 x V

V

DDP

IH

DDP

Input Low Voltage

GND

0.35 x V

V

IL

DDP

Output High Voltage

V

3.3 0.3

OH

DDP

I

2.0 mA

2.5 0.2 0.75 x V

1.8 0.15

3.3 0.3

OH

DDP

V

Output Low Voltage

OL

I

2.0 mA

2.5 0.2

0.25 x V

5.0

V

A

OL

DDP

1.8 0.15

5.0

I

Input Current

V

0V to 3.6V

IN

I

Minimum Bushold Currents

3.0, V

2.3, V

1.95 or 1.05

1.495 or 0.805

1.07 or 0.58

2.34 or 1.26

1.76 or 0.945

1.268 or 0.682

35.0

25.0

10.0

200

I(Hold)

DDP

IN

uA

1.65, V

IN

I

Minimum Required Bushold

Overdrive Current

3.6, V

2.7, V

I(OD)

IN

150

uA

A

1.95, V

75.0

IN

I

Input/Output Power-Off

Leakage Current

0V, V

0, V

DDA

0

OFF

DDS

5.0

ALL LVCMOS Inputs/ Outputs 0V to 3.6V

DIFFERENTIAL I/O

Output Differential Voltage

Magnitude Change from

V

R

100 , See Figure

150

225

925

350

mV

OD

L

V

OD

15.0

Differential LOW-to-HIGH

Offset Voltage

V

2.775 5%

OS

DD

V

Offset Magnitude Change from

Differential LOW-to-HIGH

Short Circuit Output Current

(Note 4)

OS

15.0

I

V

0V

Driver Enabled

Driver Disabled

2.5

1.0

5.0

mA

A

OS

OUT

I

Disabled Output Leakage Current DP 0V to V

, DIRI

V

DDP

10.0

A

OZ

DDP

V

Differential Input Threshold HIGH See Figure 12 and Table 2

Differential Input Threshold LOW See Figure 12 and Table 2

100

mV

TH

V

100

TL

Input Common Mode Range

CKSI Internal Receiver

Termination Resistor

V

2.775 5%

300

925

100

1550

ICM

DD

ID

R

225 mV, V

CKSI |

925 mV, DIRI

0

TRM0

IC

80.0

120

|CKSI

V

ID

DS I/O Termination Resistor

V

225 mV, V

925 mV, DIRI

ID

IC

ID

80.0

100

|DS

DSI |

V

www.fairchildsemi.com

10

Preliminary

DC Electrical Characteristics (Continued)

Min

Typ

Max

Unit

Symbol

Parameter

Input Current

Test Conditions

(Note 3)

I

V

DD

0.3V or 0V

IN

20.0

A

0V or V

DD

25 C. Positive current values refer to the current flowing into device and negative values means

current flowing out of pins. Voltage are referenced to GROUND unless otherwise specified (except and V ).

Note 3: Typical Values are given for V

2.5V and T

A

DD

V

OD

Note 4: The definition of short-circuit includes all the possible situations. For example, the short of differential pairs to Ground, the short of differential pairs

(No Grounding) and either line of differential pairs tied to Ground.

Power Supply Currents

Symbol

Parameter

Test Conditions

Min

Typ

Max

Units

I

V

Serializer Static

All DP and Control Inputs at 0V or V

DDA1

DDA

DD

TBD

A

Supply Current

NOCKREF, S2 0, S1 1, DIR

All DP and Control Inputs at 0V or V

NOCKREF, S2 0, S1 1, DIR

All DP and Control Inputs at 0V or V

NOCKREF, S2 0, S1 1, DIR

All DP and Control Inputs at 0V or V

NOCKREF, S2 0, S1 1, DIR

All DP and Control Inputs at 0V or V

S1 S2

Power-Down Supply Current S1 S2 0,

1

V

Deserializer Static

DDA2

DDA

TBD

5.0

mA

A

Supply Current

Serializer Static

0

V

DDS1

DDS

Supply Current

Deserializer Static

1

V

DDS2

DDS

Supply Current

Static

0

V

DDS

DDA

Supply Current

0

V

DD_PD

DD_SER1

DD

I

All Inputs at GND or V

DD_PD

DDA

DDS

DDP

DD

26:1 Dynamic Serializer

Power Supply Current

S2

S1

S2

S1

S2

S1

S2

S1

S2

S1

S2

S1

L

2 MHz

TBD

CKREF STROBE

H

L

5 MHz

I

DDP

DIRI

H

DD_SER1

DDA

DDS

mA

See Figure 13

15 MHz

10 MHz

30 MHz

2 MHz

H

L

I

1:26 Dynamic Deserializer

Power Supply Current

DD_DES1

CKREF STROBE

H

L

5 MHz

I

DDP

DIRI

L

5 MHz

DD_DES1

DDA

DDS

mA

See Figure 13

15 MHz

10 MHz

30 MHz

2 MHz

H

26:1 Dynamic Serializer Power

Supply Current

NO CKREF

DD_SER2

STROBE

Active

5 MHz

I

DDP

CKSI 15X Strobe

10 MHz

15 MHz

30 MHz

DD_SER2

DDA

DDS

DIRI

H

See Figure 13

11

www.fairchildsemi.com

Preliminary

AC Electrical Characteristics

Over supply voltage and operating temperature ranges, unless otherwise specified.

Symbol Parameter Test Conditions

Serializer Electrical Characteristics

Min

Typ

Max

Units

ns

t

CKREF Clock Period

(2 MHz - 30 MHz)

See Figure 17

S2

0

1

S1

1

0

200

500

200

TCP

CKREF

66.0

T

STROBE

S2

1

0

1

S1

1

0

1

33.0

100

5.0

f

CKREF Frequency Relative

to Strobe Frequency

CKREF

REF

does not equal

STROBE

1.1 *f

15.0

30.0

TBD

MHz

ST

t

f

CKREF Clock High Time

CKREF Clock Low Time

TBD

0.5

T

CPWH

CPWL

CLKT

SPWH

SPWL

MAX

T

LVCMOS Input Transition Time

STROBE Pulse Width HIGH

STROBE Pulse Width LOW

Maximum Serial Data Rate

See Figure 17

CKREF x 26

ns

5.0

S2

0

1

S1

1

0

1

52.0

130

260

130

390

780

Mb/s

Serializer AC Electrical Characteristics

t

Differential Output Rise Time (20% to 80%)

Differential Output Fall Time (80% to 20%)

DP[n] Setup to STROBE

0.6

0.9

ns

TLH

See Figure 14

THL

DIRI

1

2.5

0

STC

HTC

TCCD

DP[n] Hold to STROBE

See Figure 16 (f 10 MHz)

See Figure 20, DIRI 1,

CKREF STROBE

Transmitter Clock Input to

TBD

ns

Clock Output Delay

t

CKSO Position Relative to DS

See Figure 23, (Note 5)

CKREF Serialization Mode

See Figure 23, (Note 5)

SPOS

No CKREF Serialization Mode

PLL AC Electrical Characteristics Specifications

t

CKSO Clock Out Jitter (Cycle-to-Cycle)

(Note 6)

TBD

ns

JCC

Serializer Phase Lock Loop Stabilization

Time

See Figure 19

1000

Cycles

TPLLS0

t

PLL Disable Time Loss of Clock

PLL Power-Down Time

See Figure 24, (Note 7)

See Figure 25

3.0

10.0

20.0

us

ns

TPLLD0

TPLLD1

Deserializer AC Electrical Characteristics

t

Serial Port Setup Time, DS-to-CKSI

Serial Port Hold Time, DS-to-CKS

Figure 22, (Note 8)

500

ps

ns

S_DS

H_DS

RCOP

RCOL

RCOH

Deserializer Clock Output (CKP OUT) Period Figure 18

33.0

T

500

CKP OUT Low Time

CKP OUT High Time

Figure 18 (Rising Edge Strobe)

Serializer Source STROBE CKREF

Where a (1/f)/26 (Note 9)

13a-3

13a 3

t

Data Valid to CKP LOW

Figure 18 (Rising Edge Strobe)

Where a (1/f)/26 (Note 9)

6a-3

6a

6a 3

ns

PDV

t

Output Rise Time (20% to 80%)

Output Fall time (80% to 20%)

C

8 pF

2.5

5.0

ns

ROLH

ROHL

L

Figure 15

Note 5: Skew is measured from either the rising or falling edge of the clock (CKSO) relative to the center of the data bit (DSO). Both outputs should have

identical load conditions for this to be valid.

Note 6: This jitter specification is based on the assumption that PLL has a REF Clock with cycle-to-cycle input jitter less than 2ns.

Note 7: The power-down time is a function of the CKREF frequency prior to CKREF being stopped HIGH or LOW and the state of the S1/S2 mode pins. The

specific number of clock cycles required for the PLL to be disabled will vary dependent upon the operating mode of the device.

Note 8: Signals are transmitted from the serializer source synchronously. Note that in some cases data is transmitted when the clock remains at a high state.

Skew should only be measured when data and clock are transitioning at the same time. Total measured input skew would be a combination of output skew

from the serializer, load variations and ISI and jitter effects.

Note 9: Rising edge of CKP will appear approximately 13 bit times after the falling edge of the CKP output. Falling edge of CKP will occur approximately 6 bit

times after a data transition. Variation with respect to the CKP signal is due to internal propagation delays of the device. Note that if CKREF is not equal to

STROBE for the serializer the CKP signal will not maintain a 50% Duty Cycle. The low time of CKP will remain 13 bit times.

www.fairchildsemi.com

12

Preliminary

Control Logic Timing Controls

Symbol

Parameter

Propagation Delay

Test Conditions

Min

Typ

Max

Units

t

,

PHL_DIR

PLH_DIR

DIRI LOW-to-HIGH or HIGH-to-LOW

TBD

7.0

ns

DIRI-to-DIRO

,

Propagation Delay

DIRI-to-DP

PLZ

PHZ

DIRI LOW-to-HIGH

DIRI HIGH-to-LOW

7.0

10.0

7.0

ns

,

Propagation Delay

DIRI-to-DP

PZL

PZH

,

Deserializer Disable Time:

S0 or S1 to DP

DIRI 0,

PLZ

S1(2) 0 and S2(1) LOW-to-HIGH Figure 26

DIRI 0,

PHZ

,

Deserializer Enable Time:

S0 or S1 to DP

PZL

10.0

7.0

S1(2) 0 and S2(1) LOW-to-HIGH Figure 26

DIRI 1,

PZH

,

Serializer Disable Time:

S0 or S1 to CKSO, DS

Serializer Enable Time:

S0 or S1 to CKSO, DS

PLZ

S1(2) 0 and S2(1) HIGH-to-LOW Figure 25

DIRI 1,

PHZ

,

PZL

10.0

S1(2) and S2(1) LOW-to-HIGH Figure 25

PZH

Capacitance

Symbol

Parameter

Test Conditions

Min

Typ

Max

Units

C

Capacitance of Input Only Signals,

CKREF, STROBE, S1, S2, DIRI

Capacitance of Parallel Port Pins

DIRI 1, S1 0,

IN

TBD

pF

V

2.5V

DIRI 1, S1 0,

2.5V

Capacitance of Differential I/O Signals DIRI 0, PwnDwn 0;

S1 0, V 2.5V

DD

C

IO

TBD

pF

DP

V

DD

1:12

IO-DIFF

DD

13

www.fairchildsemi.com

Preliminary

AC Loading and Waveforms

Note A: For All input pulses, t or t

1 ns

R

F

FIGURE 12. Differential Receiver Voltage Definitions

FIGURE 11. Differential LpLVDS Output DC Test Circuit

Note: The Worst Case test pattern produces a maximum toggling of internal digital circuits, LpLVDS I/O and LVCMOS I/O with the PLL operating at the ref-

erence frequency unless otherwise specified. Maximum power is measured at the maximum V values. Minimum values are measured at the minimum V

DD

values. Typical values are measured at V

2.5V.

DD

FIGURE 13. “Worst Case” Serializer Test Pattern

FIGURE 14. LpLVDS Output Load

and Transition Times

FIGURE 15. LVCMOS Output Load

and Transition Times

www.fairchildsemi.com

14

Preliminary

AC Loading and Waveforms (Continued)

Setup: MODE0 “0” or “1”, MODE1 “1”, SER/DES “1”

FIGURE 17. LVCMOS Clock Parameters

FIGURE 16. Serial Setup and Hold Time

Setup: EN_DES “1”, CKSI and DSI are valid signals

Note: CKREF Signal is free running.

FIGURE 18. Deserializer Data Valid Window Time

and Clock Output Parameters

FIGURE 19. Serializer PLL Lock Time

Note: STROBE CKREF

FIGURE 20. Serializer Clock Propagation Delay

FIGURE 21. Deserializer Clock Propagation Delay

15

www.fairchildsemi.com

Preliminary

AC Loading and Waveforms (Continued)

FIGURE 23. Differential Output Signal Skew

FIGURE 22. Differential Input Setup and Hold Times

Note: CKREF Signal can be stopped either HIGH or LOW

FIGURE 24. PLL Loss of Clock Disable Time

FIGURE 25. PLL Power-Down Time

Note: If S1(2) transitioning then S2(1) must 0 for test to be valid

Note: CKREF must be active and PLL must be stable

FIGURE 27. Deserializer Enable and Disable Times

FIGURE 26. Serializer Enable and Disable Time

www.fairchildsemi.com

16

Preliminary

Tape and Reel Specification

TAPE FORMAT for USS-BGA

Dimensions are in millimeters

A₀

B₀

D₁

K₀

P₁

P₀

P₂

0/05 TYP

2.0 0.3

T_C

W_C

D

E

F

T

W

0.3

Package

0.10

0.05

1.55

min

0.1

5.5

0.1

TYP

0.005

TYP

3.5 x 4.5 TBD

TBD

1.5

1.75

1.1

8.0

4.0

0.07

12.0

9.3

Note: A0, B0, and K0 dimensions are determined with respect to the EIA/JEDEC RS-481 rotational and lateral movement requirements

(see sketches A, B, and C).

Dimensions are in millimeters

Dia A

max

330

Dim B

min

1.5

Dia C

0.5/ 0.2

13.0

Dia D

min

Dim N

min

178

Dim W1

2.0/ 0

8.4

Dim W2

max

Dim W3

Tape Width

(LSL - USL)

7.9 10.4

8

20.2

14.4

12

16

330

1.5

13.0

178

12.4

18.4

11.9 15.4

15.9 19.4

330

1.5

13.0

178

16.4

22.4

17

www.fairchildsemi.com

Preliminary

Tape and Reel Specification (Continued)

TAPE FORMAT for MLP

Package

Tape

Section

Number

Cavities

125 (typ)

3000

Cavity

Status

Empty

Filled

Cover Tape

Status

Designator

Leader (Start End)

Carrier

Sealed

MLX

Sealed

Trailer (Hub End)

75 (typ)

Empty

Sealed

MLP Embossed Tape Dimension

www.fairchildsemi.com

18

Preliminary

Physical Dimensions inches (millimeters) unless otherwise noted

Pb-Free 42-Ball Ultra Small Scale Ball Grid Array (USS-BGA), JEDEC MO-195, 3.5mm Wide

Package Number BGA042A

19

www.fairchildsemi.com

Preliminary

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Pb-Free 40-Terminal Molded Leadless Package (MLP), Quad, JEDEC MO-220, 6mm Square

Package Number MLP040A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical component in any component of a life support

device or system whose failure to perform can be rea-

sonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

www.fairchildsemi.com

20


型号：	FIN24A
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	Low Voltage 24-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges (Preliminary) 低电压24位双向串行器/解串器与多个频率范围（初步）
文件：	总20页 (文件大小：1759K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

FIN24A [FAIRCHILD]

相关型号：

FIN24AC

FIN24ACGFX

FIN24ACMLX

FIN24AC_07

FIN24AGFX

FIN24AMLX

FIN24C

FIN24CGFX

FIN24CMLX

FIN24C_06

FIN24GFX

FIN24MLX