FIN3386 [FAIRCHILD]
Low Voltage 28-Bit Flat Panel Display Link Serializers/Deserializers; 低电压28位平板显示器连接串行器/解串器
| 型号： | FIN3386 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Low Voltage 28-Bit Flat Panel Display Link Serializers/Deserializers |
| 文件： | 总18页 (文件大小：551K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
October 2003
Revised April 2005
FIN3385 • FIN3383 •
FIN3384 • FIN3386
Low Voltage 28-Bit Flat Panel Display Link
Serializers/Deserializers
General Description
Features
■ Low power consumption
The FIN3385 and FIN3383 transform 28 bit wide parallel
LVTTL (Low Voltage TTL) data into 4 serial LVDS (Low
Voltage Differential Signaling) data streams. A phase-
locked transmit clock is transmitted in parallel with the data
stream over a separate LVDS link. Every cycle of transmit
clock 28 bits of input LVTTL data are sampled and trans-
mitted.
■ 20 MHz to 85 MHz shift clock support
1V common-mode range around 1.2V
■
■ Narrow bus reduces cable size and cost
■ High throughput (up to 2.38 Gbps throughput)
■ Internal PLL with no external component
■ Compatible with TIA/EIA-644 specification
■ Devices are offered 56-lead TSSOP packages
The FIN3386 and FIN3384 receive and convert the 4/3
serial LVDS data streams back into 28/21 bits of LVTTL
data. Refer to Table 1 for a matrix summary of the Serializ-
ers and Deserializers available. For the FIN3385, at a
transmit clock frequency of 85MHz, 28 bits of LVTTL data
are transmitted at a rate of 595Mbps per LVDS channel.
These chipsets are an ideal solution to solve EMI and cable
size problems associated with wide and high-speed TTL
interfaces.
Ordering Code:
Order Number Package Number
Package Description
FIN3383MTD
FIN3384MTD
FIN3385MTD
FIN3386MTD
MTD56
MTD56
MTD56
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
TABLE 1. Display Panel Link Serializers/Deserializers Chip Matrix
Part
CLK Frequency LVTTL IN
LVDS OUT
LVDS IN
LVTTL OUT
Package
56 TSSOP
56 TSSOP
56 TSSOP
56 TSSOP
FIN3385
FIN3383
FIN3386
FIN3384
85
66
85
66
28
28
4
4
4
4
28
28
© 2005 Fairchild Semiconductor Corporation
DS500864
www.fairchildsemi.com
Block Diagrams
Functional Diagram for FIN3385 and FIN3383
Receiver Functional Diagram for FIN3386 and FIN3384
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2
TRANSMITTERS
Pin Descriptions
Pin Names I/O Type Number of Pins
Description of Signals
LVTTL Level Input
TxIn
I
I
28/21
1
TxCLKIn
LVTTL Level Clock Input
The rising edge is for data strobe.
TxOut
TxOut
O
O
O
O
I
4/3
4/3
1
Positive LVDS Differential Data Output
Negative LVDS Differential Data Output
Positive LVDS Differential Clock Output
Negative LVDS Differential Clock Output
Rising Edge Clock (HIGH), Falling Edge Clock (LOW)
TxCLKOut
TxCLKOut
R_FB
1
1
PwrDn
I
1
LVTTL Level Power-Down Input
Assertion (LOW) puts the outputs in High Impedance state.
PLL VCC
PLL GND
LVDS VCC
LVDS GND
VCC
I
I
I
I
I
I
1
2
1
3
3
5
Power Supply Pin for PLL
Ground Pins for PLL
Power Supply Pin for LVDS Output
Ground Pins for LVDS Output
Power Supply Pins for LVTTL Input
Ground pins for LVTTL Input
No Connect
GND
NC
Connection Diagram
Truth Table
Inputs
Outputs
TxCLKOut
FIN3383 and FIN3385 (28:4 Transmitter)
Pin Assignment for TSSOP
PwrDn
(Note 1)
TxIn
TxCLKIn
TxOut
Active
Active
L/H/Z
Active
F
H
H
H
H
L
L/H
L/H
L
L/H
X (Note 2)
L/H
Active
F
F
X
L
X (Note 2)
Z
X
Z
H
L
X
Z
F
HIGH Logic Level
LOW Logic Level
Don’t Care
High Impedance
Floating
Note 1: The outputs of the transmitter or receiver will remain in a
High Impedance state until V reaches 2V.
CC
Note 2: TxCLKOut will settle at a free running frequency when the
part is powered up, PwrDn is HIGH and the TxCLKIn is a steady logic
level (L/H/Z).
3
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RECEIVERS
Pin Descriptions
Number
of Pins
Pin Names I/O Type
Description of Signals
Negative LVDS Differential Data Input
RxIn
RxIn
I
I
4/3
4/3
1
Positive LVDS Differential Data Input
Negative LVDS Differential Clock Input
Positive LVDS Differential Clock Input
RxCLKIn
RxCLKIn
RxOut
I
I
1
O
28/21 LVTTL Level Data Output
Goes HIGH for PwrDn LOW
RxCLKOut
PwrDn
O
I
1
1
LVTTL Clock Output
LVTTL Level Input
Refer to Transmitter and Receiver Power-Up and Power-Down Operation Truth Table
PLL VCC
PLL GND
LVDS VCC
LVDS GND
VCC
I
I
I
I
I
I
1
2
1
3
4
5
Power Supply Pin for PLL
Ground Pins for PLL
Power Supply Pin for LVDS Input
Ground Pins for LVDS Input
Power Supply for LVTTL Output
Ground Pin for LVTTL Output
No Connect
GND
NC
Connection Diagram
FIN3386 and FIN3384 (4:28 Receiver)
Pin Assignment for TSSOP
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4
Transmitter and Receiver Power-Up/Power-Down Operation Truth Table
The outputs of the transmitter remain in the High-Impedance state until the power supply reaches 2V. The following table
shows the operation of the transmitter during power-up and power-down and operation of the PwrDn pin.
Transmitter
PwrDn
Normal
2V
VCC
TxIn
2V
X
Z
2V
2V
Active
X
2V
2V
X
Active
Active
Active
Active
H
TxOut
Z
TxCLKIn
TxCLKOut
PwrDn
X
Z
X
H/L/Z
(Note 3)
H
Z
L
L
H
H
Receiver
PwrDn
RxIn
RxOut
X
Z
X
Active
L/H
Active
P
(Note 4)
H
(Note 4)
P
L
RxCLKIn
RxCLKOut
PwrDn
VCC
X
Z
X
(Note 5)
L
Active
Active
H
(Note 4)
(Note 5)
H
Active
(Note 5)
H
(Note 4)
(Note 5)
H
L
2V
2V
2V
2V
2V
2V
H
L
P
X
Z
HIGH Logic Level
LOW Logic Level
Last Valid State
Don’t Care
High-Impedance
Note 3: If the transmitter is powered up and PwrDn is inactive HIGH and the clock input goes to any state LOW, HIGH, or Z then the internal PLL will go to a
known low frequency and stay until the clock starts normal operation again.
Note 4: If the input is terminated and un-driven (Z) or shorted or open. (fail safe condition)
Note 5: For PwrDn or fail safe condition the RxCLKOut pin will go LOW for Panel Link devices and HIGH for Channel Link devices.
Note 6: Shorted here means ( inputs are shorted to each other, or inputs are shorted to each other and Ground or V , or either inputs are shorted to
CC
Ground or V ) with no other Current/Voltage sources (noise) applied. If the V is still in the valid range (greater than 100mV) and VCM is in the valid range
CC
ID
(0V to 2.4V) then the input signal is still recognized and the part will respond normally.
5
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Absolute Maximum Ratings(Note 7)
Recommended Operating
Conditions
Power Supply Voltage (VCC
)
-0.3V to +4.6V
0.5V to 4.6V
-0.3V to +4.6V
Continuous
TTL/CMOS Input/Output Voltage
LVDS Input/Output Voltage
Supply Voltage (VCC
)
3.0V to 3.6V
Operating Temperature (TA)(Note 7)
Maximum Supply Noise Voltage
10°C to 70°C
LVDS Output Short Circuit Current (IOSD
)
Storage Temperature Range (TSTG
)
65 C to 150 C
150 C
(VCCNPP
)
100 mVP-P (Note 8)
Maximum Junction Temperature (TJ)
Lead Temperature (TL)
(Soldering, 4 seconds)
ESD Rating (HBM, 1.5 k , 100 pF)
I/O to GND
Note 7: Absolute maximum ratings are DC values beyond which the device
may be damaged or have its useful life impaired. The datasheet specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari-
ables. Fairchild does not recommend operation outside datasheet specifi-
cations.
260 C
10.0 kV
6.5 kV
400V
All Pins
Note 8: 100mV V noise should be tested for frequency at least up to
CC
2 MHz. All the specification below should be met under such a noise.
ESD Rating (MM, 0 , 200 pF)
Transmitter DC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified. (Note 9)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Transmitter LVTTL Input Characteristics
V
V
V
Input High Voltage
Input Low Voltage
Input Clamp Voltage
Input Current
2.0
V
V
V
V
IH
CC
GND
0.8
1.5
IL
I
18 mA
0.79
1.8
0
IK
IK
I
V
V
0.4V to 4.6V
GND
10.0
IN
IN
A
10.0
250
IN
Transmitter LVDS Output Characteristics (Note 10)
Output Differential Voltage
Magnitude Change from Differential LOW-to-HIGH
V
TBD
1.25
450
35.0
mV
mV
V
OD
V
V
OD
OD
R
100 , See Figure 1
L
V
Offset Voltage
1.125
1.375
OS
V
Offset Magnitude Change from Differential LOW-to-HIGH
Short Circuit Output Current
mV
mA
OS
I
I
V
0V
3.5
1.0
5.0
OS
OUT
Disabled Output Leakage Current
DO 0V to 4.6V, PwrDn 0V
10.0
A
OZ
Transmitter Supply Current
I
28:4 Transmitter Power Supply Current
for Worst Case Pattern (With Load)
(Note 11)
32.5 MHz
31.0
32.0
37.0
42.0
49.5
55.0
60.5
66.0
CCWT
R
100
,
40.0 MHz
66.0 MHz
85.0 MHz
L
mA
See Figure 3
I
I
Powered Down Supply Current
28:4 Transmitter Supply Current
for 16 Grayscale (Note 11)
PwrDn 0.8V
10.0
29.0
30.0
35.0
39.0
55.0
41.8
44.0
49.5
55.0
A
CCPDT
CCGT
32.5 MHz
40.0 MHz
65.0 MHz
85.0 MHz
See Figure 21
(Note 12)
mA
Note 9: All Typical values are at T
25 C and with V
3.3V.
Note 10: Positive current values refer to the current flowing into device and negative values means current flowing out of pins. Voltage are referenced to
ground unless otherwise specified (except and V ).
A
CC
V
OD
OD
Note 11: The power supply current for both transmitter and receiver can be different with the number of active I/O channels.
Note 12: The 16-grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching
needed to produce groups of 16 vertical strips across the display.
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6
Transmitter AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified.
Symbol Parameter Test Conditions
Transmit Clock Period
Min
11.76
0.35
0.35
1.0
Typ
T
Max
50.0
0.65
0.65
6.0
Units
ns
T
t
t
t
t
t
t
TCP
Transmit Clock (TxCLKIn) HIGH Time
Transmit Clock Low Time
See Figure 5
0.5
0.5
TCH
TCL
CLKT
JIT
T
TxCLKIn Transition Time (Rising and Failing)
TxCLKIn Cycle-to-Cycle Jitter
TxIn Transition Time
(10% to 90%) See Figure 6
ns
ns
ns
3.0
1.5
6.0
XIT
LVDS Transmitter Timing Characteristics
t
t
t
t
t
t
Differential Output Rise Time (20% to 80%)
Differential Output Fall Time (80% to 20%)
TxIn Setup to TxCLNIn
0.75
0.75
1.5
1.5
ns
ns
ns
ns
ns
TLH
See Figure 4
THL
2.5
0
STC
See Figure 5 (f 85 MHz)
See Figure 12, (Note 13)
TxIn Holds to TCLKIn
HTC
TPDD
TCCD
Transmitter Power-Down Delay
100
5.5
6.8
Transmitter Clock Input to Clock Output Delay
Transmitter Clock Input to Clock Output Delay
(T
25 C and with V
3.3V)
A
CC
ns
See Figure 9
2.8
Transmitter Output Data Jitter (f 40 MHz) (Note 14)
t
t
t
t
t
t
t
Transmitter Output Pulse Position of Bit 0
Transmitter Output Pulse Position of Bit 1
Transmitter Output Pulse Position of Bit 2
Transmitter Output Pulse Position of Bit 3
Transmitter Output Pulse Position of Bit 4
Transmitter Output Pulse Position of Bit 5
Transmitter Output Pulse Position of Bit 6
0.25
0
0.25
ns
ns
ns
ns
ns
ns
ns
TPPB0
TPPB1
TPPB2
TPPB3
TPPB4
TPPB5
TPPB6
See Figure 16
a 0.25
a
a 0.25
1
2a 0.25
3a 0.25
4a 0.25
5a 0.25
6a 0.25
2a
3a
4a
5a
6a
2a 0.25
3a 0.25
4a 0.25
5a 0.25
6a 0.25
a
f x 7
Transmitter Output Data Jitter (f 65 MHz) (Note 14)
t
t
t
t
t
t
t
Transmitter Output Pulse Position of Bit 0
Transmitter Output Pulse Position of Bit 1
Transmitter Output Pulse Position of Bit 2
Transmitter Output Pulse Position of Bit 3
Transmitter Output Pulse Position of Bit 4
Transmitter Output Pulse Position of Bit 5
Transmitter Output Pulse Position of Bit 6
0.2
0
0.2
ns
ns
ns
ns
ns
ns
ns
TPPB0
TPPB1
TPPB2
TPPB3
TPPB4
TPPB5
TPPB6
See Figure 16
a 0.2
a
a 0.2
1
2a 0.2
3a 0.2
4a 0.2
5a 0.2
6a 0.2
2a
3a
4a
5a
6a
2a 0.2
3a 0.2
4a 0.2
5a 0.2
6a 0.2
a
f x 7
Transmitter Output Data Jitter (f 85 MHz) (Note 14)
t
t
t
t
t
t
t
t
Transmitter Output Pulse Position of Bit 0
Transmitter Output Pulse Position of Bit 1
Transmitter Output Pulse Position of Bit 2
Transmitter Output Pulse Position of Bit 3
Transmitter Output Pulse Position of Bit 4
Transmitter Output Pulse Position of Bit 5
Transmitter Output Pulse Position of Bit 6
FIN3385 Transmitter Clock Out Jitter
(Cycle-to-Cycle)
0.2
0
a
0.2
ns
ns
ns
ns
ns
ns
ns
TPPB0
TPPB1
TPPB2
TPPB3
TPPB4
TPPB5
TPPB6
JCC
See Figure 16
a 0.2
a 0.2
1
2a 0.2
3a 0.2
4a 0.2
5a 0.2
6a 0.2
2a
3a
4a
5a
6a
350
210
110
2a 0.2
3a 0.2
4a 0.2
5a 0.2
6a 0.2
370
a
f x 7
f
f
f
40 MHz
65 MHz
85 MHz
230
ps
See Figure 20
150
t
Transmitter Phase Lock Loop Set Time (Note 15)
See Figure 22, (Note 14)
10.0
ms
TPLLS
Note 13: Outputs of all transmitters stay in 3-STATE until power reaches 2V. Both clock and data output begins to toggle 10ms after V
reaches 3V and
CC
Power-Down pin is above 1.5V.
Note 14: This output data pulse position works for TTL inputs except the LVDS output bit mapping difference (see Figure 14). Figure 16 shows the skew
between the first data bit and clock output. Also 2-bit cycle delay is guaranteed when the MSB is output from transmitter.
Note 15: This jitter specification is based on the assumption that PLL has a ref clock with cycle-to-cycle input jitter less than 2ns.
7
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Receiver DC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified. (Note 16)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
LVTTL/CMOS DC Characteristics
V
V
V
V
V
Input High Voltage
2.0
GND
2.7
V
V
V
V
V
V
A
IH
CC
Input Low Voltage
0.8
IL
Output High Voltage
Output Low Voltage
Input Clamp Voltage
Input Current
I
I
I
0.4 mA
2mA
3.3
OH
OL
IK
OH
OL
IK
0.06
0.79
0.3
1.5
18 mA
0V to 4.6V
0V,
I
I
V
V
10.0
10.0
IN
IN
Input/Output Power Off Leakage Current
OFF
CC
10.0
120
A
All LVTTL Inputs/Outputs 0V to 4.6V
0V
I
Output Short Circuit Current
V
60.0
mA
OS
OUT
Receiver LVDS Input Characteristics
V
V
V
Differential Input Threshold HIGH
Differential Input Threshold LOW
Input Common Mode Range
Input Current
Figure 2, Table 2
Figure 2, Table 2
Figure 2, Table 2
100
mV
mV
V
TH
TL
100
0.05
2.35
10.0
10.0
ICM
I
V
V
2.4V, V
CC
3.6V or 0V
3.6V or 0V
A
IN
IN
IN
0V, V
A
CC
Receiver Supply Current
I
I
4:28 Receiver Power Supply Current
for Worst Case Pattern (With Load)
(Note 17)
32.5 MHz
70.0
75.0
114
CCWR
CCWR
C
8 pF,
40.0 MHz
66.0 MHz
85.0 MHz
32.5 MHz
40.0 MHz
66.0 MHz
85.0 MHz
L
mA
See Figure 3
135
60.0
65.0
100
115
3:21 Receiver Power Supply Current
for Worst Case Pattern (With Load)
(Note 17)
49.0
53.0
78.0
90.0
C
8 pF,
L
mA
A
See Figure 3
I
t
t
t
t
t
t
t
t
Powered Down Supply Current
Receiver Clock Output (RxCLKOut) Period
RxCLKOut LOW Time
PwrDn 0.8V (RxOut stays LOW)
NA
T
55.0
50.0
6.0
CCPDT
RCOP
RCOL
RCOH
RSRC
RHRC
ROLH
ROHL
RCCD
11.76
4.0
See Figure 8
5.0
5.0
ns
ns
ns
ns
ns
ns
RxCLKOut HIGH Time
(f 85MHz)
4.5
6.5
RxOut Valid Prior to RxCLKOut
RxOut Valid After RxCLKOut
(Rising Edge Strobe)
3.5
3.5
Output Rise Time (20% to 80%)
Output Fall Time (80% to 20%)
Receiver Clock Input to Clock Output Delay
C
8 pF,
2.0
1.8
3.5
3.5
L
See Figure 4
See Figure 20, (Note 18)
3.5
5.0
7.5
ns
T
25 C and V
3.3V
A
CC
t
t
t
t
t
t
t
t
t
t
Receiver Power-Down Delay
See Figure 13
1.0
1.19
2.87
4.55
6.23
7.91
9.59
11.27
s
ns
ns
ns
ns
ns
ns
ns
ps
ms
RPDD
Receiver Input Strobe Position of Bit 0
Receiver Input Strobe Position of Bit 1
Receiver Input Strobe Position of Bit 2
Receiver Input Strobe Position of Bit 3
Receiver Input Strobe Position of Bit 4
Receiver Input Strobe Position of Bit 5
Receiver Input Strobe Position of Bit 6
RxIN Skew Margin
0.49
2.17
3.85
5.53
7.21
8.89
10.57
290
0.84
2.52
4.20
5.88
7.56
9.24
10.92
RSPB0
RSPB1
RSPB2
RSPB3
RSPB4
RSPB5
RSPB6
RSKM
RPLLS
See Figure 17 (f 85MHz)
See Figure 17, (Note 19)
See Figure 11
Receiver Phase Lock Loop Set Time
10.0
Note 16: All Typical values are at T
25 C and with V
3.3V. Positive current values refer to the current flowing into device and negative values means
current flowing out of pins. Voltage are referenced to ground unless otherwise specified (except and V ).
Note 17: The power supply current for the receiver can be different with the number of active I/O channels.
Note 18: Total channel latency from Sewrializer to deserializer is (T ). There is the clock period.
Note 19: Receiver skew margin is defined as the valid sampling window after considering potential setup/hold time and minimum/maximum bit position.
A
CC
V
OD
OD
t
TCCD
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8
Receiver AC Electrical Characteristics (66MHz)
Symbol
Parameter
Receiver Clock Output (RxCLKOut) Period
RxCLKOut LOW Time
Test Conditions
See Figure 8
Min
15.0
10.0
10.0
6.5
Typ
T
Max
Units
ns
t
t
t
t
t
t
t
t
t
t
t
t
50.0
RCOP
RCOL
RCOH
RSRC
RHRC
RCOL
RCOH
RSRC
RHRC
ROLH
ROHL
RCCD
11.0
12.2
11.6
11.6
6.3
ns
RxCLKOut HIGH Time
See Figure 8
ns
RxOut Valid Prior to RxCLKOut
RxOut Valid After RxCLKOut
RxCLKOut LOW Time
(Rising Edge Strobe)
(f 40 MHz)
ns
6.0
ns
5.0
9.0
9.0
ns
RxCLKOut HIGH Time
See Figure 8, (Note 20)
(Rising Edge Strobe)
(f 66 MHz)
5.0
7.6
ns
RxOut Valid Prior to RxCLKOut
RxOut Valid After RxCLKOut
Output Rise Time (20% to 80%)
Output Fall Time (80% to 20%)
Receiver Clock Input to Clock Output Delay
4.5
7.3
ns
4.0
6.3
ns
C
8 pF, (Note 20)
2.0
5.0
5.0
ns
L
See Figure 8
1.8
ns
See Figure 10, (Note 21)
3.5
5.0
7.5
ns
T
25 C and V
3.3V
A
CC
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Receiver Power-Down Delay
See Figure 13
1.0
2.15
5.8
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RPDD
Receiver Input Strobe Position of Bit 0
Receiver Input Strobe Position of Bit 1
Receiver Input Strobe Position of Bit 2
Receiver Input Strobe Position of Bit 3
Receiver Input Strobe Position of Bit 4
Receiver Input Strobe Position of Bit 5
Receiver Input Strobe Position of Bit 6
Receiver Input Strobe Position of Bit 0
Receiver Input Strobe Position of Bit 1
Receiver Input Strobe Position of Bit2
Receiver Input Strobe Position of Bit 3
Receiver Input Strobe Position of Bit 4
Receiver Input Strobe Position of Bit 5
Receiver Input Strobe Position of Bit 6
RxIn Skew Margin
1.0
4.5
1.4
5.0
RSPB0
RSPB1
RSPB2
RSPB3
RSPB4
RSPB5
RSPB6
RSPB0
RSPB1
RSPB2
RSPB3
RSPB4
RSPB5
RSPB6
RSKM
See Figure 17
(f 40 MHz)
8.1
8.5
9.15
12.6
16.3
19.9
23.6
1.4
11.6
15.1
18.8
22.5
0.7
11.9
15.6
19.2
22.9
1.1
2.9
3.3
3.6
See Figure 17
(f 65 MHz)
5.1
5.5
5.8
7.3
7.7
8.0
9.5
9.9
10.2
12.4
14.6
11.7
13.9
490
400
12.1
14.3
f
f
40 MHz
66 MHz
ps
See Figure 17, (Note 22)
t
Receiver Phase Lock Loop Set Time
See Figure 11
10.0
ms
RPLLS
Note 20: For the receiver with falling-edge strobe, the definition of setup/hold time will be slightly different from the one with rising-edge strobe. The clock ref-
erence point is the time when the clock falling edge passes through 2V. For hold time t
, the clock reference point is the time when falling edge passes
RHRC
through 0.8V.
Note 21: Total channel latency from Sewrializer to deserializer is (T
t
)
(2*T
t
). There is the clock period.
TCCD
RCCD
Note 22: Receiver skew margin is defined as the valid sampling window after considering potential setup/hold time and minimum/maximum bit position.
9
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FIGURE 1. Differential LVDS Output DC Test Circuit
Note A: For all input pulses, t or t
1 ns.
R
F
Note B: C includes all probe and jig capacitance.
L
FIGURE 2. Differential Receiver Voltage Definitions and Propagation Delay and Transition Time Test Circuit
TABLE 2. Receiver Minimum and Maximum Input Threshold Test Voltages
Applied Voltages
(V)
Resulting Differential Input Voltage Resulting Common Mode Input Voltage
(mV)
VID
(V)
VIC
VIA
VIB
1.25
1.15
2.4
2.3
0.1
0
1.15
1.25
2.3
2.4
0
100
100
100
100
100
100
600
600
600
600
600
600
1.2
1.2
2.35
2.35
0.05
0.05
1.2
0.1
0.9
1.5
1.8
2.4
0
1.5
0.9
2.4
1.8
0.6
0
1.2
2.1
2.1
0.3
0.6
0.3
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10
AC Loading and Waveforms
Note: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and LVTTL/CMOS I/O. Depending on the valid strobe edge of
transmitter, the TxCLKIn can be either rising or falling edge data strobe.
FIGURE 3. “Worst Case” Test Pattern
FIGURE 4. Transmitter LVDS Output Load and Transition Times
FIGURE 5. Transmitter Setup/Hold and HIGH/LOW Times (Rising Edge Strobe)
FIGURE 6. Transmitter Input Clock Transition Time
11
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AC Loading and Waveforms (Continued)
FIGURE 7. Transmitter Outputs Channel-to-Channel Skew
Note: For the receiver with falling-edge strobe, the definition of setup/hold time will be slightly different from the one with rising-edge strobe. The clock refer-
ence point is the time when the clock falling edge passes through 2V. For hold time t
, the clock reference point is the time when falling edge passes
RHRC
through 0.8V.
FIGURE 8. (Receiver) Setup/Hold and HIGH/LOW Times
FIGURE 9. Transmitter Clock In to Clock Out Delay (Rising Edge Strobe)
FIGURE 10. Receiver Clock In to Clock Out Delay (Falling Edge Strobe)
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12
AC Loading and Waveforms (Continued)
FIGURE 11. Receiver Phase Lock Loop Set Time
FIGURE 12. Transmitter Power-Down Delay
FIGURE 13. Receiver Power-Down Delay
13
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AC Loading and Waveforms (Continued)
Note: The information in this diagram shows the relationship between clock out and the first data bit. A 2-bit cycle delay is guaranteed when the MSB is out-
put from the transmitter.
FIGURE 14. 28 Parallel LVTTL Inputs Mapped to 4 Serial LVDS Outputs
Note: This output data pulse position works for both transmitter with 28 or 21 TTL inputs except the LVDS output bit mapping difference. All the information
in this diagram tells that the skew between the first data bit and clock output. Also 2-bit cycle delay is guaranteed when the MSB is output from transmitter.
FIGURE 15. 21 Parallel LVTTL Inputs Mapped to 3 Serial LVDS Outputs
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14
AC Loading and Waveforms (Continued)
FIGURE 16. Transmitter Output Pulse Bit Position
FIGURE 17. Receiver Input Bit Position
15
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AC Loading and Waveforms (Continued)
Note: t
is the budget for the cable skew and source clock skew plus ISI (Inter-Symbol Interference).
RSKM
Note: The minimum and maximum pulse position values are based on the bit position of each of the 7 bits within the LVDS data stream across PVT
(Process, Voltage Supply, and Temperature).
FIGURE 18. Receiver LVDS Input Skew Margin
Note: Test setup used considers no requirement for separation of RMS and deterministic jitter. Other hardware setup such as Wavecrest boxes can be used
if no M1 software is available, but the test methodology in Figure 20 should be followed.
FIGURE 19. Transmitter Clock Out Jitter Measurement Setup
Note: This jitter pattern is used to test the jitter response (Clock Out) of the device over the power supply range with worst jitter 3ns (cycle-to-cycle) clock
input. The specific test methodology is as follows:
•
•
Switching input data TxIn0 to TxIn20 at 0.5 MHz, and the input clock is shifted to left 3ns and to the right 3ns when data is HIGH.
The 3 ns cycle-to-cycle input jitter is the static phase error between the two clock sources. Jumping between two clock sources to simulate the worst
case of clock edge jump (3 ns) from graphical controllers. Cycle-to-cycle jitter at TxCLK out pin should be measured cross V range with 100mV noise
CC
(V noise frequency 2 MHz).
CC
FIGURE 20. Timing Diagram of Transmitter Clock Input with Jitter
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16
AC Loading and Waveforms (Continued)
Note: The 16-grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching
needed to produce groups of 16 vertical strips across the display.
FIGURE 21. “16 Grayscale” Test Pattern
FIGURE 22. Transmitter Phase Lock Loop Time
17
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Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD56
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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18
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