FM24C03UFEMT8 [FAIRCHILD]
I2C Serial EEPROM ; I2C串行EEPROM\n
| 型号： | FM24C03UFEMT8 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | I2C Serial EEPROM
|
| 文件： | 总14页 (文件大小：107K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 2000
FM24C02U/03U – 2K-Bit Standard 2-Wire Bus
Interface Serial EEPROM
General Description
Features
The FM24C02U/03U devices are 2048 bits of CMOS non-volatile
electrically erasable memory. These devices conform to all speci-
fications in the Standard IIC 2-wire protocol. They are designed to
minimize device pin count and simplify PC board layout require-
ments.
I Extended operating voltage 2.7V – 5.5V
I 400 KHz clock frequency (F) at 2.7V - 5.5V
I 200µA active current typical
10µA standby current typical
1µA standby current typical (L)
0.1µA standby current typical (LZ)
The upper half (upper 1Kbit) of the memory of the FM24C03U can
be write protected by connecting the WP pin to VCC. This section of
I IIC compatible interface
memory then becomes unalterable unless WP is switched to VSS
.
– Provides bi-directional data transfer protocol
This communications protocol uses CLOCK (SCL) and DATA
I/O (SDA) lines to synchronously clock data between the master
(forexampleamicroprocessor)andtheslaveEEPROMdevice(s).
The Standard IIC protocol allows for a maximum of 16K of
EEPROM memory which is supported by the Fairchild family in
2K, 4K, 8K, and 16K devices, allowing the user to configure the
memory as the application requires with any combination of
EEPROMs. In order to implement higher EEPROM memory
densities on the IIC bus, the Extended IIC protocol must be used.
(RefertotheFM24C32orFM24C65datasheetsformoreinforma-
tion.)
I Sixteen byte page write mode
– Minimizes total write time per byte
I Self timed write cycle
Typical write cycle time of 6ms
I Hardware Write Protect for upper half (FM24C03U only)
I Endurance: 1,000,000 data changes
I Data retention greater than 40 years
I Packages available: 8-pin DIP, 8-pin SO, and 8-pin TSSOP
I Available in three temperature ranges
- Commercial: 0° to +70°C
Fairchild EEPROMs are designed and tested for applications requir-
ing high endurance, high reliability and low power consumption.
- Extended (E): -40° to +85C
- Automotive (V): -40° to +125°C
Block Diagram
V
CC
V
SS
WP
H.V. GENERATION
TIMING &CONTROL
START
STOP
SDA
LOGIC
CONTROL
LOGIC
SLAVE ADDRESS
REGISTER &
2
E
PROM
COMPARATOR
XDEC
ARRAY
SCL
A2
A1
A0
WORD
ADDRESS
COUNTER
R/W
YDEC
CK
D
OUT
DATA REGISTER
D
IN
1
© 2000 Fairchild Semiconductor International
FM24C02U/03U Rev. A.3
www.fairchildsemi.com
Connection Diagrams
Dual-in-Line Package (N), SO Package (M8) and TSSOP Package (MT8)
A0
A1
A2
1
2
3
4
8
7
6
5
V
CC
NC
24C02
SCL
SDA
V
SS
See Package Number N08E, M08A and MTC08
Pin Names
A0,A1,A2
Device Address Inputs
Ground
VSS
SDA
SCL
Serial Data I/O
Serial Clock Input
No Connection
Power Supply
NC
VCC
Dual-in-Line Package (N), SO Package (M8) and TSSOP Package (MT8)
A0
A1
A2
1
2
3
4
8
7
6
5
V
CC
WP
24C03
SCL
SDA
V
SS
See Package Number N08E, M08A and MTC08
Pin Names
A0,A1,A2
Device Address Inputs
Ground
VSS
SDA
SCL
Serial Data I/O
Serial Clock input
Write Protect
WP
VCC
Power Supply
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FM24C02U/03U Rev. A.3
Ordering Information
FM 24 XX
C
U
F
LZ
E
XXX
Letter
Description
Package
N
8-pin DIP
M8
MT8
8-pin SOIC
8-pin TSSOP
Temp. Range
Blank
0 to 70°C
V
E
-40 to +125°C
-40 to +85°C
Voltage Operating Range
SCL Clock Frequency
Blank
L
LZ
4.5V to 5.5V
2.7V to 5.5V
2.7V to 5.5V and
<1µA Standby Current
Blank
F
100KHz
400KHz
Process
Density
U
Ultralite CS100UL
02
03
2K
2K with Write Protect
C
CMOS Technology
IIC
Interface
24
FM
Fairchild Non-Volatile
Memory
3
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FM24C02U/03U Rev. A.3
Product Specifications
Operating Conditions
Ambient Operating Temperature
Absolute Maximum Ratings
Ambient Storage Temperature
–65°C to +150°C
–0.3V to 6.5V
FM24C02U/03U
FM24C02UE/03UE
FM24C02UV/03UV
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
All Input or Output Voltages
with Respect to Ground
Lead Temperature
Positive Power Supply
FM24C02U/03U
(Soldering, 10 seconds)
+300°C
4.5V to 5.5V
2.7V to 5.5V
2.7V to 5.5V
ESD Rating
2000V min.
FM24C02UL/03UL
FM24C02ULZ/03ULZ
DC Electrical Characteristics (2.7V to 5.5V)
Symbol
Parameter
Test Conditions
Limits
Typ
Units
Max
Min
(Note 1)
ICCA
Active Power Supply Current fSCL = 400 KHz ("F" Version)
fSCL = 100 KHz
0.2
1.0
mA
ISB
(Note 3)
Standby Current
VIN = GND VCC = 2.7V - 5.5V
10
1
0.1
50
10
1
µA
µA
µA
or VCC
VCC = 2.7V - 5.5V (L)
VCC = 2.7V - 4.5V (LZ)
ILI
ILO
Input Leakage Current
Output Leakage Current
Input Low Voltage
VIN = GND to VCC
0.1
0.1
1
1
µA
µA
V
VOUT = GND to VCC
VIL
VIH
VOL
–0.3
VCC x 0.3
VCC + 0.5
0.4
Input High Voltage
VCC x 0.7
V
Output Low Voltage
IOL = 3 mA
V
Capacitance TA = +25°C, f = 100/400 KHz, VCC = 5V (Note 2)
Symbol
CI/O
Test
Conditions
VI/O = 0V
Max Units
Input/Output Capacitance (SDA)
8
pF
CIN
Input Capacitance (A0, A1, A2, SCL)
VIN = 0V
6
pF
Note 1: Typical values are TA = 25°C and nominal supply voltage of 5V for 4.5V-5.5V operation and at 3V for 2.7V-4.5V operation.
Note 2: This parameter is periodically sampled and not 100% tested.
Note 3: The "L" and "LZ" versions can be operated in the 2.7V to 5.5V VCC range. However, for a standby current (ISB) of 1µA, the VCC should be within 2.7V to 4.5V.
4
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FM24C02U/03U Rev. A.3
AC Testing Input/Output Waveforms
AC Test Conditions
Input Pulse Levels
VCC x 0.1 to VCC x 0.9
10 ns
0.9VCC
0.7VCC
0.3VCC
Input Rise and Fall Times
0.1VCC
Input & Output Timing Levels VCC x 0.3 to VCC x 0.7
Output Load 1 TTL Gate and CL = 100 pF
Read and Write Cycle Limits (Standard and Low VCC Range 2.7V - 5.5V)
Symbol
Parameter
100 KHz
400 KHz
Units
Min
Max
Min
Max
fSCL
TI
SCL Clock Frequency
100
100
3.5
400
KHz
ns
Noise Suppression Time Constant at
SCL, SDA Inputs (Minimum VIN
Pulse width)
50
tAA
SCL Low to SDA Data Out Valid
0.3
4.7
0.1
1.3
0.9
µs
µs
tBUF
Time the Bus Must Be Free before
a New Transmission Can Start
tHD:STA
tLOW
Start Condition Hold Time
Clock Low Period
4.0
4.7
4.0
4.7
0.6
1.5
0.6
0.6
µs
µs
µs
µs
tHIGH
Clock High Period
tSU:STA
Start Condition Setup Time
(for a Repeated Start Condition)
tHD:DAT
tSU:DAT
tR
Data in Hold Time
0
0
ns
ns
µs
ns
µs
ns
Data in Setup Time
250
100
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
1
0.3
tF
300
300
tSU:STO
tDH
4.7
0.6
50
300
tWR
(Note 4)
Write Cycle Time
4.5V to 5.5V VCC
2.7V to 4.5V VCC
10
15
10
15
ms
Note 4: The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the
FM24C02U/03U bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address. Refer
"Write Cycle Timing" diagram.
Bus Timing
t
t
R
F
t
HIGH
t
t
LOW
LOW
SCL
t
SU:STO
t
t
t
SU:DAT
SU:STA
HD:DAT
t
HD:STA
SDA
IN
t
BUF
t
t
AA
DH
SDA
OUT
5
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FM24C02U/03U Rev. A.3
Write Cycle Timing
SCL
SDA
8th BIT
WORD n
ACK
t
WR
STOP
START
CONDITION
CONDITION
Note:
The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle.
Typical System Configuration
V
V
CC
CC
SDA
SCL
Master
Transmitter/
Receiver
Slave
Transmitter/
Receiver
Master
Transmitter/
Receiver
Master
Transmitter
Slave
Receiver
Note:
Due to open drain configuration of SDA and SCL, a bus-level pull-up resistor is called for, (typical value = 4.7kΩ)
Example of 16K of Memory on 2-Wire Bus
Note:
The SDA pull-up resistor is required due to the open-drain/open collector output of IIC bus devices.
The SCL pull-up resistor is recommended because of the normal SCL line inactive 'high' state.
It is recommended that the total line capacitance be less than 400pF
V
V
CC
CC
SDA
SCL
V
V
V
V
CC
CC
CC
CC
24C02/03
24C02/03
24C04/05
24C08/09
A0 A1 A2
V
A0 A1 A2
V
A1 A2
V
A2
V
SS
SS
SS
SS
To To To
To To To
To To
To
V
V
V
V
V
V
V
V
V
SS SS SS
CC SS SS
CC SS
CC
Device
Address Pins Present
A1
Memory Size # of Page
Blocks
A0
Yes
No
A2
Yes
Yes
Yes
No
FM24C02U/03U
FM24C04U/05U
FM24C08U/09U
FM24C16U/17U
Yes
Yes
No
2048 Bits
4096 Bits
8192 Bits
16,384 Bits
1
2
4
8
No
No
No
6
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FM24C02U/03U Rev. A.3
Acknowledge
Background Information (IIC Bus)
Acknowledge is an active LOW pulse on the SDA line driven by an
addressed receiver to the addressing transmitter to indicate
receipt of 8-bits of data. The receiver provides an ACK pulse for
every 8-bits of data received. This handshake mechanism is done
as follows: After transmitting 8-bits of data, the transmitter re-
leases the SDA line and waits for the ACK pulse. The addressed
receiver, if present, drives the ACK pulse on the SDA line during
the 9th clock and releases the SDA line back (to the transmitter).
Refer Figure 3.
IIC bus allows synchronous bi-directional communication be-
tween a TRANSMITTER and a RECEIVER using a Clock signal
(SCL) and a Data signal (SDA). Additionally there are up to three
Address signals (A2, A1 and A0) which collectively serve as "chip
select signal" to a device (example EEPROM) on the IIC bus.
All communication on the IIC bus must be started with a valid
START condition (by a MASTER), followed by transmittal (by the
MASTER) of byte(s) of information (Address/Data). For every byte
ofinformationreceived, theaddressedRECEIVERprovidesavalid
ACKNOWLEDGE pulse to further continue the communication
unless the RECEIVER intends to discontinue the communication.
Depending on the direction of transfer (Write or Read), the RE-
CEIVER can be a SLAVE or the MASTER. A typical IIC communi-
cation concludes with a STOP condition (by the MASTER).
Array Address
Array address is an 8-bit information containing the address of a
memory location to be selected within a page block of the device.
16K bit Addressing Limitation:
Addressing an EEPROM memory location involves sending a
command string with the following information:
Standard IIC specification limits the maximum size of EEPROM
memory on the bus to 16K bits. This limitation is due to the
addressingprotocolimplementedwhichconsistsofthe8-bitSlave
Address and an additional 8-bit field called Array Address. This
Array Address selects 1 out of 256 locations (28=256). Since the
data format of IIC specification is 8-bit wide, a total of 256 x 8 =
2048 = 2K bits now becomes addressable by this 8-bit Array
Address. These 2K bits are typically referred as a “Page Block”.
Combining this 8-bit Array Address with the 3-bit Device/Page
address (part of Slave Address) allows a maximum of 8 pages
(23=8) of memory that can be addressed. Since each page is 2K
bits in size, 8 x 2K bits = 16K bits is the maximum size of memory
that is addressable on the Standard IIC bus. This 16Kb of memory
can be in the form of a single 16Kb EEPROM device or multiple
EEPROMs of varying density (in 2Kb multiples) to a maximum
total of 16Kb. To address the needs of systems that require more
than 16Kb on the IIC bus, a different specification called “Ex-
tended IIC Specification” is used.
[DEVICE TYPE]—[DEVICE/PAGE BLOCK SELECTION]—[R/W
BIT]—{acknowledge pulse}—[ARRAY ADDRESS]
Slave Address
Slave Address is an 8-bit information consisting of a Device type
field (4bits), Device/Page block selection field (3bits) and Read/
Write bit (1bit).
Slave Address Format
Device Type
Identifier
Device/Page Block
Selection
1
0
1
0
A2
A1
A0 R/W (LSB)
Device Type
DEFINITIONS
IIC bus is designed to support a variety of devices such as RAMs,
EPROMs etc., along with EEPROMS. Hence to properly identify
various devices on the IIC bus, a 4-bit “Device Type” identifier
stringisused. ForEEPROMS, this4-bitstringis1-0-1-0. EveryIIC
device on the bus internally compares this 4-bit string to its own
“Device Type” string to ensure proper device selection.
WORD
PAGE
8 bits (byte) of data
16 sequential byte locations
starting at a 16-byte address
boundary, that may be pro-
grammed during a "page write"
programming cycle
Device/Page Block Selection
PAGE BLOCK
2048 (2K) bits organized into 16
pages of addressable memory. (8
bits) x (16 bytes) x (16 pages) =
2048 bits
Whenmultipledevicesofthesametype(e.g.multipleEEPROMS)
are present on the IIC bus, then the A2, A1 and A0 address
information bits are also used as part of the Slave Address. Every
IICdeviceonthebusinternallycomparesthis3-bitstringtoitsown
physical configuration (A2, A1 and A0 pins) to ensure proper
device selection. This comparison is in addition to the “Device
Type” comparison. In addition to selecting an EEPROM, these 3
bits are also used to select a “page block” within the selected
EEPROM. Each page block is 2Kbit (256Bytes) in size. Depend-
ing on the density, an EEPROM can contain from a minimum of 1
to a maximum of 8 page blocks (in multiples of 2) and selection of
a page block within a device is by using A2, A1 and A0 bits.
MASTER
Any IIC device CONTROLLING the
transfer of data (such as a
microprocessor)
SLAVE
Device being controlled
(EEPROMs are always considered
Slaves)
TRANSMITTER
RECEIVER
Device currently SENDING data on
the bus (may be either a Master or
Slave).
Read/Write Bit
Device currently RECEIVING data
on the bus (Master or Slave)
Last bit of the Slave Address indicates if the intended access is
Read or Write. If the bit is "1," then the access is Read, whereas
if the bit is "0," then the access is Write.
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FM24C02U/03U Rev. A.3
Pin Descriptions
Device Operation
The FM24C02U/03U supports a bi-directional bus oriented proto-
col. The protocol defines any device that sends data onto the bus
as a transmitter and the receiving device as the receiver. The
device controlling the transfer is the master and the device that is
controlled is the slave. The master will always initiate data
transfers and provide the clock for both transmit and receive
operations. Therefore, the FM24C02U/03U will be considered a
slave in all applications.
Serial Clock (SCL)
The SCL input is used to clock all data into and out of the device.
Serial Data (SDA)
SDA is a bi-directional pin used to transfer data into and out of the
device. It is an open drain output and may be wire–ORed with any
number of open drain or open collector outputs.
Write Protect (WP) (FM24C03U Only)
Clock and Data Conventions
If tied to V , PROGRAM operations onto the upper half (upper
CC
Data states on the SDA line can change only during SCL LOW.
SDA state changes during SCL HIGH are reserved for indicating
start and stop conditions. Refer to Figure 1 and Figure 2 on next
page.
1Kbits) of the memory will not be executed. READ operations are
possible. If tied to V , normal operation is enabled, READ/
SS
WRITE over the entire memory is possible.
Start Condition
Thisfeatureallowstheusertoassigntheupperhalfofthememory
as ROM which can be protected against accidental programming.
When write is disabled, slave address and word address will be
acknowledged but data will not be acknowledged.
All commands are preceded by the start condition, which is a
HIGH to LOW transition of SDA when SCL is HIGH. The
FM24C02U/03UcontinuouslymonitorstheSDAandSCLlinesfor
the start condition and will not respond to any command until this
condition has been met.
This pin has an internal pull-down circuit. However, on systems
where write protection is not required it is recommended that this
pin is tied to VSS
.
Stop Condition
Device Selection Inputs A2, A1 and A0 (as
appropriate)
All communications are terminated by a stop condition, which is a
LOW to HIGH transition of SDA when SCL is HIGH. The stop
condition is also used by the FM24C02U/03U to place the device
in the standby power mode, except when a Write operation is
being executed, in which case a second stop condition is required
after tWR period, to place the device in standby mode.
These inputs collectively serve as “chip select” signal to an
EEPROM when multiple EEPROMs are present on the same IIC
bus. Hence these inputs, if present, should be connected to VCC
orVSS inauniquemannertoallowproperselectionofanEEPROM
amongst multiple EEPROMs. During a typical addressing se-
quence, every EEPROM on the IIC bus compares the configura-
tion of these inputs to the respective 3 bit “Device/Page block
selection” information (part of slave address) to determine a valid
selection. For e.g. if the 3 bit “Device/Page block selection” is 1-
0-1, then the EEPROM whose “Device Selection inputs” (A2, A1
and A0) are connected to VCC-VSS-VCC respectively, is selected.
Depending on the density, only appropriate numbers of “Device
Selection inputs” are provided on an EEPROM. For every “Device
selection input” that is not present on the device, the correspond-
ing bit in the “Device/Page block selection” field is used to select
a “Page Block” within the device instead of the device itself.
Following table illustrates the above:
EEPROM
Density
2k bit
Number of
Page Blocks
Device Selection Inputs
Address Bits
Selecting Page Block
None
Provided
1
2
4
8
A0
—
—
—
A1
A1
—
A2
A2
A2
—
4k bit
A0
8k bit
A0 and A1
16k bit
—
A0, A1 and A2
Note that even when just one EEPROM present on the IIC bus,
these pins should be tied to VCC or VSS to ensure proper termina-
tion.
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FM24C02U/03U Rev. A.3
Data Validity (Figure 1)
SCL
SDA
DATA STABLE
DATA
CHANGE
Start and Stop Definition (Figure 2)
SCL
SDA
START
STOP
CONDITION
CONDITION
Acknowledge Response from Receiver (Figure 3)
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM
TRANSMITTER
t
DH
t
AA
DATA OUTPUT
FROM
RECEIVER
START
CONDITION
ACKNOWLEDGE
PULSE
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FM24C02U/03U Rev. A.3
Refer the following table for Slave Addresses string details:
Acknowledge
The FM24C02U/03U device will always respond with an acknowl-
edge after recognition of a start condition and its slave address. If
both the device and a write operation have been selected, the
FM24C02U/03U will respond with an acknowledge after the
receipt of each subsequent eight bit byte.
Device
A0 A1 A2 Page Page Block
Blocks Addresses
FM24C02U/03U
A
A
A
1
(None)
A: Refers to a hardware configured Device Address pin.
In the read mode the FM24C02U/03U slave will transmit eight bits
of data, release the SDA line and monitor the line for an acknowl-
edge. If an acknowledge is detected, FM24C02U/03U will continue
totransmitdata.Ifanacknowledgeisnotdetected,FM24C02U/03U
will terminate further data transmissions and await the stop condi-
tion to return to the standby power mode.
All IIC EEPROMs use an internal protocol that defines a PAGE
BLOCK size of 2K bits (for Word addresses 0x00 through 0xFF).
Therefore, address bits A0, A1, or A2 (if designated 'P') are used
to access a PAGE BLOCK in conjunction with the Word address
used to access any individual data byte.
The last bit of the slave address defines whether a write or read
condition is requested by the master. A '1' indicates that a read
operation is to be executed, and a '0' initiates the write mode.
Device Addressing
Following a start condition the master must output the address of
the slave it is accessing. The most significant four bits of the slave
address are those of the device type identifier. This is fixed as
1010 for all EEPROM devices.
A simple review: After the FM24C02U/03U recognizes the start
condition, the devices interfaced to the IIC bus wait for a slave
address to be transmitted over the SDA line. If the transmitted
slave address matches an address of one of the devices, the
designated slave pulls the SDA line LOW with an acknowledge
signal and awaits further transmissions.
Device Type
Identifier
Device
Address
1
0
1
0
A2
A1
A0 R/W (LSB)
24C02/03
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FM24C02U/03U Rev. A.3
Write Operations
Page Write is initiated in the same manner as the Byte Write
operation; but instead of terminating the cycle after transmitting
the first data byte, the master can further transmit up to 15 more
bytes. After the receipt of each byte, FM24C02U/03U will respond
withanacknowledgepulse,incrementtheinternaladdresscounter
to the next address, and is ready to accept the next data. If the
master should transmit more than sixteen bytes prior to generat-
ing the STOP condition, the address counter will “roll over” and
previously written data will be overwritten. As with the Byte Write
operation, all inputs are disabled until completion of the internal
write cycle. Refer to Figure 5 for the address, acknowledge, and
data transfer sequence.
BYTE WRITE
For a write operation, a second address field is required which is a
word address that is comprised of eight bits and provides access to
any one of the 256 bytes in the selected page of memory. Upon
receipt of the byte address, the FM24C02U/03U responds with an
acknowledge and waits for the next eight bits of data, again,
responding with an acknowledge. The master then terminates the
transferbygeneratingastopconditionatwhichtimetheFM24C02U/
03Ubeginstheinternalwritecycletothenonvolatilememory.While
the internal write cycle is in progress, the FM24C02U/03U inputs
are disabled, and the device will not respond to any requests from
the master for the duration of tWR. Refer to Figure 4 for the address,
acknowledge, and data transfer sequence.
Acknowledge Polling
Once the stop condition is issued to indicate the end of the host’s
write operation, the FM24C02U/03U initiates the internal write
cycle. ACK polling can be initiated immediately. This involves
issuing thestart condition followedbythe slave addressfor a write
operation. If the FM24C02U/03U is still busy with the write
operation, no ACK will be returned. If the FM24C02U/03U has
completed the write operation, an ACK will be returned and the
host can then proceed with the next read or write operation.
PAGE WRITE
To minimize write cycle time, FM24C02U/03U offer Page Write
feature, by which, up to a maximum of 16 contiguous byte
locations can be programmed all at once (instead of 16 individual
byte writes). To facilitate this feature, the memory array is orga-
nized in terms of “Pages.” A Page consists of 16 contiguous byte
locations starting at every 16-Byte address boundary (for ex-
ample, starting at array address 0x00, 0x10, 0x20 etc.). Page
Write operation limits access to byte locations within a page. In
other words a single Page Write operation will not cross over to
locationsonanotherpagebutwill“rollover”tothebeginningofthe
page whenever end of Page is reached and additional locations
are continued to be accessed. A Page Write operation can be
initiated to begin at any location within a page (starting address of
the Page Write operation need not be the starting address of a
Page).
Write Protection (FM24C03U Only)
Programmingoftheupperhalf(upper1Kbit)ofthememorywillnot
take place if the WP pin of the FM24C03U is connected to V
.
CC
The FM24C03U will respond to slave and byte addresses; but if
the memory accessed is write protected by the WP pin, the
FM24C03U will not generate an acknowledge after the first byte
of data has been received. Thus, the program cycle will not be
started when the stop condition is asserted.
Byte Write (Figure 4)
S
T
A
R
T
S
T
O
P
SLAVE
ADDRESS
WORD
ADDRESS
Bus Activity:
Master
DATA
SDA Line
A
C
K
A
C
K
A
C
K
Bus Activity:
EEPROM
Page Write (Figure 5)
S
T
A
R
T
S
T
O
P
SLAVE
ADDRESS
Bus Activity:
Master
WORD ADDRESS (n)
DATA n
DATA n + 1
DATA n + 15
SDA Line
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Bus Activity:
EEPROM
11
www.fairchildsemi.com
FM24C02U/03U Rev. A.3
immediately issues another start condition and the slave address
with the R/W bit set to one. This will be followed by an acknowl-
edgefromtheFM24C02U/03Uandthenbytheeightbitword. The
master will not acknowledge the transfer but does generate the
stop condition, and therefore the FM24C02U/03U discontinues
transmission. RefertoFigure7fortheaddress, acknowledge, and
data transfer sequence.
Read Operations
Read operations are initiated in the same manner as write
operations, with the exception that the R/W bit of the slave
address is set to a one. There are three basic read operations:
current address read, random read, and sequential read.
Current Address Read
Sequential Read
Internally the FM24C02U/03U contains an address counter that
maintains the address of the last byte accessed, incremented by
one. Therefore, if the last access (either a read or write) was to
address n, the next read operation would access data from
address n + 1. Upon receipt of the slave address with R/W set to
one, the FM24C02U/03U issues an acknowledge and transmits
the eight bit word. The master will not acknowledge the transfer
butdoesgenerateastopcondition,andthereforetheFM24C02U/
03U discontinues transmission. Refer to Figure 6 for the se-
quence of address, acknowledge and data transfer.
Sequential reads can be initiated as either a current address read
or random access read. The first word is transmitted in the same
manner as the other read modes; however, the master now
responds with an acknowledge, indicating it requires additional
data. The FM24C02U/03U continues to output data for each
acknowledge received. The read operation is terminated by the
master not responding with an acknowledge or by generating a
stop condition.
The data output is sequential with the data from address n
followed by the data from n + 1. The address counter for read
operations increments all word address bits, allowing the entire
memory contents to be serially read during one operation. After
the entire memory has been read, the counter "rolls over" to the
beginning of the memory. FM24C02U/03U continues to output
data for each acknowledge received. Refer to Figure 8 for the
address, acknowledge, and data transfer sequence.
Random Read
Randomreadoperationsallowthemastertoaccessanymemory
location in a random manner. Prior to issuing the slave address
with the R/W bit set to one, the master must first perform a
“dummy” write operation. The master issues the start condition,
slave address with the R/W bit set to zero and then the byte
address is read. After the byte address acknowledge, the master
Current Address Read (Figure 6)
S
T
S
T
O
P
SLAVE
ADDRESS
Bus Activity:
Master
A
R
T
1 0 1
0
1
SDA Line
A
C
K
NO
A
C
K
Bus Activity:
EEPROM
DATA
Random Read (Figure 7)
S
T
A
R
T
S
S
T
O
P
T
A
R
T
SLAVE
ADDRESS
WORD
ADDRESS
SLAVE
ADDRESS
Bus Activity:
Master
SDA Line
A
C
K
A
C
K
A
C
K
NO
DATA n
A
C
K
Bus Activity:
EEPROM
Sequential Read (Figure 8)
S
T
O
P
A
C
K
A
C
K
A
C
K
Bus Activity:
Slave
Master
Address
SDA Line
A
C
K
NO
DATA n +1
DATA n +1
DATA n + 2
DATA n + x
A
C
K
Bus Activity:
EEPROM
12
www.fairchildsemi.com
FM24C02U/03U Rev. A.3
Physical Dimensions inches (millimeters) unless otherwise noted
0.189 - 0.197
(4.800 - 5.004)
8
7
6
3
5
4
0.228 - 0.244
(5.791 - 6.198)
1
2
Lead #1
IDENT
0.150 - 0.157
(3.810 - 3.988)
0.053 - 0.069
(1.346 - 1.753)
0.010 - 0.020
(0.254 - 0.508)
0.004 - 0.010
(0.102 - 0.254)
x 45¡
8¡ Max, Typ.
All leads
Seating
Plane
0.004
(0.102)
All lead tips
0.0075 - 0.0098
(0.190 - 0.249)
Typ. All Leads
0.014
(0.356)
0.016 - 0.050
(0.406 - 1.270)
Typ. All Leads
0.050
(1.270)
Typ
0.014 - 0.020
Typ.
(0.356 - 0.508)
8-Pin Molded Small Outline Package (M8)
Package Number M08A
0.114 - 0.122
(2.90 - 3.10)
8
5
(7.72) Typ
(4.16) Typ
0.169 - 0.177
(4.30 - 4.50)
0.246 - 0.256
(6.25 - 6.5)
(1.78) Typ
(0.42) Typ
0.123 - 0.128
(3.13 - 3.30)
(0.65) Typ
Land pattern recommendation
1
4
Pin #1 IDENT
0.0433
Max
(1.1)
0.0035 - 0.0079
See detail A
0.002 - 0.006
(0.05 - 0.15)
0.0256 (0.65)
Typ.
Gage
plane
0.0075 - 0.0118
(0.19 - 0.30)
0¡-8¡
DETAIL A
Typ. Scale: 40X
0.0075 - 0.0098
(0.19 - 0.25)
0.020 - 0.028
(0.50 - 0.70)
Seating
plane
Notes: Unless otherwise specified
1. Reference JEDEC registration MO153. Variation AA. Dated 7/93
8-Pin Molded Thin Shrink Small Outline Package (MT8)
Package Number MTC08
13
www.fairchildsemi.com
FM24C02U/03U Rev. A.3
Physical Dimensions inches (millimeters) unless otherwise noted
0.373 - 0.400
(9.474 - 10.16)
0.090
(2.286)
8
7
0.032 0.005
(0.813 0.127)
RAD
8
7
6
3
5
4
0.092
(2.337)
DIA
0.250 - 0.005
(6.35 0.127)
Pin #1
IDENT
+
Pin #1 IDENT
1
Option 1
1
2
Option 2
0.280
MIN
0.040
(1.016)
Typ.
(7.112)
0.030
0.145 - 0.200
(3.683 - 5.080)
0.039
(0.991)
MAX
(0.762)
0.300 - 0.320
(7.62 - 8.128)
20° 1°
0.130 0.005
(3.302 0.127)
0.125 - 0.140
95° 5°
(3.175 - 3.556)
0.065
(1.651)
0.125
(3.175)
DIA
0.020
90° 4°
Typ
0.009 - 0.015
(0.229 - 0.381)
(0.508)
Min
0.018 0.003
(0.457 0.076)
NOM
+0.040
-0.015
0.325
0.100 0.010
+1.016
-0.381
8.255
(2.540 0.254)
0.045 0.015
(1.143 0.381)
0.060
(1.524)
0.050
(1.270)
Molded Dual-In-Line Package (N)
Package Number N08E
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written
approval of the President of Fairchild Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which,
(a)areintendedforsurgicalimplantintothebody,or(b)support
or sustain life, and whose failure to perform, when properly
used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant
injury to the user.
2. A critical component is any component of a life support device
or system whose failure to perform can be reasonably ex-
pected to cause the failure of the life support device or system,
or to affect its safety or effectiveness.
Fairchild Semiconductor
Americas
Fairchild Semiconductor
Europe
Fairchild Semiconductor
Hong Kong
Fairchild Semiconductor
Japan Ltd.
Customer Response Center
Tel. 1-888-522-5372
Fax:
Tel:
Tel:
Tel:
Tel:
+44 (0) 1793-856858
8/F, Room 808, Empire Centre
68 Mody Road, Tsimshatsui East
Kowloon. Hong Kong
Tel; +852-2722-8338
Fax: +852-2722-8383
4F, Natsume Bldg.
Deutsch
English
Français
Italiano
+49 (0) 8141-6102-0
+44 (0) 1793-856856
+33 (0) 1-6930-3696
+39 (0) 2-249111-1
2-18-6, Yushima, Bunkyo-ku
Tokyo, 113-0034 Japan
Tel: 81-3-3818-8840
Fax: 81-3-3818-8841
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
14
www.fairchildsemi.com
FM24C02U/03U Rev. A.3
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