FM24C256FLZYYX [FAIRCHILD]

256 KBit 2-Wire Bus Interface Serial EEPROM with Write Protect; 256 Kbit的2线总线接口的串行EEPROM，带有写保护


型号：	FM24C256FLZYYX
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	256 KBit 2-Wire Bus Interface Serial EEPROM with Write Protect 256 Kbit的2线总线接口的串行EEPROM，带有写保护可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件：	总12页 (文件大小：91K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

June 2000

FM24C256

256 KBit 2-Wire Bus Interface

Serial EEPROM with Write Protect

General Description

Features

The FM24C256/C256L/C256LZ devices are 256 Kbits CMOS

nonvolatile electrically erasable memory. These devices offer the

designer different low voltage and low power options. They

conform to all requirements in the Extended IIC 2-wire protocol.

Furthermore, they are designed to minimize device pin count and

simplify PC board layout requirements.

I Extended Operating Voltages

— C256: 4.5V - 5.5V

— C256L: 2.7V - 5.5V

— C256LZ: 2.7V - 5.5V

I Low Power CMOS

— 1mA active current typical

— C256/C256L: 10µA standby current typical

— C256LZ: less than 1µA standby current

The entire memory array can be write disabled (Write Protection)

by connecting the WP pin to V_CC

I 2-wire IIC serial interface

Functional address lines allow up to eight devices on the same

bus, for up to a total of 2 Mbit address space.

I 64 byte page write mode

I Max write cycle time of 6ms byte/page

I 40 years data retention

The IIC communication protocol uses CLOCK (SCL) and DATA

I/O (SDA) lines to synchronously clock data between the master

(forexampleamicroprocessor)andtheslaveEEPROMdevice(s).

I Endurance: 100,000 data changes

I Hardware write protect for entire array

I Schmitt trigger inputs for noise suppression

I Electrostatic discharge protection > 4000V

Fairchild EEPROMs are designed and tested for applications

requiring high endurance, high reliability, and low power con-

sumption.

I 8-pin DIP and 8-pin SO (150 mil) packages. Contact factory

for CSP package availability

Block Diagram

WRITE

LOCKOUT

H.V. GENERATION

TIMING &CONTROL

START CYCLE

START

STOP

SDA

LOGIC

CONTROL

LOGIC

SLAVE ADDRESS

COMPARATOR

PROM

ARRAY

XDEC

SCL

LOAD

INC

WORD

ADDRESS

COUNTER

R/W

YDEC

OUT

DATA REGISTER

DS800023-1

www.fairchildsemi.com

FM24C256 rev. B.3

Connection Diagram

Dual-In-Line Package (N)

and 8-Pin SO Package (M8)

FM24C256

SCL

SDA

DS800023-2

Top View

See Package Number N08E and M08A

Pin Names

A0, A1, A2

V_SS

Device Address Input

Ground

SDA

Data I/O

SCL

Clock Input

Write Protect

Power Supply

V_CC

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FM24C256 rev. B.3

Ordering Information

Commercial Temperature Range: 0° to +70°C

Part Number

FM24C256YYX

Clock Frequency

V_CC

Standby Current

4.5V - 5.5V

2.7V - 5.5V

10µA typical

FM24C256LYYX

FM24C256LZYYX

FM24C256FYYX

FM24C256FLYYX

FM24C256FLZYYX

100KHz

1µA max

4.5V - 5.5V

2.7V - 5.5V

10µA typical

400KHz

1µA max

Industrial Temperature Range: -40° to +85°C

Part Number

FM24C256EYYX

Clock Frequency

V_CC

Standby Current

4.5V - 5.5V

2.7V - 5.5V

10µA typical

FM24C256LEYYX

FM24C256LZEYYX

FM24C256FEYYX

FM24C256FLEYYX

FM24C256FLZEYYX

100KHz

1µA max

4.5V - 5.5V

2.7V - 5.5V

10µA typical

400KHz

1µA max

Letter Description

Blank

Tube

Tape and Reel

Package

8-pin DIP

8-pin SO8

Temp. Range

Blank

0 to 70°C

-40 to +85°C

Voltage Operating Range

Blank

4.5V to 5.5V

2.7V to 5.5V

2.7V to 5.5V and

<1µA Standby Current

SCL Clock Frequency

Density

Blank

100KHz

400KHz

256

256K with write protect

CMOS

Interface

IIC - 2 Wire

Fairchild Non-Volatile

Memory

www.fairchildsemi.com

FM24C256 rev. B.3

Absolute Maximum Ratings

Operating Conditions

Ambient Storage Temperature

–65°C to +150°C

Ambient Operating Temperature

FM24C256/L/LZ

0°C to +70°C

All Input or Output Voltages

with Respect to Ground

FM24C256F/FL/FLZ

FM24C256E/LE/LZE

6.5V to –0.3V

-40°C to +85°C

FM24C256FE/FLE/FLZE

Lead Temperature

(Soldering, 10 seconds)

+300°C

Positive Power Supply

FM24C256/E

4.5V to 5.5V

2.7V to 5.5V

2.7V to 4.5V

ESD Rating

4000V min.

FM24C256F/FE

FM24C256L/LZ

FM24C256FL/FLZ

FM24C256LE/LZE

FM24C256FLE/FLZE

Standard V_CC(4.5V to 5.5V) DC Electrical Characteristics

Symbol

Parameter

Test Conditions

Limits

Typ

Units

Min

Max

I_CCA

Active Power Supply Current

f_SCL= 100 kHz

f_SCL= 400 kHz

0.5

1.0

I_SB

I_LI

Standby Current

V_IN= GND or V_CC

V_IN= GND to V_CC

V_OUT= GND to V_CC

0.1

µA

Input Leakage Current

Output Leakage Current

Input Low Voltage

I_LO

V_IL

V_IH

V_OL

–0.3

V_CCx 0.3

V_CC+ 0.5

0.4

Input High Voltage

Output Low Voltage

V_CCx 0.7

I_OL= 2.1 mA

Low V_CC(2.7V to 5.5V) DC Electrical Characteristics

Symbol

Parameter

Test Conditions

Limits

Typ

Units

Min

Max

I_CCA

Active Power Supply Current

f_SCL= 100 kHz

0.5

1.0

f_SCL= 400 kHz

I_SB

(Note 1)

Standby Current for L

Standby Current for LZ

V_IN= GND or V_CC= 4.5V - 5.5V

V_IN= GND or V_CC= 2.7V - 4.5V

V_IN= GND or V_CC= 4.5V - 5.5V

V_IN= GND or V_CC= 2.7V - 4.5V

0.1

µA

I_LI

I_LO

Input Leakage Current

Output Leakage Current

Input Low Voltage

V_IN= GND to V_CC

0.1

µA

V_OUT= GND to V_CC

V_IL

V_IH

V_OL

–0.3

V_CCx 0.3

V_CC+ 0.5

0.4

Input High Voltage

V_CCx 0.7

Output Low Voltage

I_OL= 2.1 mA

Capacitance T_A= +25°C, f = 100/400 KHz, V_CC= 5V

Symbol

C_I/O

Test

Conditions

V_I/O= 0V

Max Units

Input/Output Capacitance (SDA)

Input Capacitance (A0, A1, A2, SCL)

C_IN

V_IN= 0V

Note 1: Typical values are for T = 25°C and nominal supply voltage (5V).

www.fairchildsemi.com

FM24C256 rev. B.3

AC Conditions of Test

Input Pulse Levels

V_CCx 0.1 to V_CCx 0.9

Input Rise and Fall Times

10 ns

Input & Output Timing Levels V_CCx 0.5

Output Load

1 TTL Gate and C_L= 100 pF

Read and Write Cycle Limits (Standard and Low V_CCRange - 2.7V-5.5V)

Symbol

Parameter

100 kHz

Max

400 kHz

Max

Units

kHz

Min

f_SCL

T_I

SCL Clock Frequency

100

3.5

400

Noise Suppression Time Constant at

SCL, SDA Inputs (Minimum V_IN

Pulse width)

t_AA

SCL Low to SDA Data Out Valid

0.3

4.7

0.3

1.3

1.2

µs

t_BUF

Time the Bus Must Be Free before

a New Transmission Can Start

t_HD:STA

t_LOW

Start Condition Hold Time

Clock Low Period

4.0

4.7

4.0

4.7

0.6

1.5

0.6

µs

t_HIGH

Clock High Period

t_SU:STA

Start Condition Setup Time

(for a Repeated Start Condition)

t_HD:DAT

t_SU:DAT

t_R

Data in Hold Time

µs

Data in Setup Time

250

100

SDA and SCL Rise Time

SDA and SCL Fall Time

Stop Condition Setup Time

Data Out Hold Time

Write Cycle Time

0.3

t_F

300

t_SU:STO

t_DH

4.7

0.6

100

t_WR

(Note 2)

Note 2: The write cycle time (t_WR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the

FM24C256 bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address

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FM24C256 rev. B.3

Bus Timing

HIGH

LOW

SCL

SU:STO

SU:DAT

SU:STA

HD:DAT

HD:STA

SDA

BUF

SDA

OUT

Note 3: SCL = Serial Clock Data

DS800023-3

SDA = Serial Data I/O

BACKGROUND INFORMATION (IIC Bus)

SERIAL DATA (SDA)

The IIC bus allows synchronous bidirectional communication be-

tween Transmitter/Receiver using the SCL (clock) and SDA (Data

I/O) lines. All communication must be started with a valid START

condition, concluded with a STOP condition and acknowledged by

the Receiver with an ACKNOWLEDGE condition.

SDA is a bidirectional pin used to transfer data to and from the

device. It is an open drain output and may be wire-ORed with any

number of open drain or open collector outputs.

Device Address Inputs (A0, A1, A2)

Device address pins A0, A1, and A2 are connected to V_CCor V_SS

to configure the EEPROM address for multiple device configura-

tion. A total of eight different devices can be attached to the same

SDA bus.

In addition, since the IIC bus is designed to support other devices

such as RAM, EPROM, etc., the device type identifier string, or

control byte, must follow the START condition. For EEPROMs, the

first 4-bit of the control byte is 1010 binary for READ and WRITE

operations. This is then followed by the device selection bits A2, A1

and A0, and acts as the three most significant bits of the word

address.The final bit in the control byte determines the type of

operation performed (READ/WRITE). A "1" signifies a READ while

a"0"signifiesaWRITE.Thecontrolbyteisthenfollowedbytwobytes

that define the word address, which is then followed by the data byte.

Write Protection (WP)

If WP is tied to V_CC, program WRITE operations onto the entire

array of the memory will not be executed. READ operations are

always available.

If WP is tied to V_SSor left floating (unconnected), normal memory

operation is enabled for READ/WRITE over the entire 256K bit

memory array.

The EEPROMs on the IIC bus may be configured in any manner

required, providing the total memory addressed does not exceed

512Kbits(64Kbytes). EEPROMmemoryaddressingiscontrolled

by hardware configuring the A2, A1, and A0 pins (Device Address

pins) with pull-up or pull-down resistors. ALL UNUSED PINS

MUST BE GROUNDED (tied to V_SS).

Thisfeatureallowstheusertoassigntheentirearrayofthememory

as ROM, which can be protected against accidental programming

writes. When WRITE is disabled, slave address and word address

will be acknowledged but data will not be acknowledged.

Addressing an EEPROM memory location involves sending a

command string with the following information:

Device Operation

The FM24C256xxx supports a bidirectional bus oriented protocol.

The protocol defines any device that sends data onto the bus as a

transmitter and the receiving devices as the receiver. The device

controlling the transfer is the master and the device that is con-

trolledistheslave.Themasterwillalwaysinitiatedatatransfersand

provide the clock for both transmit and receive operations. There-

fore, the FM24C256xxx is considered a slave in all applications.

[DEVICE TYPE]-[DEVICE ADDRESS]-[PAGE BLOCK AD-

DRESS]-[BYTE ADDRESS]

Pin Description

SERIAL CLOCK (SCL)

Definitions

CLOCK AND DATA CONVENTIONS

Data states on the SDA line can change only during SCL LOW.

SDA state changes during SCL HIGH and are reserved for

indication of start and stop conditions. Refer to Figures 1 and 2.

Word

Page

8 bits (byte) of data

64 sequential addresses (one byte each) that

may be programmed during a "Page Write"

programming cycle.

START CONDITION

Master

Any IIC device CONTROLLING the transfer of

data (such as a microcontroller).

All commands are preceded by the start condition, which is a

HIGH to LOW transition of SDA when SCL is HIGH. The

FM24C256xxx continuously monitors the SDA and SCL lines for

the start condition and will not respond to any command until this

condition has been met.

Slave

Device being controlled (EEPROMS are

always considered Slaves).

Transmitter

Receiver

Device currently SENDING data on the bus

(may be either a Master or Slave).

STOP CONDITION

All communications are terminated by a stop condition, which is a

LOW to HIGH transition of SDA when SCL is HIGH. The stop

condition is also used by the FM24C256xxx to place the device in

the standby power mode.

Device currently receiving data on the bus

(Master or Slave).

The SCL input is used to clock all data into and out of the device.

www.fairchildsemi.com

FM24C256 rev. B.3

both the device and a WRITE operation have been selected, the

FM24C256xxx will respond with an acknowledge after the receipt

of each subsequent eight bit word.

Write Cycle Timing

ACKNOWLEDGE

ACK (acknowledge) is a software convention used to indicate

successful data transfers. The transmitting device, either master or

slave,willreleasethebusaftertransmittingeightbits.Duringtheninth

clock cycle the receiver will pull the SDA line LOW to acknowledge

that it received the eight bits of data. Refer to Figure 3.

In the READ mode the FM24C256xxx slave will transmit eight bits

of data, release the SDA line and monitor the line for an acknowl-

edge. If an acknowledge is detected and no stop condition is

generated by the master, the slave will continue to transmit data.

If an acknowledge is not detected, the slave will terminate further

data transmissions and await the stop condition to return to the

standby power mode.

The FM24C256xxx device will always respond with an acknowl-

edge after recognition of a start condition and its slave address. If

Write Cycle Timing:

SCL

SDA

8th BIT

WORD n

ACK

STOP

CONDITION

START

CONDITION

DS800023-4

Data Validity (Figure 1)

SCL

SDA

DATA

CHANGE

DATA STABLE

DS800023-5

Definition of Start and Stop (Figure 2)

SCL

SDA

START CONDITION

STOP CONDITION

DS800023-6

Acknowledge Response from Receiver (Figure 3)

SCL FROM

MASTER

Data Output

from Transmitter

Data Output

from Receiver

START

ACKNOWLEDGE

DS800023-7

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FM24C256 rev. B.3

transfer by generating a stop condition, at which time the

FM24C256xxx begins the internal write cycle to the nonvolatile

memory. While the internal write cycle is in progress, the device's

inputsaredisabledandthedevicewillnotrespondtoanyrequests

from the master. Refer to Figure 5 for the address, acknowledge

and data transfer sequence.

DEVICE ADDRESSING

Following a start condition the master must output the address of

the slave it is accessing. The most significant four bits of the slave

address are those of the device type identifier. This is fixed as

1010 for all different FM24C256xxx devices.

The next three bits identify the device address. Address from 000

to 111 are acceptable thus allowing up to eight devices to be

connected to the IIC bus.

PAGE WRITE

The FM24C256xxx is capable of 64 byte page write operation. It

is initiated in the same manner as the byte write operation; but

instead of terminating the write cycle after the first data word is

transferred, the master can transmit up to 63 more words. After

the receipt of each word, the device responds with an acknowl-

edge.

The last bit of the slave address defines whether a write or read

condition is requested by the master. A "1" indicates that a READ

operation is to be executed and a "0" initiates the WRITE mode.

A simple review: After the FM24C256xxx recognizes the start

condition, the device interfaced to the IIC bus waits for a slave

address to be transmitted over the SDA line. If the transmitted

slave address matches an address of one of the devices, the

designated slave pulls the SDA line LOW with an acknowledge

signal and awaits further transmissions.

After the receipt of each word, the internal address counter

increments to the next address and the next SDA data is ac-

cepted. If the master should transmit more than 64 words prior to

generating the stop condition, the address counter will "roll over"

and the previous written data will be overwritten. As with the byte

write operation, all inputs are disabled until completion of the

internal write cycle. Refer to Figure 6 for the address, acknowl-

edge and data transfer sequence.

Write Operations

BYTE WRITE

For a WRITE operation, two additional address fields are required

afterthecontrolbyteacknowledge.Thesearethewordaddresses

and comprise fifteen bits to provide access to any one of the 32K

words. The first byte indicates the high-order byte of the word

address. Only the seven least signicant bits can be changed, the

most significant bit is pre-assigned the value "0". Following the

acknowledgement from the first word address, the next byte

indicates the low-order byte of the word address. Upon receipt of

the word address, the FM24C256xxx responds with another

acknowledge and waits for the next eight bits of data, again,

responding with an acknowledge. The master then terminates the

Acknowledge Polling

Once the stop condition is isssued to indicate the end of the host's

write operation, the FM24C256xxx initiates the internal write

cycle. ACK polling can be initiated immediately. This involves

issuingthestartconditionfollowedbytheslaveaddressforawrite

operation. If the FM24C256xxx is still busy with the write opera-

tion, noACKwillbereturned. Ifthedevicehascompletedthewrite

operation, an ACK will be returned and the host can then proceed

with the next read or write operation.

Byte Write (Figure 5)

SLAVE

ADDRESS

WORD

ADDRESS (1)

WORD

ADDRESS (0)

DATA

Bus Activity:

Master

1 0

SDA Line

Bus Activity

DS800023-8

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FM24C256 rev. B.3

withtheR/Wbitsetto"1", themastermustfirstperforma"dummy"

write operation. The master issues a start condition, a slave

address, and then the word address to be read. After the word

address acknowledge, the master immediately reissues the start

conditionandtheslaveaddresswiththeR/Wbitsetto"1". Thiswill

be followed by an acknowledge from the FM24C256xxx and then

by theeightbit word. The master willnotacknowledge the transfer

but does generate the stop condition, and therefore the

FM24C256xxx discontinues transmission. Refer to Figure 8 for

the address, acknowledge, and data transfer sequence.

Write Protection

Programming of the memory array will not take place if the WP pin

is connected to V_CC. The device will accept control and word

addresses; but if the memory accessed is write protected by the

WPpin, theFM24C256xxxwillnotgenerateanacknowledgeafter

the first byte of data has been received, and thus the program

cycle will not be started when the stop condition is asserted.

Read Operation

Read operations are initiated in the same manner as write

operations,withtheexceptionthattheR/Wbitoftheslaveaddress

is set to "1". There are three basic read operations: current

address read, random read and sequential read.

SEQUENTIAL READ

Sequential reads can be initiated as either a current address read

or random access read. The first word is transmitted in the same

manner as the other read modes; however, the master now

responds with an acknowledge, indicating it requires additional

data. The FM24C256xxx continues to output data for each ac-

knowledge received. The read operation is terminated by the

master not responding with an acknowledge or by generating a

stop condition.

CURRENT ADDRESS READ

Internally the FM24C256xxx contains an address counter that

maintains the address of the last word accessed, incremented by

one. Therefore, if the last access (either a read or write) was to

address n, the next read operation would access data from

address n+1. Upon receipt of the slave address with R/W set to

"1," the FM24C256xxx issues an acknowledge and transmits the

eight bit word. The master will not acknowledge the transfer but

does generate a stop condition, and therefore discontinues trans-

mission. Refer to Figure 7 for the sequence of address, acknowl-

edge and data transfer.

The data output is sequential, with the data from address n,

followedbythedatan+1. Theaddresscounterforreadoperations

increments all word address bits, allowing the entire memory

contents to be serially read during one operation. After the entire

memory has been read, the counter "rolls over" and the

FM24C256xxx continues to output data for each acknowledge

received. Refer to Figure 9 for the address, acknowledge, and

data transfer sequence.

RANDOM READ

Random read operations allow the master to access any memory

location in a random manner. Prior to issuing the slave address

Page Write (Figure 6)

SLAVE

ADDRESS

WORD

ADDRESS (1)

WORD

ADDRESS (0)

DATA n

DATA n+63

Bus Activity:

Master

1 0

SDA Line

Bus Activity

DS800023-9

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FM24C256 rev. B.3

Current Address Read (Figure 7)

SLAVE ADDRESS

1 0 1 0

DATA

DS800023-10

Random Read (Figure 8)

SLAVE

WORD

ADDRESS (1)

WORD

ADDRESS (0)

SLAVE

ADDRESS

Bus Activity:

DATA n

ADDRESS

Master

1 0

1 0 1 0

1 0

SDA Line

Bus Activity

DS800023-11

Sequential Read (Figure 9)

SLAVE

ADDRESS

DATA n

DATA n + 1

DATA n + x

Bus Activity:

Master

0 1 0

SDA Line

Bus Activity

DS800023-12

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FM24C256 rev. B.3

Physical Dimensions inches (millimeters) unless otherwise noted

0.189 - 0.197

(4.800 - 5.004)

0.228 - 0.244

(5.791 - 6.198)

Lead #1

IDENT

0.150 - 0.157

(3.810 - 3.988)

0.053 - 0.069

(1.346 - 1.753)

0.010 - 0.020

(0.254 - 0.508)

0.004 - 0.010

(0.102 - 0.254)

x 45¡

8¡ Max, Typ.

All leads

Seating

Plane

0.004

(0.102)

All lead tips

0.0075 - 0.0098

(0.190 - 0.249)

Typ. All Leads

0.014

(0.356)

0.016 - 0.050

(0.406 - 1.270)

Typ. All Leads

0.050

(1.270)

Typ

0.014 - 0.020

Typ.

(0.356 - 0.508)

Molded Small Out-Line Package (M8)

Order Number FM24C256xxxM8 or FM24C256xxxEM8

Package Number M08A

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FM24C256 rev. B.3

Physical Dimensions inches (millimeters) unless otherwise noted

0.373 - 0.400

(9.474 - 10.16)

0.090

(2.286)

0.032 0.005

(0.813 0.127)

RAD

0.092

(2.337)

DIA

0.250 - 0.005

(6.35 0.127)

Pin #1

IDENT

Pin #1 IDENT

Option 1

Option 2

0.280

MIN

0.040

(1.016)

Typ.

(7.112)

0.030

0.145 - 0.200

(3.683 - 5.080)

0.039

(0.991)

MAX

(0.762)

0.300 - 0.320

(7.62 - 8.128)

20° 1°

0.130 0.005

(3.302 0.127)

0.125 - 0.140

95° 5°

0.009 - 0.015

(3.175 - 3.556)

0.065

(1.651)

0.125

(3.175)

DIA

0.020

90° 4°

Typ

(0.508)

Min

(0.229 - 0.381)

0.018 0.003

(0.457 0.076)

NOM

+0.040

-0.015

0.325

0.100 0.010

+1.016

-0.381

8.255

(2.540 0.254)

0.045 0.015

(1.143 0.381)

0.060

(1.524)

0.050

(1.270)

Molded Dual-In-Line Package (N)

Order Number FM24C256xxxN or FM24C256xxxEN

Package Number N08E

Life Support Policy

Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written

approval of the President of Fairchild Semiconductor Corporation. As used herein:

1. Life support devices or systems are devices or systems which,

(a)areintendedforsurgicalimplantintothebody,or(b)support

or sustain life, and whose failure to perform, when properly

used in accordance with instructions for use provided in the

labeling, can be reasonably expected to result in a significant

injury to the user.

2. A critical component is any component of a life support device

or system whose failure to perform can be reasonably ex-

pected to cause the failure of the life support device or system,

or to affect its safety or effectiveness.

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Fairchild Semiconductor

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Fairchild Semiconductor

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Fairchild Semiconductor

Japan Ltd.

Customer Response Center

Tel. 1-888-522-5372

Fax:

Tel:

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Tel: 81-3-3818-8840

Fax: 81-3-3818-8841

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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FM24C256 rev. B.3

FM24C256FLZYYX [FAIRCHILD]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E