FM24C32UFTHN [FAIRCHILD]

EEPROM ; EEPROM\n


型号：	FM24C32UFTHN
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	EEPROM EEPROM\n 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件：	总13页 (文件大小：88K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

September 2002

FM24C32U – 32K-Bit Standard 2-Wire Bus

Interface Serial EEPROM

General Description

Features

FM24C32U is a 32Kbit CMOS non-volatile serial EEPROM orga-

nized as 4K x 8 bit memory. This device confirms to Extended IIC

2-wire protocol that allows accessing of memory in excess of

16Kbit on an IIC bus. This serial communication protocol uses a

Clock signal (SCL) and a Data signal (SDA) to synchronously

clock data between a master (e.g. a microcontroller) and a slave

(EEPROM). FM24C32U is designed to minimize pin count and

simplify PC board layout requirements.

I Extended operating voltage: 2.7V to 5.5V

I Up to 400 KHz clock frequency at 2.7V to 5.5V

I Low power consumption

—0.2mA active current typical

—10µA standby current typical

—1µA standby current typical (L version)

—0.1µA standby current typical (LZ version)

I Schmitt trigger inputs

FM24C32U offers hardware write protection where by the upper

half (upper 16Kbit) of the memory array can be write protected by

connecting WP pin to V_CC. This section of memory then becomes

I 32 byte page write mode

I Self timed write cycle (6ms typical)

I Hardware Write Protection for upper half of the array

unalterable until the WP pin is switched to V_SS

I Low V_CCprogramming lockout for V_CC= 5V 10% (“H” option)

—Internal ERASE/WRITE logic is disabled if V_CCis below 3.8V

“LZ” and “L” versions of FM24C32U offer very low standby current

making them suitable for low power applications. This device is

offered in both SO and DIP packages.

I Endurance: 1 Million data changes

I Data Retention: Greater than 40 years

I Packages: 8-Pin DIP and 8-Pin SO

Fairchild EEPROMs are designed and tested for applications

requiringhighendurance, highreliabilityandlowpowerconsump-

tion.

I Temperature range

—Commercial: 0°C to +70°C

—Industrial (V): -40°C to +85°C

—Automotive (E): -40°C to +125°C

Block Diagram

WRITE

LOCKOUT

H.V. GENERATION

TIMING &CONTROL

START

STOP

SDA

LOGIC

CONTROL

LOGIC

SLAVE ADDRESS

COMPARATOR

PROM

ARRAY

XDEC

SCL

WORD

ADDRESS

COUNTER

R/W

YDEC

OUT

DATA REGISTER

FM24C32U Rev. A.1

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Connection Diagram

Dual-in-Line Package (N) and SO Package (M8)

V_CC

FM24C32U

SCL

SDA

V_SS

See Package Number N08E and M08A

Pin Names

V_SS

SDA

SCL

Ground

Serial Data I/O

Serial Clock Input

Write Protect

V_CC

Power Supply

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FM24C32U Rev. A.1

Ordering Information

FM 24

XXX

Letter

Description

Package

8-pin DIP

8-pin SOIC

Temp. Range

None

0 to 70°C

-40 to +125°C

-40 to +85°C

Voltage Operating Range

Blank

4.5V to 5.5V

4.5V to 5.5V and V_CC

Lockout

2.7V to 5.5V

2.7V to 5.5V and

<1µA Standby Current

Blank

Normal Pin Out

Rotated Die Pin Out

SCL Clock Frequency

Process

Blank

100KHz

400KHz

Ultralite Process

Density

32K with Write Protect

CMOS Technology

IIC

Interface

Fairchild Non-Volatile

Memory

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FM24C32U Rev. A.1

Product Specifications

Operating Conditions

Absolute Maximum Ratings

Ambient Operating Temperature

FM24C32U

Ambient Storage Temperature

–65°C to +150°C

6.5V to –0.3V

0°C to +70°C

-40°C to +85°C

-40°C to +125°C

All Input or Output Voltages

with Respect to Ground

FM24C32UE

FM24C32UV

Lead Temperature

Positive Power Supply

FM24C32U/FM24C32UH

FM24C32UL

(Soldering, 10 seconds)

+300°C

4.5V to 5.5V

2.7V to 5.5V

ESD Rating

2000V min.

FM24C32ULZ

Standard V_CC(4.5V to 5.5V) DC Electrical Characteristics

Symbol

Parameter

Test Conditions

Limits

Typ

Units

Min

Max

(Note 1)

I_CCA

Active Power Supply

Current

f_SCL= 400 KHz

f_SCL= 100 KHz

0.2

1.0

I_SB

I_LI

Standby Current

V_IN= GND or V_CC

µA

Input Leakage Current

V_IN= GND A₀, A₁, A₂, WP

0.1

0.5

µA

to V_CC

SCL

I_LO

V_IL

Output Leakage Current

Input Low Voltage

V_OUT= GND to V_CC

0.1

µA

–0.3

V_CCx 0.3

V_CC+ 0.5

0.4

V_IH

V_OL

Input High Voltage

Output Low Voltage

V_CCx 0.7

I_OL= 3 mA

Low V_CC(2.7V to 5 .5V) DC Electrical Characteristics

Symbol

Parameter

Test Conditions

Limits

Units

Min

Typ

Max

(Note 1)

I_CCA

Active Power Supply Current f_SCL= 400 KHz

f_SCL= 100 KHz

0.2

1.0

I_SB

(Note 3)

Standby Current

V_IN= GND V_CC= 2.7V - 4.5V (L)

0.1

µA

or V_CC

V_CC= 2.7V - 4.5V (LZ)

V_CC= 4.5V - 5.5V

I_LI

Input Leakage Current

V_IN= GND A₀, A₁, A₂, WP

to V_CCSCL

0.1

0.5

µA

I_LO

V_IL

Output Leakage Current

Input Low Voltage

V_OUT= GND to V_CC

0.1

µA

–0.3

V_CCx 0.3

V_CC+ 0.5

0.4

V_IH

V_OL

Input High Voltage

Output Low Voltage

V_CCx 0.7

I_OL= 3 mA

Capacitance T_A= +25°C, f = 100/400 KHz, V_CC= 5V (Note 2)

Symbol

C_I/O

Test

Conditions

V_I/O= 0V

Max Units

Input/Output Capacitance (SDA)

Input Capacitance (A0, A1, A2, SCL)

C_IN

V_IN= 0V

Note 1: Typical values are T_A= 25°C and nominal supply voltage (5V).

Note 2: This parameter is periodically sampled and not 100% tested.

Note 3: The "L" and "LZ" versions can be operated in the 2.7V to 5.5V V_CCrange. However the I_SBvalues for L and LZ are applicable only when V_CCis in the 2.7V to 4.5V range.

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FM24C32U Rev. A.1

AC Testing Input/Output Waveforms

AC Test Conditions

Input Pulse Levels

V_CCx 0.1 to V_CCx 0.9

10 ns

0.9V_CC

0.7V_CC

0.3V_CC

Input Rise and Fall Times

0.1V_CC

Input & Output Timing Levels V_CCx 0.3 to V_CCx 0.7

Output Load 1 TTL Gate and C_L= 100 pF

Read and Write Cycle Limits (Standard and Low V_CCRange 2.7V - 5.5V)

Symbol

Parameter

100 KHz

400 KHz

Units

Min

Max

Min

Max

f_SCL

T_I

SCL Clock Frequency

100

3.5

400

KHz

Noise Suppression Time Constant at

SCL, SDA Inputs (Minimum V_IN

Pulse width)

t_AA

SCL Low to SDA Data Out Valid

0.3

4.7

0.1

1.3

0.9

µs

t_BUF

Time the Bus Must Be Free before

a New Transmission Can Start

t_HD:STA

t_LOW

Start Condition Hold Time

Clock Low Period

4.0

4.7

4.0

4.7

0.6

1.5

0.6

µs

t_HIGH

Clock High Period

t_SU:STA

Start Condition Setup Time

(for a Repeated Start Condition)

t_HD:DAT

t_SU:DAT

t_R

Data in Hold Time

µs

Data in Setup Time

250

100

SDA and SCL Rise Time

SDA and SCL Fall Time

Stop Condition Setup Time

Data Out Hold Time

0.3

t_F

300

t_SU:STO

t_DH

4.7

0.6

300

t_WR

(Note 4)

Write Cycle Time

4.5V to 5.5V V_CC

2.7V to 4.5V V_CC

Note 4: The write cycle time (t_WR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the

FM24C32U bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address. Refer

"Write Cycle Timing" diagram.

Bus Timing

HIGH

LOW

SCL

SU:STO

SU:DAT

SU:STA

HD:DAT

HD:STA

SDA

BUF

SDA

OUT

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FM24C32U Rev. A.1

Write Cycle Timing

SCL

SDA

8th BIT

WORD n

ACK

STOP

START

CONDITION

Note:

The write cycle time (t_WR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle.

Typical System Configuration

V_CC

SDA

SCL

Master

Transmitter/

Receiver

Slave

Transmitter/

Receiver

Master

Transmitter/

Receiver

Master

Transmitter

Slave

Receiver

Note:

Due to open drain configuration of SDA and SCL, a bus-level pull-up resistor is called for, (typical value = 4.7kΩ)

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FM24C32U Rev. A.1

Device Type

Background Information (IIC Bus)

IIC bus is designed to support a variety of devices such as RAMs,

EPROMs etc., along with EEPROMS. Hence to properly identify

various devices on the IIC bus, a 4-bit “Device Type” identifier

stringisused. ForEEPROMS, this4-bitstringis1-0-1-0. EveryIIC

device on the bus internally compares this 4-bit string to its own

“Device Type” string to ensure proper device selection.

Extended IIC specification is an extension of Standard IIC speci-

fication to allow addressing of EEPROMs with more than 16Kbits

of memory on an IIC bus. The difference between the two

specifications is that Extended IIC specification defines two bytes

of “Array Address” information while Standard IIC specification

defines only one. All other aspects are identical between the two

specifications. Using two bytes of Array Address and 3 address

signals (A2, A1 and A0), it is now possible to address up to 4 Mbits

(2⁸* 2⁸* 2³* 8 = 4 Mbits) of memory on an IIC bus.

Device/Page Block Selection

Whenmultipledevicesofthesametype(e.g.multipleEEPROMS)

are present on the IIC bus, then the A2, A1 and A0 address

information bits are used in device selection. Every IIC device on

the bus internally compares this 3-bit string to its own physical

configuration (A2, A1 and A0 pins) to ensure proper device

selection. This comparison is in addition to the “Device Type”

comparison.

Note that due to format difference, it is not possible to have

peripherals which follow Standard IIC specification (e.g. 16K bit

EEPROM) and peripherals which follow Extended IIC specifica-

tion (e.g. 32K bit EEPROM) on a common IIC bus.

IIC bus allows synchronous bi-directional communication be-

tween a TRANSMITTER and a RECEIVER using a Clock signal

(SCL) and a Data signal (SDA). Additionally there are up to three

Address signals (A2, A1 and A0) which collectively serve as “chip

select signal” to a device (e.g. EEPROM) on the bus.

In addition to selecting an EEPROM, these 3 bits are also used to

select a “page block” within the selected EEPROM. Each page

blockis512Kbit(64KBytes)insize. IfanEEPROMcontainsmore

than one page bock then the selection of a page block within the

EEPROM is by using A2, A1 and A0 bits.

All communication on the IIC bus must be started with a valid

START condition (by a MASTER), followed by transmittal (by the

MASTER) of byte(s) of information (Address/Data). For every

byte of information received, the addressed RECEIVER provides

a valid ACKNOWLEDGE pulse to further continue the communi-

cation unless the RECEIVER intends to discontinue the commu-

nication. Depending on the direction of transfer (Write or Read),

the RECEIVER can be a SLAVE or the MASTER. A typical IIC

communication concludes with a STOP condition (by the MAS-

TER).

Read/Write Bit

Last bit of the Slave Address indicates if the intended access is

Read or Write. If the bit is "1," then the access is Read, whereas

if the bit is "0," then the access is Write.

Acknowledge

Acknowledge is an active LOW pulse on the SDA line driven by an

addressed receiver to the addressing transmitter to indicate

receipt of 8-bits of data. The receiver provides an ACK pulse for

every 8-bits of data received. This handshake mechanism is done

as follows: After transmitting 8-bits of data, the transmitter re-

leases the SDA line and waits for the ACK pulse. The addressed

receiver, if present, drives the ACK pulse on the SDA line during

the 9th clock and releases the SDA line back (to the transmitter).

Refer Figure 3.

Addressing an EEPROM memory location involves sending a

command string with the following information:

[DEVICE TYPE]—[DEVICE/PAGE BLOCK SELECTION]—[R/W

BIT]—[ARRAY ADDRESS#1]—[ARRAY ADDRESS#0]

Slave Address

Slave Address is an 8-bit information consisting of a Device type

field (4bits), Device/Page block selection field (3bits) and Read/

Write bit (1bit).

Array Address#1

This is an 8-bit information containing the most significant 8-bits of

16-bit memory array address of a location to be selected within a

page block of the device.

Slave Address Format

Array Address#0

Device Type

Identifier

Device/Page Block

Selection

This is an 8-bit information containing the least significant 8-bits of

16-bit memory array address of a location to be selected within a

page block of the device.

A0 R/W (LSB)

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FM24C32U Rev. A.1

Pin Descriptions

Device Operation

The FM24C32U supports a bi-directional bus oriented protocol.

The protocol defines any device that sends data onto the bus as

a transmitter and the receiving device as the receiver. The device

controlling the transfer is the master and the device that is

controlled is the slave. The master will always initiate data

transfers and provide the clock for both transmit and receive

operations. Therefore, the FM24C32U will be considered a slave

in all applications.

Serial Clock (SCL)

The SCL input is used to clock all data into and out of the device.

Serial Data (SDA)

SDA is a bi-directional pin used to transfer data into and out of the

device. It is an open drain output and may be wire–ORed with any

number of open drain or open collector outputs.

Write Protect (WP)

Clock and Data Conventions

If tied to V , PROGRAM operations onto the upper half (upper

Data states on the SDA line can change only during SCL LOW.

SDA state changes during SCL HIGH are reserved for indicating

start and stop conditions. Refer Figure 1.

16Kbits)ofthememorywillnotbeexecuted.READoperationsare

possible. If tied to V , normal operation is enabled, READ/

WRITE over the entire memory is possible.

Start Condition

Thisfeatureallowstheusertoassigntheupperhalfofthememory

as ROM which can be protected against accidental programming.

When write is disabled, slave address and word address will be

acknowledged but data will not be acknowledged.

All commands are preceded by the start condition, which is a

HIGHtoLOWtransitionofSDAwhenSCLisHIGH.TheFM24C32U

continuously monitors the SDA and SCL lines for the start condi-

tion and will not respond to any command until this condition has

been met. Refer Figure 2.

This pin has an internal pull-down circuit. However, on systems

where write protection is not required it is recommended that this

Stop Condition

pin is tied to V_SS

All communications are terminated by a stop condition, which is a

LOW to HIGH transition of SDA when SCL is HIGH. The stop

condition is also used by the FM24C32U to place the device in the

standby power mode. Refer Figure 2.

Device Selection Inputs A2, A1 and A0 (as

appropriate)

These inputs collectively serve as “chip select” signal to an

EEPROM when multiple EEPROMs are present on the same IIC

bus. Hence these inputs should be connected to V_CCor V_SSin a

unique manner to allow proper selection of an EEPROM amongst

multiple EEPROMs. During a typical addressing sequence, every

EEPROM on the IIC bus compares the configuration of these

inputs to the respective 3 bit “Device/Page block selection”

information (part of slave address) to determine a valid selection.

For e.g. if the 3 bit “Device/Page block selection” is 1-0-1, then the

EEPROM whose “Device Selection inputs” (A2, A1 and A0) are

connected to V_CC-V_SS-V_CCrespectively, is selected.

FM24C32U Array Addressing

During Read/Write operations, addressing the EEPROM memory

array involves in providing 2 address bytes, “Word Address 1” and

“Word Address 0." However on FM24C32U only the 4 least

significant bits (LSB) of “Word Address 1” byte are used in

decoding the access location. The remaining 4 bits are not used

and are recommended to be set to “0”. All 8 bits of the “Word

Address 0” byte are used in decoding the access location.

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FM24C32U Rev. A.1

Data Validity (Figure 1)

SCL

SDA

DATA STABLE

DATA

CHANGE

Start and Stop Definition (Figure 2)

SCL

SDA

START

STOP

CONDITION

Acknowledge Response from Receiver (Figure 3)

SCL FROM

MASTER

DATA OUTPUT

FROM

TRANSMITTER

DATA OUTPUT

FROM

RECEIVER

START

CONDITION

ACKNOWLEDGE

PULSE

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FM24C32U Rev. A.1

Page Write is initiated in the same manner as the Byte Write

operation; but instead of terminating the cycle after transmitting

the first data byte, the master can further transmit up to 31 more

bytes. After the receipt of each byte, FM24C32U will respond with

an acknowledge pulse, increment the internal address counter to

thenextaddress,andisreadytoacceptthenextdata.Ifthemaster

should transmit more than 32 bytes prior to generating the STOP

condition, the address counter will “roll over” and previously

loaded data will be re-loaded. As with the Byte Write operation, all

inputs are disabled until completion of the internal write cycle.

Refer Figure 5 for the address, acknowledge, and data transfer

sequence.

Write Operations

BYTE WRITE

For byte write operation, two bytes of address are required after

the slave address. These two bytes select 1 out of the 4096

locations in the memory. The master provides these two address

bytes and for each address byte received, FM24C32U responds

with an acknowledge pulse. Master then provides a byte of data

tobewrittenintothememory.Uponreceiptofthisdata,FM24C32U

respondswithanacknowledgepulse. Themasterthenterminates

the transfer by generating a stop condition, at which time the

FM24C32U begins the internal write cycle to the memory. While

the internal write cycle is in progress the FM24C32U inputs are

disabled, and the device will not respond to any requests from the

master for the duration of t_WR. Refer Figure 4 for the address,

acknowledge and data transfer sequence.

Acknowledge Polling

Once the stop condition is issued to indicate the end of the host’s

write operation, the FM24C32U initiates the internal write cycle.

ACKpollingcanbeinitiatedimmediately. Thisinvolvesissuingthe

start condition followed by the slave address for a write operation.

If the FM24C32U is still busy with the write operation, no ACK will

be returned. If the FM24C32U has completed the write operation,

an ACK will be returned and the host can then proceed with the

next read or write operation.

PAGE WRITE

To minimize write cycle time, FM24C32U offers Page Write

feature, which allows simultaneous programming of up to 32

contiguous bytes. To facilitate this feature, the memory array is

organized in terms of “Pages”. A Page consists of 32 contiguous

byte locations starting at every 32-Byte address boundary (for

example, starting at array address 0x0000, 0x0020, 0x0040 etc.).

Page Write operation is confined to a single page. In other words

a Page Write operation will not cross over to locations on the next

page but will “roll over” to the beginning of the same page

whenever end of page is reached and additional data bytes are a

continued to be provided. A Page Write operation can be initiated

tobeginatanylocationwithinapage(startingaddressofthePage

Write operation need not be the starting address of a Page).

Write Protection

Programmingoftheupperhalf(upper8Kbit)ofthememorywillnot

take place if the WP pin of the FM24C32U is connected to V

The FM24C32U will respond to slave and byte addresses; but if

the memory accessed is write protected by the WP pin, the

FM24C32U will not generate an acknowledge after the first byte

of data has been received. Thus the program cycle will not be

started when the stop condition is asserted.

Byte Write (Figure 4)

Page Write (Figure 5)

SLAVE

ADDRESS

WORD

ADDRESS (1)

WORD

ADDRESS (0)

DATA

Bus Activity:

Master

SDA Line

Bus Activity:

EEPROM

SLAVE

ADDRESS

WORD

ADDRESS (1)

WORD

ADDRESS (0)

DATA n

DATA n+31

Bus Activity:

Master

SDA Line

Bus Activity:

EEPROM

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FM24C32U Rev. A.1

will not acknowledge the transfer but does generate the stop

condition, and therefore the FM24C32U discontinues transmis-

sion. Refer Figure 7 for the address, acknowledge, and data

transfer sequence.

Read Operations

Read operations are initiated in the same manner as write

operations, with the exception that the R/W bit of the slave

address is set to a one. There are three basic read operations:

current address read, random read, and sequential read.

Sequential Read

Sequential reads can be initiated as either a current address read

or random access read. The first word is transmitted in the same

manner as the other read modes; however, the master now

responds with an acknowledge, indicating it requires additional

data. The FM24C32U continues to output data for each acknowl-

edgereceived. Thereadoperationisterminatedbythemasternot

responding with an acknowledge or by generating a stop condi-

tion.

Current Address Read

Internally the FM24C32U contains an address counter that

maintains the address of the last byte accessed, incremented by

one. Therefore, if the last access (either a read or write) was to

address n, the next read operation would access data from

address n + 1. Upon receipt of the slave address with R/W set to

"1," the FM24C32U issues an acknowledge and transmits the

eight bit word. The master will not acknowledge the transfer but

does generate a stop condition, and therefore the FM24C32U

discontinues transmission. Refer Figure 6 for the sequence of

address, acknowledge and data transfer.

The data output is sequential with the data from address n

followed by the data from n + 1. The address counter for read

operations increments all word address bits, allowing the entire

memory contents to be serially read during one operation. After

the entire memory has been read, the counter "rolls over" to the

beginning of the memory. FM24C32U continues to output data for

each acknowledge received. Refer Figure 8 for the address,

acknowledge, and data transfer sequence.

Random Read

Random read operations allow the master to access any memory

location in a random manner. Prior to issuing the slave address

with the R/W bit set to "1," the master must first perform a

“dummy” write operation. The master issues the start condition,

slave address with the R/W bit set to "0" and then the byte

address. After the byte address acknowledge, the master imme-

diately issues another start condition and the slave address with

the R/W bit set to one. This will be followed by an acknowledge

from the FM24C32U and then by the eight bit word. The master

Low V_CCWRITE Lockout

FM24C32U -“H” version offers low V_CCwrite lockout feature to

safeguard data whenever Vcc falls below 3.8V. Normally, the

operating V_CCfor FM24C32U “H” version is 5V. However during

system operation if the V_CCreaches below 3.8V, then internally all

write commands to the array are locked out.

Current Address Read (Figure 6)

SLAVE

ADDRESS

Bus Activity:

Master

1 0 1

SDA Line

Bus Activity:

EEPROM

DATA

Random Read (Figure 7)

SLAVE

ADDRESS

WORD

ADDRESS (1)

WORD

ADDRESS (0)

SLAVE

ADDRESS

Bus Activity:

Master

DATA

SDA Line

Bus Activity:

EEPROM

Sequential Read (Figure 8)

Bus Activity:

Slave

Master

Address

SDA Line

DATA n +1

DATA n + 2

DATA n + x

Bus Activity:

EEPROM

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FM24C32U Rev. A.1

Physical Dimensions inches (millimeters) unless otherwise noted

0.189 - 0.197

(4.800 - 5.004)

0.228 - 0.244

(5.791 - 6.198)

Lead #1

IDENT

0.150 - 0.157

(3.810 - 3.988)

0.053 - 0.069

(1.346 - 1.753)

0.010 - 0.020

(0.254 - 0.508)

0.004 - 0.010

(0.102 - 0.254)

x 45¡

8¡ Max, Typ.

All leads

Seating

Plane

0.004

(0.102)

All lead tips

0.0075 - 0.0098

(0.190 - 0.249)

Typ. All Leads

0.014

(0.356)

0.016 - 0.050

(0.406 - 1.270)

Typ. All Leads

0.050

(1.270)

Typ

0.014 - 0.020

Typ.

(0.356 - 0.508)

8-Pin Molded Small Outline Package (M8)

Package Number M08A

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FM24C32U Rev. A.1

Physical Dimensions inches (millimeters) unless otherwise noted

0.373 - 0.400

(9.474 - 10.16)

0.090

(2.286)

0.032 0.005

(0.813 0.127)

RAD

0.092

(2.337)

DIA

0.250 - 0.005

(6.35 0.127)

Pin #1

IDENT

Pin #1 IDENT

Option 1

Option 2

0.280

MIN

0.040

(1.016)

Typ.

(7.112)

0.030

0.145 - 0.200

(3.683 - 5.080)

0.039

(0.991)

MAX

(0.762)

0.300 - 0.320

(7.62 - 8.128)

20° 1°

0.130 0.005

(3.302 0.127)

0.125 - 0.140

95° 5°

(3.175 - 3.556)

0.065

(1.651)

0.125

(3.175)

DIA

0.020

90° 4°

Typ

0.009 - 0.015

(0.229 - 0.381)

(0.508)

Min

0.018 0.003

(0.457 0.076)

NOM

+0.040

-0.015

0.325

0.100 0.010

+1.016

-0.381

8.255

(2.540 0.254)

0.045 0.015

(1.143 0.381)

0.060

(1.524)

0.050

(1.270)

Molded Dual-In-Line Package (N)

Package Number N08E

Life Support Policy

Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written

approval of the President of Fairchild Semiconductor Corporation. As used herein:

1. Life support devices or systems are devices or systems which,

(a)areintendedforsurgicalimplantintothebody,or(b)support

or sustain life, and whose failure to perform, when properly

used in accordance with instructions for use provided in the

labeling, can be reasonably expected to result in a significant

injury to the user.

2. A critical component is any component of a life support device

or system whose failure to perform can be reasonably ex-

pected to cause the failure of the life support device or system,

or to affect its safety or effectiveness.

Fairchild Semiconductor

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Fairchild Semiconductor

Europe

Fairchild Semiconductor

Hong Kong

Fairchild Semiconductor

Japan Ltd.

Customer Response Center

Tel. 1-888-522-5372

Fax:

Tel:

+44 (0) 1793-856858

8/F, Room 808, Empire Centre

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Tel: 81-3-3818-8840

Fax: 81-3-3818-8841

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

www.fairchildsemi.com

FM24C32U Rev. A.1

FM24C32UFTHN [FAIRCHILD]

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