FM25C020UN [FAIRCHILD]
EEPROM, 256X8, Serial, CMOS, PDIP8, PLASTIC, DIP-8;
| 型号： | FM25C020UN |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | EEPROM, 256X8, Serial, CMOS, PDIP8, PLASTIC, DIP-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 |
| 文件： | 总11页 (文件大小：106K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 2002
FM25C020U
2K-Bit SPI™ Interface
Serial CMOS EEPROM
General Description
Functions
The FM25C020U is a 2K (2,048) bit serial interface CMOS
EEPROM (Electrically Erasable Programmable Read-Only
Memory). This device fully conforms to the SPI 4-wire protocol
whichusesChipSelect(/CS), Clock(SCK), Data-in(SI)andData-
out (SO) pins to synchronously control data transfer between the
SPI microcontroller and the EEPROM. In addition, the serial
interface allows a minimal pin count, packaging designed to
simplify PC board layout requirements and offers the designer a
variety of low voltage and low power options.
I SPI MODE 0 interface
I 2,048 bits organized as 256 x 8
I Extended 2.7V to 5.5V operating voltage
I 2.1 MHz operation @ 4.5V - 5.5V
I Self-timed programming cycle
I "Programming complete" indicated by STATUS REGISTER
polling
I /WP pin and BLOCK WRITE protection
This SPI EEPROM family is designed to work with the 68HC11 or
any other SPI-compatible, high-speed microcontroller and offers
both hardware (/WP pin) and software ("block write") data protec-
tion. For example, entering a 2-bit code into the STATUS REGIS-
TER prevents programming in a selected block of memory and all
Features
I Sequential read of entire array
I 4 byte "Page write" mode to minimize total write time per
byte
programming can be inhibited by connecting the /WP pin to VSS
;
allowing the user to protect the entire array or a selected section.
In addition, SPI devices feature a /HOLD pin, which allows a
temporary interruption of the datastream into the EEPROM.
I /WP pin and BLOCK WRITE protection to prevent inadvert-
ent programming as well as programming ENABLE and
DISABLE opcodes.
I /HOLD pin to suspend data transfer
Fairchild EEPROMs are designed and tested for applications
requiring high endurance, high reliability, and low power con-
sumption for a continuously reliable non-volatile solution for all
markets.
I Typical 1µA standby current (ISB) for "L" devices and 0.1µA
standby current for "LZ" devices.
I Endurance: Up to 1,000,000 data changes
I Data retention greater than 40 years
Block Diagram
/CS
/HOLD
SCK
VCC
VSS
Instruction
Decoder
Control Logic
and Clock
/WP
Instruction
SI
Generators
Register
Program
Enable
Address
Counter/
Register
High Voltage
Generator
and
Program
Timer
VPP
Decoder
EEPROM Array
Read/Write Amps
Data In/Out Register
8 Bits
Data Out
Buffer
SO
Non-Volatile
Status Register
SPI™ is a trademark of Motorola Corporation
1
© 2002 Fairchild Semiconductor Corporation
FM25C020U Rev. B
www.fairchildsemi.com
Connection Diagram
Dual-In-Line Package (N), SO Package (M8),
and TSSOP Package (MT8)
/CS
SO
1
2
3
4
8
7
6
5
VCC
/HOLD
SCK
SI
FM25C020U
/WP
VSS
Top View
See Package Number N08E (N), M08A (M8), and MTC08 (MT8)
Pin Names
/CS
SO
Chip Select Input
Serial Data Output
Write Protect
/WP
VSS
Ground
SI
Serial Data Input
Serial Clock Input
Suspends Serial Data
Power Supply
SCK
/HOLD
VCC
Ordering Information
FM
25
C
XX
U
LZ E
XX
Letter Description
Package
N
8-pin DIP
M8
MT8
8-pin SO
8-pin TSSOP
Temp. Range
None
0 to 70°C
V
E
-40 to +125°C
-40 to +85°C
Voltage Operating Range
Blank
L
4.5V to 5.5V
2.7V to 5.5V
LZ
2.7V to 5.5V and
<1µA Standby Current
Ultralite
020
C
CS100UL Process
2K, mode 0
Density/Mode
Interface
CMOS technology
SPI
25
FM
Fairchild Nonvolatile
Memory Prefix
2
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FM25C020U Rev. B
Standard Voltage 4.5 ≤ VCC ≤ 5.5V Specifications
Operating Conditions
Absolute Maximum Ratings (Note 1)
Ambient Operating Temperature
FM25C020U
Ambient Storage Temperature
-65°C to +150°C
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
All Input or Output Voltage with
Respect to Ground
FM25C020UE
FM25C020UV
+6.5V to -0.3V
+300°C
Lead Temp. (Soldering, 10 sec.)
ESD Rating
Power Supply (VCC
)
4.5V to 5.5V
2000V
DC and AC Electrical Characteristics 4.5V ≤ VCC ≤ 5.5V (unless otherwise specified)
Symbol
Parameter
Conditions
Min
Max
Units
ICC
ICCSB
IIL
Operating Current
/CS = VIL
3
50
mA
µA
µA
µA
V
Standby Current
/CS = VCC
Input Leakage
VIN = 0 to VCC
VOUT = GND to VCC
-1
-1
+1
IOL
Output Leakage
+1
VIL
CMOS Input Low Voltage
CMOS Input High Voltage
Output Low Voltage
Output High Voltage
SCK Frequency
-0.3
VCC * 0.3
VCC + 0.3
0.4
VIH
VOL
VOH
fOP
0.7 * VCC
V
IOL = 1.6 mA
IOH = -0.8 mA
V
VCC - 0.8
V
2.1
2.0
2.0
MHz
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
tRI
Input Rise Time
tFI
Input Fall Time
tCLH
tCLL
tCSH
tCSS
tDIS
tHDS
tCSN
tDIN
tHDN
tPD
Clock High Time
Clock Low Time
(Note 2)
(Note 2)
(Note 3)
190
190
240
240
100
90
Min /CS High Time
/CS Setup Time
Data Setup Time
/HOLD Setup Time
/CS Hold Time
240
100
90
Data Hold Time
/HOLD Hold Time
Output Delay
CL = 200 pF
240
tDH
Output Hold Time
/HOLD to Output Low Z
Output Disable Time
/HOLD to Output High Z
Write Cycle Time
0
tLZ
100
240
100
10
tDF
CL = 200 pF
tHZ
tWP
1–16 Bytes
Capacitance TA = 25°C, f = 2.1/1 MHz (Note 4)
AC Test Conditions
Output Load
CL = 200 pF
Symbol
COUT
Test
Typ Max Units
Input Pulse Levels
0.1 * VCC – 0.9 * VCC
Output Capacitance
Input Capacitance
3
2
8
6
pF
pF
Timing Measurement Reference Level 0.3 * VCC - 0.7 * VCC
CIN
Note 1: Stress above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the
device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Note 2: The fOP frequency specification specifies a minimum clock period of 1/fOP. Therefore, for every fOP clock cycle, tCLH + tCLL must be equal to or greater than 1/fOP. For
example, for a fOP of 2.1MHz, the period equals 476ns. In this case if t CLH = is set to 190ns, then tCLL must be set to a minimum of 286ns.
Note 3: /CS must be brought high for a minimum of tCSH between consecutive instruction cycles.
Note 4: This parameter is periodically sampled and not 100% tested.
3
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FM25C020U Rev. B
Low Voltage 2.7V ≤ VCC ≤ 4.5V Specifications
Operating Conditions
Absolute Maximum Ratings (Note 5)
Ambient Storage Temperature
-65°C to +150°C
Ambient Operating Temperature
FM25C020UL/LZ
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
All Input or Output Voltage with
Respect to Ground
FM25C020ULE/LZE
FM25C020ULV
+6.5V to -0.3V
+300°C
Lead Temp. (Soldering, 10 sec.)
ESD Rating
Power Supply (VCC
)
2.7V–4.5V
2000V
DC and AC Electrical Characteristics 2.7V ≤ VCC ≤ 4.5V (unless otherwise specified)
25C020UL/LE
25C020ULZ/ZE
25C020ULV
Symbol
Parameter
Part
Conditions
Min.
Max.
Min
Max
Units
ICC
Operating Current
/CS = VIL
3
3
mA
ICCSB
Standby Current
L
LZ
/CS = VCC
10
1
10
N/A
µA
µA
IIL
Input Leakage
VIN = 0 to VCC
-1
-1
1
1
-1
-1
1
1
µA
µA
V
IOL
Output Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
SCK Frequency
Input Rise Time
VOUT = GND to VCC
VIL
-0.3
VCC * 0.3
-0.3
VCC * 0.3
VIH
VOL
VOH
fOP
tRI
VCC * 0.7 VCC + 0.3
VCC * 0.7 VCC + 0.3
V
IOL = 0.8 mA
0.4
0.4
V
IOH = –0.8 mA
VCC - 0.8
VCC - 0.8
V
1.0
1.0
MHz
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
2.0
2.0
tFI
Input Fall Time
2.0
2.0
tCLH
tCLL
tCSH
tCSS
tDIS
tHDS
tCSN
tDIN
tHDN
tPD
Clock High Time
Clock Low Time
Min. /CS High Time
/CS Setup Time
Data Setup Time
/HOLD Setup Time
/CS Hold Time
(Note 6)
(Note 6)
(Note 7)
410
410
500
500
100
240
500
100
240
500
0
410
410
500
500
100
240
500
100
240
500
0
Data Hold Time
/HOLD Hold Time
Output Delay
CL = 200 pF
tDH
tLZ
Output Hold Time
/HOLD Output Low Z
Output Disable Time
/HOLD to Output Hi Z
Write Cycle Time
240
500
240
15
240
500
240
15
tDF
CL = 200 pF
1-16 Bytes
tHZ
tWP
Capacitance TA = 25°C, f = 2.1/1 MHz (Note 8)
AC Test Conditions
Output Load
CL = 200pF
Symbol
COUT
Test
Typ Max Units
Input Pulse Levels
0.1 * VCC - 0.9 * VCC
Output Capacitance
3
8
pF
Timing Measurement Reference Level 0.3 * VCC - 0.7 * VCC
CIN
Input Capacitance
2
6
pF
Note 5: Stress above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Note 6: The fOP frequency specification specifies a minimum clock period of 1/fOP. Therefore, for every fOP clock cycle, tCLH + tCLL must be equal to or greater than 1/fOP. For
example, for a fOP of 1MHz, the period equals 1000ns. In this case if tCLH = is set to 410ns, then tCLL must be set to a minimum of 590ns.
Note 7: /CS must be brought high for a minimum of tCSH between consecutive instruction cycles.
Note 8: This parameter is periodically sampled and not 100% tested.
4
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FM25C020U Rev. B
FIGURE 1. Synchronous Data Timing Diagram
t
CSI
/CS
t
t
t
t
CSH
CSS
CLH
CLL
Mode 3
Mode 0
Mode 3
Mode 0
SCK
SI
t
t
DIH
DIS
Valid Input
t
t
t
DF
PD
DH
High Z
SO
Valid Output
FIGURE 2. SPI Protocol
/CS
Mode 3
Mode 3
SCK
Don't Care
SI
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
High Z
SO
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
FIGURE 3. HOLD Timing
CS
Low state ( /CS = 0)
t
t
t
t
HDH
HDS HDH
HDS
Don't Care
SCK
/HOLD
t
t
LZ
HZ
High Z
Output (n+2)
Output (n+1)
Input (n+1)
Output (n)
Output (n)
Input (n)
SO
t
DIS
Input (n+2)
Input (n)
Don't Care
SI
5
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FM25C020U Rev. B
Pin Description
Functional Description
The Serial Peripheral Interface (SPI) of FM25C020U consists of
an 8-bit Instruction register to decode a specific instruction to be
executed. Six different instructions (Opcodes) are incorporated
on FM25C020U for various operations. Table2 lists the instruc-
tions set and the format for proper operation. All Opcodes, Array
addresses and Data are transferred in “MSB first-LSB last”
fashion. Detailed information is provided under individual instruc-
tion descriptions.
Chip Select (/CS)
This is an active low input pin to the EEPROM and is generated by
a master that is controlling the EEPROM. A low level on this pin
selects the EEPROM and a high level deselects the EEPROM. All
serial communications with the EEPROM is enabled only when
this pin is held low.
Serial Clock (SCK)
TABLE 2. Instruction Set
ThisisaninputpintotheEEPROMandisgeneratedbythemaster
that is controlling the EEPROM. This is a clock signal that
synchronizes the communication between a master and the
EEPROM. All input information (SI) to the EEPROM is latched on
the rising edge of this clock input, while output data (SO) from the
EEPROM is driven after the falling edge of this clock input.
Instruction Instruction
Operation
Name
WREN
WRDI
Opcode
00000110
00000100
00000101
00000001
00000011
Write Enabled
Write Disabled
Serial Input (SI)
RDSR
WRSR
READ
Read Status Register
Write Status Register
ThisisaninputpintotheEEPROMandisgeneratedbythemaster
that is controlling the EEPROM. The master transfers Input
information (Instruction Opcodes, Array addresses and Data)
serially via this pin into the EEPROM. This Input information is
latched on the rising edge of the SCK.
Read Data from Memory
Array
WRITE
00000010
Write Data to Memory Array
Serial Output (SO)
In addition to the Instruction register, FM25C020U also contains
an8-bitStatusregisterthatcanbeaccessedbyRDSRandWRSR
instructions. Only the least significant (LSB) 4 bits are defined at
present and the most significant (MSB) 4 bits are undefined (don’t
care).TheLSB4bitsdefineBlockWriteProtectionlevels(BP1and
BP0), Write-enable status (WEN) and Busy/Rdy status (/RDY) of
the EEPROM. Table 3 illustrates the format:
This is an output pin from the EEPROM and is used to transfer
Output data via this pin to the controlling master. Output data is
serially shifted out on this pin after the falling edge of the SCK.
Hold (/HOLD)
This is an active low input pin to the EEPROM and is generated by
the master that is controlling the EEPROM. When driven low, this
pin suspends any current communication with the EEPROM. The
suspended communication can be resumed by driving this pin
high. This feature eliminates the need to re-transmit the entire
sequence by allowing the master to resume the communication
from where it was left off. This pin should be tied high if this feature
is not used. Refer Hold Function description for additional
details.
TABLE 3. Status Register Format
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
X
X
X
X
BP1
BP0 WEN RDY
Refer RDSR and WRSR instruction descriptions for additional
information on Status register operations.
Write Protect (/WP)
This is an active low input pin to the EEPROM. This pin allows
enabling and disabling of writes to memory array and status
register of the EEPROM. When this pin is held low, writes to the
memory array and status register are disabled. When this pin is
held high, writes to the memory array and status register are
enabled. Status of this pin does not affect operations other than
array write and status register write. /WP signal going low at any
time will inhibit programming, except when an internal write has
already begun. If an internal write cycle has already begun, /WP
signal going low will have no effect on the write. Refer Table1 for
Write Protection matrix.
Table1. Write Protection Matrix
Protected Blocks
/WP Pin
Low
WEN Bit
Status Register
Write Protected
Write Protected
Write Allowed
(by BP1-BP0)
Write Protected
Write Protected
Write Protected
Unprotected Blocks
Write Protected
X
0
1
High
Write Protected
High
Write Allowed
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FM25C020U Rev. B
SPI Modes 0 and 3 (00 and 11)
Functional Description (Continued)
FM25C020U supports both Mode 0 and Mode 3 of operations.
The difference between Mode 0 and Mode 3 is determined by the
state of the SCK clock signal when a SPI cycle starts (when /CS
is driven low) as well as when the SPI cycle ends (when /CS is
drivenhigh).UnderMode0ofoperation,theSCKsignalisheldlow
both at the start and at the end of a SPI cycle. Under Mode 1 of
operation, the SCK signal is held high both at the start and at the
end of a SPI cycle. However in both of these two modes, the input
data(SI)issampled(latchedin)attherisingedgeoftheSCKclock
signal and the output data (SO) is driven after the falling edge of
the SCK clock signal. See Figure 1 and Figure 2.
SPI communication
As mentioned before, serial communication with the EEPROM is
enabled when the /CS pin is held low and the /HOLD pin is held
high. Input data (Instruction Opcodes, Array addresses and Data)
on the SI pin is latched in on the rising edges of SCK clock signal,
startingfromthefirstrisingedgeafterthe/CSpingoeslow. During
the time the SI data is input into the EEPROM, the SO pin remains
in high impedance state. If the intended instruction is of read
nature (Array read and Status register read), then data from the
EEPROM is driven out actively on the SO pin from every falling
edge of the SCK after the last input data (SI) is latched in. During
the time the SO data is output from the EEPROM, the data on the
SI pin is ignored. Figure 2 illustrates the above. Refer Figure 1 for
timing information.
READ SEQUENCE (READ)
Reading the memory via the serial SPI link requires the following
sequence. The /CS pin is pulled low to select the EEPROM. The
READ opcode is transmitted on the SI pin followed by the byte
address (A7–A0) to be read. After this is done, data on the SI pin
becomes don’t care. The data (D7–D0) at the address specified is
then shifted out on the SO pin. If only one byte is to be read, the
/CS pin can be pulled back to the high level. It is possible to
continuetheREADsequenceasthebyteaddressisautomatically
incremented and data will continue to be shifted out as clock
pulses are continuously applied. When the end of memory array
isreached(lastbytelocation),theaddresscounterrollsovertothe
start of memory array (first byte location) allowing the entire
memory to be read in one continuous READ cycle. See Figure 5.
HOLD function
An active communication with the EEPROM can be temporarily
suspended by bringing the /HOLD pin low when a EEPROM is
selected (/CS pin should be low) and a serial sequence with the
EEPROM is currently underway. To suspend the communication,
/HOLDpinmustbedrivenlowwhileSCKislow,otherwisetheHold
function will not be invoked until the next SCK high to low
transition. The EEPROM must remain selected during this se-
quence. TransitionsontheSCKandSIpinsareignoredduringthe
time the part is suspended and the SO pin will be in high
impedance state. Releasing the /HOLD pin back to high state will
allow the operation to resume from the point it was suspended.
/HOLD pin must be driven high while the SCK pin is low, otherwise
serial communication will not resume until the next SCK high to
low transition. Asserting a low on the /HOLD pin at any time will tri-
state the SO pin. Figure 3 illustrates Hold timing.
FIGURE 5. Read Sequence
/CS
Read
Opcode
Byte
Addr
SI
System Configuration
Data
(1)
Data
(2)
Data
(n)
SO
WhenmultipleSPIperipherals(fore.g.EEPROMs)arepresenton
the bus, the SI, SO and the SCK signals can be tied together.
Figure 4 illustrates a typical system configuration with respect to
/CS, SCK, SI and SO pins.
READ STATUS REGISTER (RDSR):
The Read Status Register (RDSR) instruction provides read
access to the status register. As mentioned before, of the 8bits of
data, only the LSB 4bits are valid and they indicate Block Protec-
tion information (BP1 and BP0), Write Enable status (WEN) and
Busy/Ready status (/RDY) of the EEPROM. MSB 4bits of are
invalid (Don’t cares) Following is the format of RDSR data:
FIGURE 4. System Configuration
MASTER MCU
FM25Cxxx
DATA OUT (MOSI)
SI
DATA IN (MISO)
TABLE 3. Status Register Format
SO
SERIAL CLOCK (SPICK)
SCK
Bit
7
X
Bit
6
X
Bit
5
X
Bit
4
X
Bit
3
BP1
Bit
2
Bit
1
Bit
0
SS0
SS1
SS2
SS3
/CS
BP0 WEN RDY
SPI
SI
SO
SCK
/CS
CHIP
SELECTION
Bit3 (BP1) and Bit2 (BP0) together indicate Block write protection
previously set on the EEPROM. Refer Table 2.
Bit1 (WEN) indicates the Write enable status of the EEPROM.
This bit is a read-only bit and is read by executing RDSR
instruction. If this bit is “1” then the EEPROM is write enabled. If
this bit is “0” then the EEPROM is write disabled.
SI
SO
SCK
/CS
Bit0 (/RDY) indicates the Busy/Ready status of the EEPROM.
This bit is a read-only bit and is read by executing RDSR
instruction. If this bit is “1” then the EEPROM is busy doing a
program cycle. If this bit is “0” then the EEPROM is ready.
SI
SO
SCK
/CS
Note that if a RDSR instruction is executed when an internal
programming cycle is in progress, only the /RDY bit is valid.
All other bits are don’t cares.
7
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FM25C020U Rev. B
The RDSR command requires the following sequence. The /CS
pin is pulled low to select the EEPROM and then the RDSR
opcode is transmitted on the SI pin. After this is done, data on the
SI pin becomes don’t care. The data from the Status Register is
then shifted out on the SO pin starting with D7 bit first and D0 last.
See Figure 6.
TABLE 4. Block Write Protection Levels
Level
Status Register Bits
Array
Address
Protected
None
BP1
BP0
0
0
1
2
3
0
0
1
1
1
0
1
C0-FF
80-FF
00-FF
FIGURE 6. Read Status Register
/CS
RDSR
OP-CODE
SI
A WRITE command requires the following sequence. The /CS pin
is pulled low to select the EEPROM, then the WRITE opcode is
transmittedontheSIpinfollowedbythebyteaddress(A7-A0)and
followed by the data (D7-D0) to be written. See Figure 9.
SO
RDSR DATA
WRITE ENABLE (WREN):
FIGURE 9. Byte Write
When VCC is applied to the EEPROM, it “powers up” in a write-
disabledstate.Therefore,allprogrammingmodes(Writetomemory
array and Status register), must be preceded by a WRITE EN-
ABLE (WREN) instruction. See Figure 7.
/CS
Write
Op-Code
Byte
Addr
Data
FIGURE 7. Write Enable
SI
/CS
High Z
SO
SI
Internally, the programming will start after the /CS pin is brought
back to a high level. Note that the LOW to HIGH transition of the
/CS pin must occur during the SCK low time immediately after
clocking in the D0 data bit. See Figure 10.
WREN Op-Code
SO
FIGURE 10. Start of Programming
WRITE DISABLE (WRDI):
Executing this instruction disables all programming modes (Write
to memory array and Status register), preventing the EEPROM
from accidental writes. Once WRDI instruction is executed,
WREN instruction should be executed to re-enable all program-
ming modes. See Figure 8.
/CS
Start of internal
programming
SCK
FIGURE 8. Write Disable
D2
D1
D0
SI
/CS
High Z
SO
Programming status (Busy/Ready) of the EEPROM can be deter-
mined by executing a READ STATUS REGISTER (RDSR) in-
struction after a write command. Upon executing the RDSR
instruction, if Bit 0 of the RDSR data is “1”, it indicates the WRITE
cycleisstillinprogress. Ifitis“0”thentheWRITEcyclehasended.
Note that while the internal programming is still in progress (Bit 0
= 1), only the RDSR instruction is enabled. It is recommended that
no other instruction be issued till the internal programming is
complete.
SI
WRDI Op-Code
SO
WRITE SEQUENCE (WRITE):
Write to the array is enabled only when /WP pin is held high and
the EEPROM is write enabled previously (via WREN instruction).
Also, the address of the memory location(s) to be programmed
must be outside the protected address field selected by the Block
Write Protection Level. See Table 4.
8
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FM25C020U Rev. B
The FM25C020U is also capable of a 4 byte PAGE WRITE
operation. Page write is performed similar to byte write operation
describedabove.DuringaPagewriteoperation,afterthefirstbyte
of data, additional bytes (up to 3 bytes) can be input, before
bringing the /CS pin high to start the programming. After receipt of
each byte of data, the EEPROM internally increments the two low
order address bits (A1-A0) by one. The high order address bits
(A7-A2) will remain constant. If the master should transmit more
than 4 bytes of data, the address counter (A1-A0) will “roll over”
and the previously loaded data will be reloaded. See Figure 11.
FIGURE 12. Write Status Register
/CS
WRSR
Op-Code
SR Data
xxxxBP1BP0xx
SI
SO
FIGURE 11. Page Write
Programming will start after the /CS pin is forced back to a high
level. As in the WRITE instruction the LOW to HIGH transition of
the /CS pin must occur during the SCK low time immediately after
clocking in the last don’t care bit. See Figure 13.
/CS
Write
Op-Code
Byte
Addr
Data
(1)
Data
(2)
Data
(3)
Data
(4)
FIGURE 13. Start WRSR Condition
SI
/CS
SO
SCK
At the completion of a write cycle the EEPROM is automatically
returnedtothewritedisabledstate.NotethatiftheEEPROMisnot
write enabled (WEN=0) before issuing the WRITE instruction, the
EEPROM will ignore the WRITE instruction and return to the
standby state when /CS is brought high.
BP0
SI
WRITE STATUS REGISTER (WRSR):
SO
The Write Status Register (WRSR) instruction provides write
access to the status register. This instruction is used to set Block
Write protection to a portion of the array as defined under Table
4. During a WRSR instruction only Bit3 (BP1) and Bit2 (BP0) can
be written with valid information while other bits are ignored.
Following is the format of WRSR data:
At the completion of this instruction the EEPROM is automatically
returned to write disabled state.
INVALID OPCODE
If an invalid code is received, then no data is shifted into the
EEPROM, and the SO data output pin remains high impedance
state until a new /CS falling edge reinitializes the serial communi-
cation. See Figure 14.
Status Register Write Data
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
FIGURE 14. Invalid Op-Code
X
X
X
X
BP1
BP0
X
X
X = Don’t Care
/CS
Note that the first four bits are don’t care bits followed by BP1 and
BP0 and two more don’t care bits.
SI
INVALID CODE
WRSR instruction is enabled only when /WP pin is held high and
the EEPROM is write enabled previously (via WREN instruction).
WRSR command requires the following sequence. The /CS pin is
pulled low to select the EEPROM and then the WRSR opcode is
transmitted on the SI pin followed by the data to be programmed.
See Figure 12.
SO
9
www.fairchildsemi.com
FM25C020U Rev. B
Physical Dimensions inches (millimeters) unless otherwise noted
0.189 - 0.197
(4.800 - 5.004)
8
7
6
5
0.228 - 0.244
(5.791 - 6.198)
1
2
3
4
Lead #1
IDENT
0.150 - 0.157
(3.810 - 3.988)
0.053 - 0.069
(1.346 - 1.753)
0.010 - 0.020
(0.254 - 0.508)
0.004 - 0.010
(0.102 - 0.254)
x 45°
8° Max, Typ.
All leads
Seating
Plane
0.004
(0.102)
All lead tips
0.0075 - 0.0098
(0.190 - 0.249)
Typ. All Leads
0.014
(0.356)
0.016 - 0.050
(0.406 - 1.270)
Typ. All Leads
0.050
(1.270)
Typ
0.014 - 0.020
Typ.
(0.356 - 0.508)
Molded Small Out-Line Package (M8)
Package Number M08A
0.373 - 0.400
(9.474 - 10.16)
0.090
(2.286)
8
1
7
0.032 0.005
(0.813 0.127)
RAD
8
7
6
5
4
0.092
DIA
(2.337)
0.250 - 0.005
(6.35 0.127)
Pin #1
IDENT
+
Pin #1 IDENT
Option 1
1
2
3
Option 2
0.280
MIN
0.040
(1.016)
Typ.
(7.112)
0.030
0.145 - 0.200
(3.683 - 5.080)
0.039
(0.991)
MAX
(0.762)
0.300 - 0.320
(7.62 - 8.128)
20° 1°
0.130 0.005
(3.302 0.127)
0.125 - 0.140
95° 5°
(3.175 - 3.556)
0.065
(1.651)
0.125
(3.175)
DIA
0.020
90° 4°
Typ
0.009 - 0.015
(0.508)
Min
(0.229 - 0.381)
NOM
0.018 0.003
(0.457 0.076)
+0.040
-0.015
0.325
0.100 0.010
+1.016
-0.381
8.255
(2.540 0.254)
0.045 0.015
(1.143 0.381)
0.060
(1.524)
0.050
(1.270)
Molded Dual-In-Line Package (N)
Package Number N08E
10
www.fairchildsemi.com
FM25C020U Rev. B
Physical Dimensions inches (millimeters) unless otherwise noted
0.114 - 0.122
(2.90 - 3.10)
8
5
(7.72) Typ
(4.16) Typ
0.169 - 0.177
(4.30 - 4.50)
0.246 - 0.256
(6.25 - 6.5)
(1.78) Typ
(0.42) Typ
0.123 - 0.128
(3.13 - 3.30)
(0.65) Typ
Land pattern recommendation
1
4
Pin #1 IDENT
0.0433
Max
(1.1)
0.0035 - 0.0079
See detail A
0.002 - 0.006
(0.05 - 0.15)
0.0256 (0.65)
Typ.
Gage
plane
0.0075 - 0.0118
(0.19 - 0.30)
0°-8°
DETAIL A
Typ. Scale: 40X
0.0075 - 0.0098
(0.19 - 0.25)
0.020 - 0.028
(0.50 - 0.70)
Seating
plane
Note: Metal mask option for 16-byte page size.
Notes: Unless otherwise specified
1. Reference JEDEC registration MO153. Variation AA. Dated 7/93
8-Pin Molded TSSOP, JEDEC (MT8)
Package Number MTC08
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written
approval of the President of Fairchild Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which,
(a)areintendedforsurgicalimplantintothebody,or(b)support
or sustain life, and whose failure to perform, when properly
used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant
injury to the user.
2. A critical component is any component of a life support device
or system whose failure to perform can be reasonably ex-
pected to cause the failure of the life support device or system,
or to affect its safety or effectiveness.
Fairchild Semiconductor
Americas
Fairchild Semiconductor
Europe
Fairchild Semiconductor
Hong Kong
Fairchild Semiconductor
Japan Ltd.
Customer Response Center
Tel. 1-888-522-5372
Fax:
Tel:
Tel:
Tel:
Tel:
+44 (0) 1793-856858
8/F, Room 808, Empire Centre
68 Mody Road, Tsimshatsui East
Kowloon. Hong Kong
Tel; +852-2722-8338
Fax: +852-2722-8383
4F, Natsume Bldg.
Deutsch
English
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+49 (0) 8141-6102-0
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Tokyo, 113-0034 Japan
Tel: 81-3-3818-8840
Fax: 81-3-3818-8841
11
www.fairchildsemi.com
FM25C020U Rev. B
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