FM27C040V90 [FAIRCHILD]

4,194,304-Bit 512K x 8 High Performance CMOS EPROM; 4,194,304位512K ×8的高性能CMOS EPROM


型号：	FM27C040V90
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	4,194,304-Bit 512K x 8 High Performance CMOS EPROM 4,194,304位512K ×8的高性能CMOS EPROM 存储内存集成电路可编程只读存储器 OTP只读存储器电动程控只读存储器
文件：	总11页 (文件大小：108K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

January 2000

FM27C040

4,194,304-Bit (512K x 8) High Performance

CMOS EPROM

General Description

Features

The FM27C040 is a high performance, 4,194,304-bit Electrically

Programmable UV Erasable Read Only Memory. It is organized

as 512K words of 8 bits each. Its pin-compatibility with byte-wide

JEDEC EPROMs enables upgrades through 8 Mbit EPROMs.

The “Don’t Care” feature on V_PPduring read operations allows

memory expansions from 1M to 8 Mbits with no printed circuit

board changes.

I High performance CMOS

—120, 150ns access time*

I Simplified upgrade path

—V_PPis a “Don’t Care” during normal read operation

I Manufacturer’s identification code

I JEDEC standard pin configuration

—32-pin PDIP

The FM27C040 provides microprocessor-based systems exten-

sive storage capacity for large portions of operating system and

application software. Its 120ns access time provides high speed

operation with high-performance CPUs. The FM27C040 offers a

single chip solution for the code storage requirements of 100%

firmware-based equipment. Frequently used software routines

are quickly executed from EPROM storage, greatly enhancing

system utility.

—32-pin PLCC

—32-pin CERDIP

TheFM27C040ismanufacturedusingFairchild’sadvancedCMOS

AMG™ EPROM technology.

*Note: New revision meets 70ns. Please check with factory for availability.

Block Diagram

Data Outputs O - O

GND

Output Enable,

Chip Enable, and

Program Logic

Output

Buffers

CE/PGM

Y Decoder

Y Gating

- A

Address

Inputs

4,194,304-Bit

Cell Matrix

X Decoder

DS800033-1

AMG™ is a trademark of WSI, Inc.

FM27C040 Rev. A

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Connection Diagrams

27C010

FM27C040

27C010

XX/V

XX/PGM

GND

CE/PGM

GND

DS800033-2

Note:

Compatible EPROM pin configurations are shown in the blocks adjacent to the FM27C040 pin.

Commercial Temperature Range

(0°C to +70°C) V_CC= 5V 10%

Extended Temperature Range

(-40°C to +85°C) V_CC= 5V 10%

Parameter/Order Number Access Time (ns)

FM27C040 Q, N, V 90

FM27C040 Q, N, V 120

FM27C040 Q, N, V 150

FM27C040 QE, NE, VE 90

FM27C040 QE, NE, VE 120

FM27C040 QE, NE, VE 150

120

150

120

150

Package Types: FM27C040 Q, N,V XXX

Q = Quartz-Windowed Ceramic DIP

N = Plastic DIP

• All versions are guaranteed to function for slower speeds.

Pin Names

A0–A18

CE/PGM

Addresses

V = PLCC

Chip Enable/Program

Output Enable

• All packages conform to the JEDEC standard.

O0–O7

Outputs

Don’t Care (During Read)

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FM27C040 Rev. A

All Output Voltages with

Respect to Ground

Absolute Maximum Ratings (Note 1)

V_CC+1.0V to GND - 0.6V

Storage Temperature

-65°C to +150°C

Operating Range

All Input Voltages except A9 with

Respect to Ground

-0.6V to +7V

-0.6V to +14V

Range

Commercial

Industrial

Temperature

V_CC

+5V

Tolerance

10%

V_PPand A9 with Respect to Ground

0°C to +70°C

V_CCSupply Voltage with

Respect to Ground

-40°C to +85°C

10%

-0.6V to +7V

>2000V

ESD Protection

Read Operation

DC Electrical Characteristics Over operating range with V_PP= V_CC

Symbol

V_IL

Parameter

Test Conditions

Min

-0.5

2.0

Max

0.8

Units

Input Low Level

V_IH

Input High Level

V_CC+1

0.4

V_OL

Output Low Voltage

Output High Voltage

V_CCStandby Current (CMOS)

V_CCStandby Current

V_CCActive Current

I_OL= 2.1 mA

V_OH

I_SB1

I_OH= -2.5 mA

CE = V_CC0.3V

CE = V_IH

3.5

100

µA

I_SB2

I_CC

CE = OE = V_IL,

I/O = 0 mA

f=5 MHz

I_PP

V_PP

I_LI

V_PPSupply Current

V_PPRead Voltage

V_PP= V_CC

V_CC

µA

V_CC- 0.4

-1

Input Load Current

Output Leakage Current

V_IN= 5.5V or GND

V_OUT= 5.5V or GND

µA

I_LO

-10

AC Electrical Characteristics Over operating range with V_PP= V_CC

Symbol

Parameter

120

150

Units

Min

Max

120

Min

Max

150

t_ACC

t_CE

Address to Output Delay

CE to Output Delay

OE to Output Delay

t_OE

t_DF

(Note 2)

Output Disable to

Output Float

t_OH

(Note 2)

Output Hold from Addresses CE or OE ,

Whichever Occurred First

Capacitance T_A= +25°C, f = 1 MHz (Note 2)

Symbol

C_IN

Parameter

Conditions

V_IN= 0V

Typ

Max Units

Input Capacitance

C_OUT

Output Capacitance

V_OUT= 0V

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FM27C040 Rev. A

AC Test Conditions

Output Load

1 TTL Gate and C_L= 100 pF (Note 8)

Input Rise and Fall Times

Input Pulse Levels

≤5 ns

0.45V to 2.4V

Timing Measurement Reference Level (Note 10)

Inputs

Outputs`

0.8V and 2V

AC Waveforms (Notes 6, 7, 9)

ADDRESSES

Addresses Valid

0.8V

(Note 4, 5)

0.8V

(Note 4, 5)

(Note 3)

Hi-Z

Valid Output

OUTPUT

0.8V

ACC

(Note 3)

DS800033-4

Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of

the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions

for extended periods may affect device reliability.

Note 2: This parameter is only sampled and is not 100% tested.

Note 3: OE may be delayed up to t_ACC- t_OEafter the falling edge of CE without impacting t_ACC

Note 4: The t_DFand t_CFcompare level is determined as follows:

High to TRI-STATE^®, the measured V_OH1(DC) - 0.10V;

Low to TRI-STATE, the measured V_OL1(DC) + 0.10V.

Note 5: TRI-STATE may be attained using OE or CE .

Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 µF ceramic capacitor be used on every device

between V_CCand GND.

Note 7: The outputs must be restricted to V_CC+ 1.0V to avoid latch-up and device damage.

Note 8: 1 TTL Gate: I_OL= 1.6 mA, I_OH= -400 µA.

C_L: 100 pF includes fixture capacitance.

Note 9:

V_PPmay be connected to V_CCexcept during programming.

Note 10: Inputs and outputs can undershoot to -2.0V for 20 ns Max.

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FM27C040 Rev. A

Programming Waveform (Note 13)

Program

Verify

Program

Address N

ADDRESSES

0.8V

Hi-Z

Data In Stable

Data Out Valid

DATA

ADD

0.8V

6.25V

VCS

12.75V

VPS

0.8V

CE/PGM

OES

0.8V

DS800033-5

Programming Characteristics (Notes 11, 12, 13, 14)

Symbol

t_AS

Parameter

Conditions

Min

Typ

Max

Units

µs

Address Setup Time

t_OES

t_DS

OE Setup Time

µs

Data Setup Time

µs

t_VPS

t_VCS

t_AH

V_PPSetup Time

µs

V_CCSetup Time

µs

Address Hold Time

Data Hold Time

µs

t_DH

µs

t_DF

Output Enable to Output Float Delay

Program Pulse Width

Data Valid from OE

CE/PGM = X

105

100

t_PW

µs

t_OE

CE/PGM = X

I_PP

V_PPSupply Current during

Programming Pulse

CE/PGM = V_IL

I_CC

T_A

V_CCSupply Current

°C

Temperature Ambient

Power Supply Voltage

Programming Supply Voltage

Input Rise, Fall Time

6.25

12.5

6.5

V_CC

V_PP

t_FR

6.75

13.0

12.75

V_IL

V_IH

t_IN

Input Low Voltage

-0.1

2.4

0.8

0.0

4.0

0.45

Input High Voltage

Input Timing Reference Voltage

Output Timing Reference Voltage

2.0

t_OUT

Note 11: Fairchild’s standard product warranty applies only to devices programmed to specifications described herein.

Note 12: V_CCmust be applied simultaneously or before V_PPand removed simultaneously or after V_PP. The EPROM must not be inserted into or removed from a board with

voltage applied to V_PPor V_CC

Note 13: The maximum absolute allowable voltage which may be applied to the V_PPpin during programming is 14V. Care must be taken when switching the V_PPsupply to

prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 µF capacitor is required across V_PP, V_CCto GND to suppress spurious voltage transients

which may damage the device.

Note 14: During power up the CE/PGM pin must be brought high (≥V_IH) either coincident with or before power is applied to V_PP

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FM27C040 Rev. A

Turbo Programming Algorithm Flow Chart

V_CC= 6.5V V_PP= 12.75V

n = 0

ADDRESS = FIRST LOCATION

PROGRAM ONE 50µs PULSE

INCREMENT n

YES

FAIL

DEVICE

FAILED

VERIFY

BYTE

n = 10?

PASS

INCREMENT

ADDRESS

n = 0

LAST

ADDRESS

YES

ADDRESS = FIRST LOCATION

FAIL

VERIFY

BYTE

PASS

PROGRAM ONE

50 µs

INCREMENT

ADDRESS

PULSE

LAST

ADDRESS

YES

CHECK ALL BYTES

1ST: V_CC= V_PP= 6.0V

2ND: V_CC= V_PP= 4.3V

DS800033-6

Note:

The standard National Semiconductor algorithm may also be used with it will have longer programming time.

FIGURE 1.

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FM27C040 Rev. A

supply is at 12.75V and OE is at V_IH. It is required that at least a

0.1 µF capacitor be placed across V_PP, V_CCto ground to suppress

spurious voltage transients which may damage the device. The

data to be programmed is applied 8 bits in parallel to the data

output pins. The levels required for the address and data inputs

are TTL.

Functional Description

DEVICE OPERATION

The six modes of operation of the EPROM are listed in Table 1. It

should be noted that all inputs for the six modes are at TTL levels.

The power supplies required are V_CCand V_PP. The V_PPpower

supply must be at 12.75V during the three programming modes,

andmustbeat5Vintheotherthree modes. TheV_CCpowersupply

must be at 6.25V during the three programming modes, and at 5V

in the other three modes.

Whentheaddressanddataarestable,anactivelow,TTLprogram

pulse is applied to the CE/PGM input. A program pulse must be

applied at each address location to be programmed. The EPROM

is programmed with the Turbo Programming Algorithm shown in

Figure 1. Each Address is programmed with a series of 50 µs

pulses until it verifies good, up to a maximum of 10 pulses. Most

memorycellswillprogramwithasingle50µspulse.(Thestandard

National Semiconductor Algorithm may also be used but it will

have longer programming time.)

Read Mode

The EPROM has two control functions, both of which must be

logically active in order to obtain data at the outputs. Chip Enable

(CE/PGM) is the power control and should be used for device

selection. Output Enable (OE) is the output control and should be

used to gate data to the output pins, independent of device

selection. Assuming that addresses are stable, address access

time (t_ACC) is equal to the delay from CE to output (t_CE). Data is

available at the outputs tOE after the falling edge of OE, assuming

that CE/PGM has been low and addresses have been stable for

The EPROM must not be programmed with a DC signal applied to

the CE/PGM input.

Programming multiple EPROM in parallel with the same data can

be easily accomplished due to the simplicity of the pro-gramming

requirements. Like inputs of the parallel EPROM may be con-

nected together when they are programmed with the same data.

A low level TTL pulse applied to the CE/PGM input programs the

paralleled EPROM.

at least t_ACC-t_OE

Standby Mode

The EPROM has a standby mode which reduces the active power

dissipation by over 99%, from of 65 mW to 0.55 mW. The EPROM

is placed in the standby mode by applying a CMOS high signal to

the CE/PGM input. When in standby mode, the outputs are in a

high impedance state, independent of the OE input.

Program Inhibit

Programming multiple EPROMs in parallel with different data is

also easily accomplished. Except for CE/PGM all like in-puts

(including OE) of the parallel EPROMs may be com-mon. A TTL

low level program pulse applied to an EPROM’s CE/PGM input

withV_PPat12.75VwillprogramthatEPROM. ATTLhighlevelCE/

PGM input inhibits the other EPROMs from being programmed.

Output Disable

The EPROM is placed in output disable by applying a TTL high

signal to the OE input. When in output disable all circuitry is

enabled, except the outputs are in a high impedance state (TRI-

STATE).

Program Verify

Averifyshouldbeperformedontheprogrammedbitstodetermine

whether they were correctly programmed. The verify may be

performed with V_PPat 12.75V. V_PPmust be at V_CC, except during

programming and program verify.

Output OR-Typing

Because the EPROM is usually used in larger memory arrays,

Fairchild has provided a 2-line control function that accommo-

dates this use of multiple memory connections. The 2-line control

function allows for:

AFTER PROGRAMMING

Opaque labels should be placed over the EPROM window to

prevent unintentional erasure. Covering the window will also

preventtemporaryfunctionalfailureduetothegenerationofphoto

currents.

1. the lowest possible memory power dissipation, and

2. complete assurance that output bus contention will not occur.

To most efficiently use these two control lines, it is recommended

that CE/PGM be decoded and used as the primary device select-

ing function, while OE be made a common connection to all

devices in the array and connected to the READ line from the

system control bus. This assures that all deselected memory

devices are in their low power standby modes and that the output

pinsareactiveonlywhendataisdesiredfromaparticularmemory

device.

MANUFACTURER’S IDENTIFICATION CODE

The EPROM has a manufacturer’s identification code to aid in

programming. When the device is inserted in an EPROM pro-

grammer socket, the programmer reads the code and then

automatically calls up the specific programming algorithm for the

part. This automatic programming control is only possible with

programmers which have the capability of reading the code.

The Manufacturer’s Identification code, shown in Table 2, specifi-

cally identifies the manufacturer and device type. The code for

FM27C040 is “8F08”, where “8F” designates that it is made by

Fairchild Semiconductor, and “08” designates a 4 Megabit (512K

x 8) part.

Programming

CAUTION:Exceeding14Vonpin1(V_PP)willdamagetheEPROM.

Initially, and after each erasure, all bits of the EPROM are in the

“1’s” state. Data is introduced by selectively programming “0’s”

into the desired bit locations. Although only “0’s” will be pro-

grammed, both “1’s” and “0’s” can be presented in the data word.

The only way to change a “0” to a “1” is by ultraviolet light erasure.

The code is accessed by applying 12V 0.5V to address pin A9.

Addresses A1–A8, A10–A18, and all control pins are held at V_IL.

Address pin A0 is held at V_ILfor the manufacturer’s code, and held

at V_IHfor the device code. The code is read on the eight data pins,

O0 –O7 . Proper code access is only guaranteed at 25°C 5°C.

The EPROM is in the programming mode when the V_PPpower

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FM27C040 Rev. A

be checked to make certain full erasure is occurring. Incomplete

erasure will cause symptoms that can be misleading. Program-

mers, components, and even system designs have been errone-

ously suspected when incomplete erasure was the problem.

Functional Description (Continued)

ERASURE CHARACTERISTICS

The erasure characteristics of the device are such that erasure

begins to occur when exposed to light with wavelengths shorter

than approximately 4000 Angstroms (Å). It should be noted that

sunlight and certain types of fluorescent lamps have wavelengths

in the 3000Å–4000Å range.

SYSTEM CONSIDERATION

The power switching characteristics of EPROMs require careful

decoupling of the devices. The supply current, I_CC, has three

segments that are of interest to the system designer: the standby

current level, the active current level, and the transient current

peaks that are produced by voltage transitions on input pins. The

magnitude of these transient current peaks is dependent of the

output capacitance loading of the device. The associated V_CC

transient voltage peaks can be suppressed by properly selected

decoupling capacitors. It is recommended that at least a 0.1 µF

ceramic capacitor be used on every device between V_CCand

GND. This should be a high frequency capacitor of low inherent

inductance. In addition, at least a 4.7 µF bulk electrolytic capacitor

shouldbeusedbetweenV_CCandGNDforeacheightdevices.The

bulk capacitor should be located near where the power supply is

connected to the array. The purpose of the bulk capacitor is to

overcome the voltage drop caused by the inductive effects of the

PC board traces.

The recommended erasure procedure for the EPROM is expo-

sure to short wave ultraviolet light which has a wavelength of

2537Å.Theintegrateddose(i.e.,UVintensityXexposuretime)for

erasure should be minimum of 15W-sec/cm².

The EPROM should be placed within 1 inch of the lamp tubes

during erasure. Some lamps have a filter on their tubes which

should be removed before erasure.

Anerasuresystemshouldbecalibratedperiodically.Thedistance

fromlamptodeviceshouldbemaintainedatoneinch.Theerasure

time increase as the square of the distance from the lamp. (If

distance is doubled the erasure time increases by factor of 4.)

Lamps lose intensity as they age. When a lamp is changed, the

distance has changed, or the lamp has aged, the system should

Mode Selection

The modes of operation of the FM27C040 are listed in Table 1. A single 5V power supply is required in the read mode. All inputs are TTL

levels except for V_PPand A9 for device signature.

TABLE 1. Modes Selection

Pins

CE/PGM

V_PP

V_CC

Outputs

Mode

Read

V_IL

5.0V

D_OUT

(Note 15)

Output Disable

Standby

V_IH

5.0V

High Z

D_IN

V_IH

V_IL

Programming

Program Verify

Program Inhibit

V_IH

V_IL

V_IH

12.75V

6.25V

D_OUT

V_IH

High Z

Note 15: X can be V_ILor V_IH

TABLE 2. Manufacturer’s Identification Code

Pins

Hex

(12)

(26)

(21)

(20)

(19)

(18)

(17)

(15)

(14)

(13)

Data

Manufacturer Code

Device Code

V_IL

12V

V_IH

12V

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FM27C040 Rev. A

Physical Dimensions inches (millimeters) unless otherwise noted

1.660 MAX

R 0.025

0.585

MAX

UV WINDOW SIZE AND

R 0.030-0.055

TYP

CONFIGURATION DETERMINED

BY DEVICE SIZE

0.050-0.060

TYP

0.590-0.620

0.10

MAX

0.005 MIN

TYP

Glass Sealant

0.175

MAX

0.225 MAX TYP

0.015 -0.060

TYP

0.125 MIN

TYP

90° - 100°

TYP

0.008-0.012

TYP

86°-94°

0.150 MIN

TYP

0.090-0.110

TYP

0.015-0.021

TYP

0.060-0.100

TYP

+0.025

-0.060

0.685

32-Lead EPROM Ceramic Dual-In-Line Package (Q)

Order Number FM27C040QXXX

Package Number J32AQ

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FM27C040 Rev. A

Physical Dimensions inches (millimeters) unless otherwise noted

0.485-0.495

[12.32-12.57]

-H-

Base

Plane

0.106-0.112

[2.69-2.84]

D-E

0.007[0.18]

0.449-0.453

[11.40-11.51]

0.023-0.029

[0.58-0.74]

0.015

[0.38]

Min Typ

-A-

0.045

[1.143]

D-E

0.007[0.18]

0.002[0.05]

0.000-0.010

[0.00-0.25]

Polished Optional

0.490-0530

[12.45-13.46]

0.400

[10.16]

-D-

(

)

0.541-0.545

[13.74-13-84]

D-E, F-G

0.015[0.38]

0.549-0.553

[13.94-14.05]

-G-

-B-

0.585-0.595

[14.86-15.11]

0.013-0.021

[0.33-0.53]

TYP

-F-

See detail A

-J-

D-E, F-G

0.007[0.18]

0.078-0.095

[1.98-2.41]

0.123-0.140

[3.12-3.56]

0.050

-E-

-C-

0.004[0.10]

0.002[0.05] S

0.007[0.18] S

0.005

[0.13]

Max

0.0100

[0.254]

F-G

0.020

[0.51]

F-G

0.007[0.18] S

0.118-0.129

[3.00-3.28]

0.045

[1.14]

0.030-0.040

[0.76-1.02]

B A D-E, F-G

0.025

[0.64]

0.010[0.25] L

Detail A

Typical

Rotated 90°

Min

0.042-0.048

[1.07-1.22]

45°X

0.025

[0.64]

0.021-0.027

[0.53-0.69]

Min

0.065-0.071

[1.65-1.80]

0.053-0.059

[1.65-1.80]

0.031-0.037

[0.79-0.94]

0.006-0.012

[0.15-0.30]

0.027-0.033

[0.69-0.84]

0.026-0.032

[0.66-0.81]

0.019-0.025

[0.48-0.64]

Typ

Section B-B

Typical

D-E, F-G

0.007[0.18] S

32-Lead PLCC Package (V)

Order Number FM27C040VXXX

Package Number VA32A

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FM27C040 Rev. A

Physical Dimensions inches (millimeters) unless otherwise noted

1.64 – 1.66

(41.66 – 42.164)

0.062

TYP

(1.575)

RAD

0.490 – 0.550

(12.446 – 13.97)

Pin No. 1 IDENT

0.580

(14.73)

MIN

0.050

(1.270)

TYP

0.125 – 0.165

(3.175 – 4.191)

0.600 – 0.620

(15.240 – 15.748)

0.145 – 0.210

(3.683 – 5.334)

86°- 94°

TYP

0.015

(0.381)

90°–105°

0.008 - 0.015

(0.203 – 0.381)

0.120 – 0.150

(3.048 – 3.81)

0.040 - 0.090

(1.016 – 2.286)

0.018 0.003

(0.457 0.078)

0.100 0.010

(2.540 0.254)

0.035 – 0.07

(0.889 – 1.778)

32-Lead PDIP Package

Order Number FM27C040NXXX

Life Support Policy

Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written

approval of the President of Fairchild Semiconductor Corporation. As used herein:

1. Life support devices or systems are devices or systems which,

(a)areintendedforsurgicalimplantintothebody,or(b)support

or sustain life, and whose failure to perform, when properly

used in accordance with instructions for use provided in the

labeling, can be reasonably expected to result in a significant

injury to the user.

2. A critical component is any component of a life support device

or system whose failure to perform can be reasonably ex-

pected to cause the failure of the life support device or system,

or to affect its safety or effectiveness.

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Fairchild Semiconductor

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Fairchild Semiconductor

Japan Ltd.

Customer Response Center

Tel. 1-888-522-5372

Fax:

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Tel: 81-3-3818-8840

Fax: 81-3-3818-8841

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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FM27C040 Rev. A

FM27C040V90 [FAIRCHILD]

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