FM93C06LVMT8 [FAIRCHILD]
Microwire Serial EEPROM ; Microwire串行EEPROM\n
| 型号： | FM93C06LVMT8 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Microwire Serial EEPROM
|
| 文件： | 总13页 (文件大小：116K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
July 2000
FM93C06
256-Bit Serial CMOS EEPROM
(MICROWIRE™ Synchronous Bus)
General Description
Features
FM93C06 is a 256-bit CMOS non-volatile EEPROM organized as
16 x 16-bit array. This device features MICROWIRE interface
which is a 4-wire serial bus with chipselect (CS), clock (SK), data
input (DI) and data output (DO) signals. This interface is compat-
ible to many of standard Microcontrollers and Microprocessors.
Thereare7instructionsimplementedontheFM93C06forvarious
Read, Write, Erase, and Write Enable/Disable operations. This
device is fabricated using Fairchild Semiconductor floating-gate
CMOS process for high reliability, high endurance and low power
consumption.
I Wide VCC 2.7V - 5.5V
I Typical active current of 200µA
10µA standby current typical
1µA standby current typical (L)
0.1µA standby current typical (LZ)
I No Erase instruction required before Write instruction
I Self timed write cycle
I Device status during programming cycles
I 40 year data retention
“LZ” and “L” versions of FM93C06 offer very low standby current
making them suitable for low power applications. This device is
offered in both SO and TSSOP packages for small space consid-
erations.
I Endurance: 1,000,000 data changes
I Packages available: 8-pin SO, 8-pin DIP, 8-pin TSSOP
Functional Diagram
VCC
CS
SK
INSTRUCTION
DECODER
CONTROL LOGIC
AND CLOCK
GENERATORS
INSTRUCTION
REGISTER
DI
HIGH VOLTAGE
GENERATOR
AND
PROGRAM
TIMER
ADDRESS
REGISTER
DECODER
EEPROM ARRAY
16
READ/WRITE AMPS
16
VSS
DATA IN/OUT REGISTER
16 BITS
DO
DATA OUT BUFFER
1
© 2000 Fairchild Semiconductor International
FM93C06 Rev. C.1
www.fairchildsemi.com
Connection Diagram
Dual-In-Line Package (N)
8–Pin SO (M8) and 8–Pin TSSOP (MT8)
1
2
3
4
8
7
6
5
CS
SK
DI
VCC
NC
NC
DO
GND
Top View
Package Number
N08E, M08A and MTC08
Pin Names
CS
SK
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
DI
DO
GND
NC
VCC
No Connect
Power Supply
NOTE: Pins designated as "NC" are typically unbonded pins. However some of them are bonded for special testing purposes. Hence if a signal is applied to these pins, care
should be taken that the voltage applied on these pins does not exceed the VCC applied to the device. This will ensure proper operation.
Ordering Information
FM
93
C
XX
LZ
E
XXX
Letter Description
Package
N
8-pin DIP
M8
MT8
8-pin SO
8-pin TSSOP
Temp. Range
None
0 to 70°C
V
E
-40 to +125°C
-40 to +85°C
Voltage Operating Range
Density
Blank
L
LZ
4.5V to 5.5V
2.7V to 5.5V
2.7V to 5.5V and
<1µA Standby Current
06
256 bits
C
CMOS
CS
Data protect and sequential
read
Interface
93
MICROWIRE
Fairchild Memory Prefix
2
www.fairchildsemi.com
FM93C06 Rev. C.1
Absolute Maximum Ratings (Note 1)
Operating Conditions
Ambient Storage Temperature
-65°C to +150°C
Ambient Operating Temperature
FM93C06
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
All Input or Output Voltages
with Respect to Ground
+6.5V to -0.3V
FM93C06E
FM93C06V
Lead Temperature
(Soldering, 10 sec.)
+300°C
Power Supply (VCC
)
4.5V to 5.5V
ESD rating
2000V
DC and AC Electrical Characteristics VCC = 4.5V to 5.5V unless otherwise specified
Symbol
Parameter
Conditions
Min
Max
Units
ICCA
Operating Current
CS = VIH, SK=1.0 MHz
1
mA
ICCS
Standby Current
CS = VIL
50
-1
µA
µA
IIL
IOL
Input Leakage
Output Leakage
VIN = 0V to VCC
(Note 2)
VIL
VIH
Input Low Voltage
Input High Voltage
-0.1
2
0.8
VCC +1
V
V
V
VOL1
VOH1
Output Low Voltage
Output High Voltage
IOL = 2.1 mA
IOH = -400 µA
0.4
0.2
1
2.4
VOL2
VOH2
Output Low Voltage
Output High Voltage
IOL = 10 µA
IOH = -10 µA
VCC - 0.2
fSK
SK Clock Frequency
SK High Time
(Note 3)
MHz
ns
tSKH
0°C to +70°C
-40°C to +125°C
250
300
tSKL
tCS
tCSS
tDH
SK Low Time
250
250
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Minimum CS Low Time
CS Setup Time
DO Hold Time
(Note 4)
70
tDIS
tCSH
tDIH
tPD
DI Setup Time
CS Hold Time
100
0
DI Hold Time
20
Output Delay
500
500
100
10
tSV
CS to Status Valid
CS to DO in Hi-Z
Write Cycle Time
tDF
CS = VIL
tWP
3
www.fairchildsemi.com
FM93C06 Rev. C.1
Absolute Maximum Ratings (Note 1)
Operating Conditions
Ambient Storage Temperature
-65°C to +150°C
Ambient Operating Temperature
FM93C06L/LZ
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
All Input or Output Voltages
with Respect to Ground
+6.5V to -0.3V
FM93C06LE/LZE
FM93C06LV/LZV
Lead Temperature
(Soldering, 10 sec.)
+300°C
Power Supply (VCC
)
2.7V to 5.5V
ESD rating
2000V
DC and AC Electrical Characteristics VCC = 2.7V to 4.5V unless otherwise specified. Refer to
page 3 for VCC = 4.5V to 5.5V.
Symbol
Parameter
Conditions
Min
Max
Units
ICCA
Operating Current
CS = VIH, SK=250 KHz
1
mA
ICCS
Standby Current
L
CS = VIL
10
1
µA
µA
LZ (2.7V to 4.5V)
IIL
IOL
Input Leakage
Output Leakage
VIN = 0V to VCC
(Note 2)
1
µA
VIL
VIH
Input Low Voltage
Input High Voltage
-0.1
0.8VCC
0.15VCC
VCC +1
V
VOL
VOH
Output Low Voltage
Output High Voltage
IOL = 10µA
IOH = -10µA
0.1VCC
V
0.9VCC
fSK
tSKH
tSKL
tCS
SK Clock Frequency
SK High Time
(Note 3)
0
1
250
KHz
µs
µs
µs
µs
ns
µs
ns
µs
µs
µs
µs
ms
SK Low Time
1
Minimum CS Low Time
CS Setup Time
DO Hold Time
(Note 4)
1
tCSS
tDH
0.2
70
0.4
0
tDIS
tCSH
tDIH
tPD
DI Setup Time
CS Hold Time
DI Hold Time
0.4
Output Delay
2
1
tSV
CS to Status Valid
CS to DO in Hi-Z
Write Cycle Time
tDF
CS = VIL
0.4
15
tWP
Note 1: Stressabovethoselistedunder“AbsoluteMaximumRatings”maycausepermanentdamage
to the device. This is a stress rating only and functional operation of the device at these or any other
conditionsabovethoseindicatedintheoperationalsectionsofthespecificationisnotimplied. Exposure
to absolute maximum rating conditions for extended periods may affect device reliability.
Capacitance TA = 25°C, f = 1 MHz or
250 KHz (Note 5)
Note 2: Typical leakage values are in the 20nA range.
Note 3: TheshortestallowableSKclockperiod=1/fSK (asshownunderthefSK parameter). Maximum
SK clock speed (minimum SK period) is determined by the interaction of several AC parameters stated
in the datasheet. Within this SK period, both tSKH and tSKL limits must be observed. Therefore, it is not
allowable to set 1/fSK = tSKHminimum + tSKLminimum for shorter SK cycle time operation.
Symbol
Test
Typ Max Units
COUT
CIN
Output Capacitance
Input Capacitance
5
5
pF
pF
Note 4: CS (Chip Select) must be brought low (to VIL) for an interval of tCS in order to reset all internal
device registers (device reset) prior to beginning another opcode cycle. (This is shown in the opcode
diagram on the following page.)
Note 5: This parameter is periodically sampled and not 100% tested.
AC Test Conditions
VCC Range
VIL/VIH
Input Levels
0.3V/1.8V
VIL/VIH
VOL/VOH
Timing Level
0.8V/1.5V
IOL/IOH
Timing Level
2.7V ≤ VCC ≤ 5.5V
1.0V
10µA
(Extended Voltage Levels)
4.5V ≤ VCC ≤ 5.5V
0.4V/2.4V
1.0V/2.0V
0.4V/2.4V
2.1mA/-0.4mA
(TTL Levels)
Output Load: 1 TTL Gate (CL = 100 pF)
4
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FM93C06 Rev. C.1
Pin Description
Microwire Interface
AtypicalcommunicationontheMicrowirebusismadethroughthe
CS, SK, DI and DO signals. To facilitate various operations on the
Memoryarray,asetof7instructionsareimplementedonFM93C06.
The format of each instruction is listed under Table 1.
Chip Select (CS)
This is an active high input pin to FM93C06 EEPROM (the device)
and is generated by a master that is controlling the device. A high
level on this pin selects the device and a low level deselects the
device. All serial communications with the device is enabled only
when this pin is held high. However this pin cannot be permanently
tied high, as a rising edge on this signal is required to reset the
internal state-machine to accept a new cycle and a falling edge to
initiateaninternalprogrammingafterawritecycle.Allactivityonthe
SK, DI and DO pins are ignored while CS is held low.
Instruction
Each of the 7 instructions is explained under individual instruction
descriptions.
Start bit
This is a 1-bit field and is the first bit that is clocked into the device
whenaMicrowirecyclestarts.Thisbithastobe“1”foravalidcycle
to begin. Any number of preceding “0” can be clocked into the
device before clocking a “1”.
Serial Clock (SK)
Thisisaninputpintothedeviceandisgeneratedbythemasterthat
is controlling the device. This is a clock signal that synchronizes the
communicationbetweenamasterandthedevice. Allinputinforma-
tion(DI)tothedeviceislatchedontherisingedgeofthisclockinput,
whileoutputdata(DO)fromthedeviceisdrivenfromtherisingedge
of this clock input. This pin is gated by CS signal.
Opcode
This is a 2-bit field and should immediately follow the start bit.
These two bits (along with 2 MSB of address field) select a
particular instruction to be executed.
Serial Input (DI)
Address Field
This is an input pin to the device and is generated by the master
that is controlling the device. The master transfers Input informa-
tion (Start bit, Opcode bits, Array addresses and Data) serially via
this pin into the device. This Input information is latched on the
rising edge of the SCK. This pin is gated by CS signal.
This is a 6-bit field and should immediately follow the Opcode bits.
In FM93C06, only the LSB bits are used for address decoding
during READ, WRITE and ERASE instructions. During these
three instructions (READ, WRITE and ERASE) the MSB 2 bits are
"don't care" (can be 0 or 1).During all other instructions, the MSB
2 bits are used to decode instruction (along with Opcode bits).
Serial Output (DO)
This is an output pin from the device and is used to transfer Output
data via this pin to the controlling master. Output data is serially
shifted out on this pin from the rising edge of the SCK. This pin is
active only when the device is selected.
Data Field
This is a 16-bit field and should immediately follow the Address
bits. Only the WRITE and WRALL instructions require this field.
D15 (MSB) is clocked first and D0 (LSB) is clocked last (both
during writes as well as reads).
Table 1. Instruction set
Instruction
READ
Start Bit Opcode Field
Address Field
Data Field
1
1
1
1
1
1
1
10
00
01
00
00
11
00
0
1
0
0
0
0
1
0
1
0
1
0
0
0
A3 A2 A1 A0
WEN
X
X
X
X
WRITE
WRALL
WDS
A3 A2 A1 A0
D15-D0
D15-D0
X
X
X
X
X
X
X
X
ERASE
ERAL
A3 A2 A1 A0
X
X
X
X
5
www.fairchildsemi.com
FM93C06 Rev. C.1
The status of the internal programming cycle can be polled at any
time by bringing the CS signal high again, after tCS interval. When
CS signal is high, the DO pin indicates the READY/BUSY status
of the chip. DO = logical 0 indicates that the programming is still
in progress. DO = logical 1 indicates that the programming is
finished and the device is ready for another instruction. It is not
required to provide the SK clock during this status polling. While
the device is busy, it is recommended that no new instruction be
issued. Refer Write cycle diagram.
Functional Description
A typical Microwire cycle starts by first selecting the device
(bringing the CS signal high). Once the device is selected, a valid
Start bit (“1”) should be issued to properly recognize the cycle.
Following this, the 2-bit opcode of appropriate instruction should
be issued. After the opcode bits, the 6-bit address information
shouldbeissued. Forcertaininstructions,someofthese6bitsare
don’tcarevalues(canbe“0”or“1”), buttheyshouldstillbeissued.
Following the address information, depending on the instruction
(WRITE and WRALL), 16-Bit data is issued. Otherwise, depend-
ing on the instruction (READ), the device starts to drive the output
data on the DO line. Other instructions perform certain control
functions and do not deal with data bits. The Microwire cycle ends
when the CS signal is brought low. However during certain
instructions, fallingedgeoftheCSsignalinitiatesaninternalcycle
(Programming), and the device remains busy till the completion of
the internal cycle. Each of the 7 instructions is explained in detail
in the following sections.
It is also recommended to follow this instruction (after the device
becomes READY) with a Write Disable (WDS) instruction to
safeguarddataagainstcorruptionduetospuriousnoise,inadvert-
ent writes etc.
4) Write All (WRALL)
Write all (WRALL) instruction is similar to the Write instruction
except that WRALL instruction will simultaneously program all
memorylocationswiththedatapatternspecifiedintheinstruction.
This instruction is valid only when device is write-enabled (Refer
WEN instruction).
1) Read (READ)
READ instruction allows data to be read from a selected location
in the memory array. Input information (Start bit, Opcode and
Address) for this instruction should be issued as listed under
Table1. Upon receiving a valid input information, decoding of the
opcode and the address is made, followed by data transfer from
the selected memory location into a 16-bit serial-out shift register.
This 16-bit data is then shifted out on the DO pin. D15 bit (MSB)
is shifted out first and D0 bit (LSB) is shifted out last. A dummy-bit
(logical 0) precedes this 16-bit data output string. Output data
changes are initiated on the rising edge of the SK clock. After
reading the 16-bit data, the CS signal can be brought low to end
the Read cycle. Refer Read cycle diagram.
Input information (Start bit, Opcode, Address and Data) for this
WRALL instruction should be issued as listed under Table1. After
inputtingthelastbitofdata(D0bit), CSsignalmustbebroughtlow
before the next rising edge of the SK clock. This falling edge of the
CS initiates the self-timed programming cycle. It takes tWP time
(Refer appropriate DC and AC Electrical Characteristics table) for
the internal programming cycle to finish. During this time, the
device remains busy and is not ready for another instruction.
Status of the internal programming can be polled as described
under WRITE instruction description. While the device is busy, it
is recommended that no new instruction be issued. ReferWrite All
cycle diagram.
2) Write Enable (WEN)
5) Write Disable (WDS)
When VCC is applied to the part, it “powers up” in the Write Disable
(WDS) state. Therefore, all programming operations must be
preceded by a Write Enable (WEN) instruction. Once a Write
Enable instruction is executed, programming remains enabled
until a Write Disable (WDS) instruction is executed or VCC is
completely removed from the part. Input information (Start bit,
Opcode and Address) for this WEN instruction should be issued
as listed under Table1. The device becomes write-enabled at the
end of this cycle when the CS signal is brought low. Execution of
a READ instruction is independent of WEN instruction. Refer
Write Enable cycle diagram.
Write Disable (WDS) instruction disables all programming opera-
tions and should follow all programming operations. Executing this
instruction after a valid write instruction would protect against
accidental data disturb due to spurious noise, glitches, inadvertent
writesetc. Inputinformation(Startbit, OpcodeandAddress)forthis
WDS instruction should be issued as listed under Table1. The
devicebecomeswrite-disabledattheendofthiscyclewhentheCS
signal is brought low. Execution of a READ instruction is indepen-
dent of WDS instruction. Refer Write Disable cycle diagram.
6) Erase (ERASE)
The ERASE instruction will program all bits in the specified
location to a logical “1” state. Input information (Start bit, Opcode
and Address) for this WDS instruction should be issued as listed
under Table1. After inputting the last bit of data (A0 bit), CS signal
must be brought low before the next rising edge of the SK clock.
This falling edge of the CS initiates the self-timed programming
cycle. It takes tWP time (Refer appropriate DC and AC Electrical
Characteristics table) for the internal programming cycle to finish.
During this time, the device remains busy and is not ready for
another instruction. Status of the internal programming can be
polled as described under WRITE instruction description. While
the device is busy, it is recommended that no new instruction be
issued. Refer Erase cycle diagram.
3) Write (WRITE)
WRITE instruction allows write operation to a specified location in
thememorywithaspecifieddata. Thisinstructionisvalidonlywhen
device is write-enabled (Refer WEN instruction).
Input information (Start bit, Opcode, Address and Data) for this
WRITE instruction should be issued as listed under Table1. After
inputtingthelastbitofdata(D0bit), CSsignalmustbebroughtlow
before the next rising edge of the SK clock. This falling edge of the
CS initiates the self-timed programming cycle. It takes tWP time
(Refer appropriate DC and AC Electrical Characteristics table) for
the internal programming cycle to finish. During this time, the
device remains busy and is not ready for another instruction.
7) Erase All (ERAL)
6
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FM93C06 Rev. C.1
The Erase all instruction will program all locations to a logical “1”
state. Input information (Start bit, Opcode and Address) for this
WDS instruction should be issued as listed under Table1. After
inputtingthelastbitofdata(A0bit), CSsignalmustbebroughtlow
before the next rising edge of the SK clock. This falling edge of the
CS initiates the self-timed programming cycle. It takes tWP time
(Refer appropriate DC and AC Electrical Characteristics table) for
the internal programming cycle to finish. During this time, the
device remains busy and is not ready for another instruction.
Status of the internal programming can be polled as described
under WRITE instruction description. While the device is busy, it
is recommended that no new instruction be issued. Refer Erase
All cycle diagram.
the programming status as either BUSY (low) or READY (high)
when CS is brought high (DO output will be tri-stated when CS is
low). To restate, during programming, the CS pin may be brought
high and low any number of times to view the programming status
without affecting the programming operation. Once programming
is completed (Output in READY state), the output is ‘cleared’
(returned to normal tri-state condition) by clocking in a Start Bit.
After the Start Bit is clocked in, the output will return to a tri-stated
condition. When clocked in, this Start Bit can be the first bit in a
command string, or CS can be brought low again to reset all
internal circuits. Refer Clearing Ready Status diagram.
Related Document
Note: The Fairchild CMOS EEPROMs do not require an “ERASE” or “ERASE ALL”
instruction prior to the “WRITE” or “WRITE ALL” instruction, respectively. The
“ERASE” and “ERASE ALL” instructions are included to maintain compatibility with
earlier technology EEPROMs.Clearing of Ready/Busy status
Application Note: AN758 - Using Fairchild’s MICROWIRE™ EE-
PROM.
When programming is in progress, the Data-Out pin will display
7
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FM93C06 Rev. C.1
Timing Diagrams
SYNCHRONOUS DATA TIMING
CS
t
t
t
t
CSH
CSS
SKH
SKL
SK
t
t
DIH
DIS
Valid
Input
Valid
Input
DI
t
PD
t
t
DF
t
t
PD
DH
Valid
Output
Valid
Output
DO (Data Read)
DO (Status Read)
DF
t
SV
Valid Status
NORMAL READ CYCLE (READ)
t
CS
CS
SK
1
1
0
A5
A4
A1
A0
DI
Start Opcode
Bit Bits(2)
Address
Bits(6)
High - Z
0
D15
D1
D0
DO
Dummy
Bit
93C06:
Address bits pattern -> 0-0-A3-A2-A1-A0; (A3-A0 -> User defined)
WRITE ENABLE CYCLE (WEN)
tCS
CS
SK
1
0
0
A5
A4
A1
A0
DI
Start Opcode
Bit Bits(2)
Address
Bits(6)
High - Z
DO
93C06:
Address bits pattern -> 1-1-x-x-x-x; (x -> Don't Care, can be 0 or 1)
8
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FM93C06 Rev. C.1
Timing Diagrams (Continued)
WRITE DISABLE CYCLE (WDS)
t
CS
CS
SK
DI
1
0
0
A5
A4
A1
A0
Start Opcode
Bit Bits(2)
Address
Bits(6)
High - Z
DO
93C06:
Address bits pattern -> 0-0-x-x-x-x; (x -> Don't Care, can be 0 or 1)
WRITE CYCLE (WRITE)
tCS
CS
SK
1
0
1
A5
A4
A1
A0
D15 D14
D1
D0
DI
tWP
Start Opcode
Bit Bits(2)
Address
Bits(6)
Data
Bits(16)
High - Z
Ready
DO
Busy
93C06:
Address bits pattern -> 0-0-A3-A2-A1-A0; (A3-A0 -> User defined)
Data bits pattern -> User defined
WRITE ALL CYCLE (WRALL)
tCS
CS
SK
1
0
0
A5
A4
A1
A0
D15 D14
D1
D0
DI
tWP
Start Opcode
Bit Bits(2)
Address
Bits(6)
Data
Bits(16)
High - Z
Ready
DO
Busy
93C06:
Address bits pattern -> 0-1-x-x-x-x; (x -> Don't Care, can be 0 or 1)
Data bits pattern -> User defined
9
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FM93C06 Rev. C.1
Timing Diagrams (Continued)
ERASE CYCLE (ERASE)
tCS
CS
SK
DI
1
1
1
A5
A4
A1
A0
tWP
Start Opcode
Bit Bits(2)
Address
Bits(6)
High - Z
Ready
DO
Busy
93C06:
Address bits pattern -> 0-0-A3-A2-A1-A0; (A3-A0 -> User defined)
ERASE ALL CYCLE (ERAL)
tCS
CS
SK
1
0
0
A5
A4
A1
A0
DI
tWP
Start Opcode
Bit Bits(2)
Address
Bits(6)
High - Z
Ready
DO
Busy
93C06:
Address bits pattern -> 1-0-x-x-x-x; (x -> Don’t Care, can be 0 or 1)
CLEARING READY STATUS
CS
SK
DI
Start
Bit
High - Z
High - Z
Ready
DO
Busy
Note: This Start bit can also be part of a next instruction. Hence the cycle
can be continued (instead of getting terminated, as shown) as if a new
instruction is being issued.
10
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FM93C06 Rev. C.1
Physical Dimensions inches (millimeters) unless otherwise noted
0.189 - 0.197
(4.800 - 5.004)
8
7
6
5
0.228 - 0.244
(5.791 - 6.198)
1
2
3
4
Lead #1
IDENT
0.150 - 0.157
(3.810 - 3.988)
0.053 - 0.069
(1.346 - 1.753)
0.010 - 0.020
(0.254 - 0.508)
0.004 - 0.010
(0.102 - 0.254)
x 45¡
8¡ Max, Typ.
All leads
Seating
Plane
0.004
(0.102)
All lead tips
0.0075 - 0.0098
(0.190 - 0.249)
Typ. All Leads
0.014
(0.356)
0.016 - 0.050
(0.406 - 1.270)
Typ. All Leads
0.050
(1.270)
Typ
0.014 - 0.020
Typ.
(0.356 - 0.508)
Molded Package, Small Outline, 0.15 Wide, 8-Lead (M8)
Package Number M08A
11
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FM93C06 Rev. C.1
Physical Dimensions inches (millimeters) unless otherwise noted
0.114 - 0.122
(2.90 - 3.10)
8
5
(7.72) Typ
(4.16) Typ
0.169 - 0.177
(4.30 - 4.50)
0.246 - 0.256
(6.25 - 6.5)
(1.78) Typ
(0.42) Typ
0.123 - 0.128
(3.13 - 3.30)
(0.65) Typ
Land pattern recommendation
1
4
Pin #1 IDENT
0.0433
Max
(1.1)
0.0035 - 0.0079
See detail A
0.002 - 0.006
(0.05 - 0.15)
0.0256 (0.65)
Typ.
Gage
plane
0.0075 - 0.0118
(0.19 - 0.30)
0¡-8¡
DETAIL A
Typ. Scale: 40X
0.0075 - 0.0098
(0.19 - 0.25)
0.020 - 0.028
(0.50 - 0.70)
Seating
plane
Notes: Unless otherwise specified
1. Reference JEDEC registration MO153. Variation AA. Dated 7/93
8-Pin Molded TSSOP, JEDEC (MT8)
Package Number MTC08
12
www.fairchildsemi.com
FM93C06 Rev. C.1
Physical Dimensions inches (millimeters) unless otherwise noted
0.373 - 0.400
(9.474 - 10.16)
0.090
(2.286)
8
7
0.032 0.005
(0.813 0.127)
RAD
8
7
6
5
4
0.092
(2.337)
DIA
0.250 - 0.005
(6.35 0.127)
Pin #1
IDENT
+
Pin #1 IDENT
1
Option 1
1
2
3
Option 2
0.280
MIN
0.040
(1.016)
Typ.
(7.112)
0.030
0.145 - 0.200
(3.683 - 5.080)
0.039
(0.991)
MAX
(0.762)
0.300 - 0.320
(7.62 - 8.128)
20° 1°
0.130 0.005
(3.302 0.127)
0.125 - 0.140
95° 5°
(3.175 - 3.556)
0.065
(1.651)
0.125
(3.175)
DIA
0.020
90° 4°
Typ
0.009 - 0.015
(0.229 - 0.381)
(0.508)
Min
0.018 0.003
(0.457 0.076)
NOM
+0.040
-0.015
0.325
0.100 0.010
+1.016
-0.381
8.255
(2.540 0.254)
0.045 0.015
(1.143 0.381)
0.060
(1.524)
0.050
(1.270)
Molded Dual-In-Line Package (N)
Package Number N08E
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written
approval of the President of Fairchild Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which,
(a)areintendedforsurgicalimplantintothebody,or(b)support
or sustain life, and whose failure to perform, when properly
used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant
injury to the user.
2. A critical component is any component of a life support device
or system whose failure to perform can be reasonably ex-
pected to cause the failure of the life support device or system,
or to affect its safety or effectiveness.
Fairchild Semiconductor
Americas
Fairchild Semiconductor
Europe
Fairchild Semiconductor
Hong Kong
Fairchild Semiconductor
Japan Ltd.
Customer Response Center
Tel. 1-888-522-5372
Fax:
Tel:
Tel:
Tel:
Tel:
+44 (0) 1793-856858
8/F, Room 808, Empire Centre
68 Mody Road, Tsimshatsui East
Kowloon. Hong Kong
Tel; +852-2722-8338
Fax: +852-2722-8383
4F, Natsume Bldg.
Deutsch
English
Français
Italiano
+49 (0) 8141-6102-0
+44 (0) 1793-856856
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2-18-6, Yushima, Bunkyo-ku
Tokyo, 113-0034 Japan
Tel: 81-3-3818-8840
Fax: 81-3-3818-8841
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
13
www.fairchildsemi.com
FM93C06 Rev. C.1
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