FM93CS66 [FAIRCHILD]

(MICROWIRE⑩ Bus Interface) 4096-Bit Serial EEPROM with Data Protect and Sequential Read; （ MICROWIRE⑩总线接口） 4096位串行EEPROM与数据保护和连续读


型号：	FM93CS66
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	(MICROWIRE⑩ Bus Interface) 4096-Bit Serial EEPROM with Data Protect and Sequential Read （ MICROWIRE⑩总线接口） 4096位串行EEPROM与数据保护和连续读可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件：	总16页 (文件大小：172K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

July 2000

FM93CS66

(MICROWIRE™ Bus Interface) 4096-Bit Serial EEPROM

with Data Protect and Sequential Read

General Description

Features

FM93CS66 is a 4096-bit CMOS non-volatile EEPROM organized

as 256 x 16-bit array. This device features MICROWIRE interface

which is a 4-wire serial bus with chipselect (CS), clock (SK), data

input (DI) and data output (DO) signals. This interface is compat-

ible to many of standard Microcontrollers and Microprocessors.

FM93CS66 offers programmable write protection to the memory

array using a special register called Protect Register. Selected

memory locations can be protected against write by programming

this Protect Register with the address of the first memory location

to be protected (all locations greater than or equal to this first

addressarethenprotectedfromfurtherchange). Additionally, this

address can be “permanently locked” into the device, making all

future attempts to change data impossible. In addition this device

features “sequential read”, by which, entire memory can be read

in one cycle instead of multiple single byte read cycles. There are

10 instructions implemented on the FM93CS66, 5 of which are for

memory operations and the remaining 5 are for Protect Register

operations. This device is fabricated using Fairchild Semiconduc-

torfloating-gateCMOSprocessforhighreliability,highendurance

and low power consumption.

I Wide V_CC2.7V - 5.5V

I Programmable write protection

I Sequential register read

I Typical active current of 200µA

10µA standby current typical

1µA standby current typical (L)

0.1µA standby current typical (LZ)

I No Erase instruction required before Write instruction

I Self timed write cycle

I Device status during programming cycles

I 40 year data retention

I Endurance: 1,000,000 data changes

I Packages available: 8-pin SO, 8-pin DIP, 8-pin TSSOP

“LZ” and “L” versions of FM93CS66 offer very low standby current

makingthemsuitableforlowpowerapplications.Thisdeviceisoffered

in both SO and TSSOP packages for small space considerations.

Functional Diagram

V_CC

INSTRUCTION

DECODER

CONTROL LOGIC

AND CLOCK

PRE

INSTRUCTION

GENERATORS

COMPARATOR

AND

WRITE ENABLE

HIGH VOLTAGE

GENERATOR

AND

PROGRAM

TIMER

ADDRESS

PROTECT

DECODER

EEPROM ARRAY

READ/WRITE AMPS

V_SS

DATA IN/OUT REGISTER

16 BITS

DATA OUT BUFFER

FM93CS66 Rev. C.1

www.fairchildsemi.com

Connection Diagram

Dual-In-Line Package (N)

8–Pin SO (M8) and 8–Pin TSSOP (MT8)

V_CC

PRE

GND

Top View

Package Number

N08E, M08A and MTC08

Pin Names

Chip Select

Serial Data Clock

Serial Data Input

Serial Data Output

Ground

GND

Program Enable

Protect Register Enable

Power Supply

PRE

V_CC

Ordering Information

CS XX LZ

XXX

Letter Description

Package

8-pin DIP

MT8

8-pin SO

8-pin TSSOP

Temp. Range

None

0 to 70°C

-40 to +125°C

-40 to +85°C

Voltage Operating Range

Blank

4.5V to 5.5V

2.7V to 5.5V

2.7V to 5.5V and

<1µA Standby Current

Density

4096 bits

CMOS

Data protect and sequential

read

Interface

MICROWIRE

Fairchild Memory Prefix

www.fairchildsemi.com

FM93CS66 Rev. C.1

Absolute Maximum Ratings (Note 1)

Operating Conditions

Ambient Storage Temperature

-65°C to +150°C

Ambient Operating Temperature

FM93CS66

0°C to +70°C

-40°C to +85°C

-40°C to +125°C

All Input or Output Voltages

with Respect to Ground

+6.5V to -0.3V

FM93CS66E

FM93CS66V

Lead Temperature

(Soldering, 10 sec.)

+300°C

Power Supply (V_CC

)

4.5V to 5.5V

ESD rating

2000V

DC and AC Electrical Characteristics V_CC= 4.5V to 5.5V unless otherwise specified

Symbol

I_CCA

Parameter

Conditions

CS = V_IH, SK=1.0 MHz

CS = V_IL

Min

Max

Units

Operating Current

I_CCS

Standby Current

-1

µA

I_IL

I_OL

Input Leakage

Output Leakage

V_IN= 0V to V_CC

(Note 2)

V_IL

V_IH

Input Low Voltage

Input High Voltage

-0.1

0.8

V_CC+1

V_OL1

V_OH1

Output Low Voltage

Output High Voltage

I_OL= 2.1 mA

I_OH= -400 µA

I_OL= 10 µA

I_OH= -10 µA

(Note 3)

0.4

0.2

2.4

V_OL2

V_OH2

Output Low Voltage

Output High Voltage

V_CC- 0.2

f_SK

SK Clock Frequency

SK High Time

MHz

t_SKH

0°C to +70°C

-40°C to +125°C

250

300

t_SKL

t_CS

SK Low Time

250

Minimum CS Low Time

(Note 4)

t_CSS

t_PRES

t_DH

CS Setup Time

PRE Setup Time

DO Hold Time

PE Setup Time

DI Setup Time

t_PES

t_DIS

100

t_CSH

t_PEH

t_PREH

t_DIH

CS Hold Time

PE Hold Time

PRE Hold Time

DI Hold Time

Output Delay

250

t_PD

500

t_SV

CS to Status Valid

t_DF

CS to DO in Hi-Z

Write Cycle Time

CS = V_IL

100

t_WP

www.fairchildsemi.com

FM93CS66 Rev. C.1

Absolute Maximum Ratings (Note 1)

Operating Conditions

Ambient Storage Temperature

-65°C to +150°C

Ambient Operating Temperature

FM93CS66L/LZ

0°C to +70°C

-40°C to +85°C

-40°C to +125°C

All Input or Output Voltages

with Respect to Ground

+6.5V to -0.3V

FM93CS66LE/LZE

FM93CS66LV/LZV

Lead Temperature

(Soldering, 10 sec.)

+300°C

Power Supply (V_CC

)

2.7V to 5.5V

ESD rating

2000V

DC and AC Electrical Characteristics V_CC= 2.7V to 4.5V unless otherwise specified. Refer to

page 3 for V_CC= 4.5V to 5.5V.

Symbol

I_CCA

Parameter

Conditions

CS = V_IH, SK=256 KHz

CS = V_IL

Min

Max

Units

Operating Current

I_CCS

Standby Current

LZ (2.7V to 4.5V)

µA

I_IL

I_OL

Input Leakage

Output Leakage

V_IN= 0V to V_CC

(Note 2)

µA

V_IL

V_IH

Input Low Voltage

Input High Voltage

-0.1

0.8V_CC

0.15V_CC

V_CC+1

V_OL

V_OH

Output Low Voltage

Output High Voltage

I_OL= 10µA

I_OH= -10µA

0.1V_CC

0.9V_CC

f_SK

t_SKH

t_SKL

SK Clock Frequency

SK High Time

(Note 3)

250

KHz

µs

SK Low Time

t_CS

Minimum CS Low Time

(Note 4)

µs

t_CSS

t_PRES

t_DH

CS Setup Time

PRE Setup Time

DO Hold Time

PE Setup Time

DI Setup Time

0.2

0.4

µs

t_PES

t_DIS

t_CSH

t_PEH

t_PREH

t_DIH

CS Hold Time

PE Hold Time

PRE Hold Time

DI Hold Time

Output Delay

µs

250

0.4

t_PD

t_SV

CS to Status Valid

µs

t_DF

CS to DO in Hi-Z

Write Cycle Time

CS = V_IL

0.4

µs

t_WP

Note 1: Stressabovethoselistedunder“AbsoluteMaximumRatings”maycausepermanentdamage

to the device. This is a stress rating only and functional operation of the device at these or any other

conditionsabovethoseindicatedintheoperationalsectionsofthespecificationisnotimplied. Exposure

to absolute maximum rating conditions for extended periods may affect device reliability.

Capacitance T_A= 25°C, f = 1 MHz or 256

KHz (Note 5)

Note 2: Typical leakage values are in the 20nA range.

Note 3: TheshortestallowableSKclockperiod=1/f_SK(asshownunderthef_SKparameter). Maximum

SK clock speed (minimum SK period) is determined by the interaction of several AC parameters stated

in the datasheet. Within this SK period, both t_SKHand t_SKLlimits must be observed. Therefore, it is not

allowable to set 1/f_SK= t_SKHminimum+ t_SKLminimumfor shorter SK cycle time operation.

Symbol

Test

Typ Max Units

C_OUT

C_IN

Output Capacitance

Input Capacitance

Note 4: CS (Chip Select) must be brought low (to V_IL) for an interval of t_CSin order to reset all internal

device registers (device reset) prior to beginning another opcode cycle. (This is shown in the opcode

diagram on the following page.)

Note 5: This parameter is periodically sampled and not 100% tested.

AC Test Conditions

V_CCRange

V_IL/V_IH

Input Levels

0.3V/1.8V

V_IL/V_IH

V_OL/V_OH

Timing Level

0.8V/1.5V

I_OL/I_OH

Timing Level

2.7V ≤ V_CC≤ 5.5V

1.0V

10µA

(Extended Voltage Levels)

4.5V ≤ V_CC≤ 5.5V

0.4V/2.4V

1.0V/2.0V

0.4V/2.4V

2.1mA/-0.4mA

(TTL Levels)

Output Load: 1 TTL Gate (C_L= 100 pF)

www.fairchildsemi.com

FM93CS66 Rev. C.1

Program Enable (PE)

Pin Description

This is an active high input pin to the device and is used to enable

operations, that are write in nature, to the memory array and to the

Protect register. When this pin is held high, operations that are

“write” in nature are enabled. When this pin is held low, operations

that are “write” in nature are disabled. This pin operates in

conjunctionwithPREpin. ReferTable1forfunctionalmatrixofthis

pin for various operations.

Chip Select (CS)

ThisisanactivehighinputpintoFM93CS66EEPROM(thedevice)

and is generated by a master that is controlling the device. A high

level on this pin selects the device and a low level deselects the

device. All serial communications with the device is enabled only

when this pin is held high. However this pin cannot be permanently

tied high, as a rising edge on this signal is required to reset the

internal state-machine to accept a new cycle and a falling edge to

initiateaninternalprogrammingafterawritecycle.Allactivityonthe

SK, DI and DO pins are ignored while CS is held low.

Microwire Interface

AtypicalcommunicationontheMicrowirebusismadethroughthe

CS, SK, DI and DO signals. To facilitate various operations on the

Memory array and on the Protect Register, a set of 10 instructions

are implemented on FM93CS66. The format of each instruction is

listed in Table 1.

Serial Clock (SK)

Thisisaninputpintothedeviceandisgeneratedbythemasterthat

is controlling the device. This is a clock signal that synchronizes the

communicationbetweenamasterandthedevice. Allinputinforma-

tion(DI)tothedeviceislatchedontherisingedgeofthisclockinput,

whileoutputdata(DO)fromthedeviceisdrivenfromtherisingedge

of this clock input. This pin is gated by CS signal.

Instruction

Each of the above 10 instructions is explained under individual

instruction descriptions.

Start Bit

Serial Input (DI)

This is a 1-bit field and is the first bit that is clocked into the device

whenaMicrowirecyclestarts.Thisbithastobe“1”foravalidcycle

to begin. Any number of preceding “0” can be clocked into the

device before clocking a “1”.

This is an input pin to the device and is generated by the master

that is controlling the device. The master transfers Input informa-

tion (Start bit, Opcode bits, Array addresses and Data) serially via

this pin into the device. This Input information is latched on the

rising edge of the SCK. This pin is gated by CS signal.

Opcode

Serial Output (DO)

This is a 2-bit field and should immediately follow the start bit.

These two bits (along with PRE, PE signals and 2 MSB of address

field) select a particular instruction to be executed.

This is an output pin from the device and is used to transfer Output

data via this pin to the controlling master. Output data is serially

shifted out on this pin from the rising edge of the SCK. This pin is

active only when the device is selected.

Address Field

This is a 8-bit field and should immediately follow the Opcode bits.

In FM93CS66, all 8 bits are used for address decoding during

READ, WRITE and PRWRITE instructions.During all other in-

structions (with the exception of PRREAD), the MSB 2 bits are

used to decode instruction (along with Opcode bits, PRE and PE

signals).

Protect Register Enable (PRE)

This is an active high input pin to the device and is used to

distinguish operations to memory array and operations to Protect

array are enabled. When this pin is held high, operations to the

Protect Register are enabled. This pin operates in conjunction

with PE pin. Refer Table1 for functional matrix of this pin for

various operations.

Data Field

This is a 16-bit field and should immediately follow the Address

bits. Only the WRITE and WRALL instructions require this field.

D15 (MSB) is clocked first and D0 (LSB) is clocked last (both

during writes as well as reads).

TABLE 1. Instruction set

Instruction Start Bit Opcode Field

Address Field

Data Field PRE Pin

PE Pin

READ

WEN

A7 A6 A5 A4 A3 A2 A1 A0

WRITE

WRALL

WDS

A7 A6 A5 A4 A3 A2 A1 A0

D15-D0

PRREAD

PREN

PRCLEAR

PRWRITE

PRDS

A7 A6 A5 A4 A3 A2 A1 A0

www.fairchildsemi.com

FM93CS66 Rev. C.1

the part. Input information (Start bit, Opcode and Address) for this

WEN instruction should be issued as listed under Table1. The

device becomes write-enabled at the end of this cycle when the

CS signal is brought low. The PRE pin should be held low during

thiscycle.ExecutionofaREADinstructionisindependentofWEN

instruction. Refer Write Enable cycle diagram.

Functional Description

A typical Microwire cycle starts by first selecting the device

(bringing the CS signal high). Once the device is selected, a valid

Start bit (“1”) should be issued to properly recognize the cycle.

Following this, the 2-bit opcode of appropriate instruction should

be issued. After the opcode bits, the 8-bit address information

should be issued. For certain instructions, some (or all) of these

8 bits are don’t care values (can be “0” or “1”), but they should still

be issued. Following the address information, depending on the

instruction (WRITE and WRALL), 16-Bit data is issued. Other-

wise, depending on the instruction (READ and PRREAD), the

device starts to drive the output data on the DO line. Other

instructions perform certain control functions and do not deal with

data bits. The Microwire cycle ends when the CS signal is brought

low. However during certain instructions, falling edge of the CS

signal initiates an internal cycle (Programming), and the device

remains busy till the completion of the internal cycle. Each of the

10 instructions is explained in detail in the following sections.

3) Write (WRITE)

WRITE instruction allows write operation to a specified location in

the memory with a specified data. This instruction is valid only

when the following are true:

I Device is write-enabled (Refer WEN instruction)

I Address of the write location is not write-protected

I PE pin is held high during this cycle

I PRE pin should be held low during this cycle

Input information (Start bit, Opcode, Address and Data) for this

WRITE instruction should be issued as listed under Table1. After

inputtingthelastbitofdata(D0bit), CSsignalmustbebroughtlow

before the next rising edge of the SK clock. This falling edge of the

CS initiates the self-timed programming cycle. It takes t_WPtime

(Refer appropriate DC and AC Electrical Characteristics table) for

the internal programming cycle to finish. During this time, the

device remains busy and is not ready for another instruction.

Memory Instructions

Following five instructions, READ, WEN, WRITE, WRALL and

WDS are specific to operations intended for memory array. The

PRE pin should be held low during these instructions.

1) Read and Sequential Read (READ)

The status of the internal programming cycle can be polled at any

time by bringing the CS signal high again, after t_CSinterval. When

CS signal is high, the DO pin indicates the READY/BUSY status

of the chip. DO = logical 0 indicates that the programming is still

in progress. DO = logical 1 indicates that the programming is

finished and the device is ready for another instruction. It is not

required to provide the SK clock during this status polling. While

the device is busy, it is recommended that no new instruction be

issued. Refer Write cycle diagram.

READ instruction allows data to be read from a selected location

in the memory array. Input information (Start bit, Opcode and

Address) for this instruction should be issued as listed under

Table1. Upon receiving a valid input information, decoding of the

opcode and the address is made, followed by data transfer from

the selected memory location into a 16-bit serial-out shift register.

This 16-bit data is then shifted out on the DO pin. D15 bit (MSB)

is shifted out first and D0 bit (LSB) is shifted out last. A dummy-bit

(logical 0) precedes this 16-bit data output string. Output data

changes are initiated on the rising edge of the SK clock. After

reading the 16-bit data, the CS signal can be brought low to end

the Read cycle. The PRE pin should be held low during this cycle.

Refer Read cycle diagram.

It is also recommended to follow this instruction (after the device

becomes READY) with a Write Disable (WDS) instruction to

safeguarddataagainstcorruptionduetospuriousnoise,inadvert-

ent writes etc.

4) Write All (WRALL)

This device also offers “sequential memory read” operation to

allowreadingofdatafromtheadditionalmemorylocationsinstead

ofjustonelocation.Itisstartedinthesamemannerasnormalread

but the cycle is continued to read further data (instead of terminat-

ing after reading the first 16-bit data). After providing 16-bit data,

the device automatically increments the address pointer to the

next location and continues to provide the data from that location.

Any number of locations can be read out in this manner, however,

after reading out from the last location, the address pointer points

back to the first location. If the cycle is continued further, data will

be read from this first location onward. In this mode of read, the

dummy-bit is present only when the very first data is read (like

normal read cycle) and is not present on subsequent data reads.

The PRE pin should be held low during this cycle. Refer Sequen-

tial Read cycle diagram.

Write all (WRALL) instruction is similar to the Write instruction

except that WRALL instruction will simultaneously program all

memorylocationswiththedatapatternspecifiedintheinstruction.

This instruction is valid only when the following are true:

I Protect Register has been cleared (Refer PRCLEAR

instruction)

I Device is write-enabled (Refer WEN instruction)

I PE pin is held high during this cycle

I PRE pin should be held low during this cycle

Input information (Start bit, Opcode, Address and Data) for this

WRALL instruction should be issued as listed under Table1. After

inputtingthelastbitofdata(D0bit), CSsignalmustbebroughtlow

before the next rising edge of the SK clock. This falling edge of the

CS initiates the self-timed programming cycle. It takes t_WPtime

(Refer appropriate DC and AC Electrical Characteristics table) for

the internal programming cycle to finish. During this time, the

device remains busy and is not ready for another instruction.

Status of the internal programming can be polled as described

under WRITE instruction description. While the device is busy, it

is recommended that no new instruction be issued. ReferWrite All

cycle diagram.

2) Write Enable (WEN)

When V_CCis applied to the part, it “powers up” in the Write Disable

(WDS) state. Therefore, all programming operations (for both

memory array and Protect Register) must be preceded by a Write

Enable (WEN) instruction. Once a Write Enable instruction is

executed, programming remains enabled until a Write Disable

(WDS) instruction is executed or V_CCis completely removed from

www.fairchildsemi.com

FM93CS66 Rev. C.1

I PREN instruction was executed immediately prior to

PRCLEAR instruction

5) Write Disable (WDS)

Write Disable (WDS) instruction disables all programming opera-

tions and is recommended to follow all programming operations.

Executing this instruction after a valid write instruction would

protect against accidental data disturb due to spurious noise,

glitches,inadvertentwritesetc.Inputinformation(Startbit,Opcode

and Address) for this WDS instruction should be issued as listed

under Table1. The device becomes write-disabled at the end of

this cycle when the CS signal is brought low. Execution of a READ

instructionisindependentofWDSinstruction. ReferWriteDisable

cycle diagram.

I PE pin is held high during this cycle

I PRE pin is held high during this cycle

Inputinformation(Startbit,OpcodeandAddress)forthisPRCLEAR

instructionshouldbeissuedaslistedunderTable1. Afterinputting

the last bit of address (A0 bit), CS signal must be brought low

before the next rising edge of the SK clock. This falling edge of the

CS initiates the self-timed clear cycle. It takes t_WPtime (Refer

appropriate DC and AC Electrical Characteristics table) for the

internal clear cycle to finish. During this time, the device remains

busy and is not ready for another instruction. Status of the internal

programmingcanbepolledasdescribedunderWRITEinstruction

description. While the device is busy, it is recommended that no

new instruction be issued. Refer Protect Register Clear cycle

diagram.

Protect Register Instructions

Following five instructions, PRREAD, PREN, PRCLEAR,

PRWRITE and PRDS are specific to operations intended for

Protect Register. The PRE pin should be held high during these

instructions.

4) Protect Register Write (PRWRITE)

1) Protect Register Read (PRREAD)

Thisinstructionisusedtowritethestartingaddressofthememory

section to be write-protected into the Protect register. After the

execution of PRWRITE instruction, all memory locations greater

than or equal to this address are write-protected. PRWRITE

instruction is enabled (valid) only the following are true:

This instruction reads the content of the internal Protect Register.

Content of this register is 8-bit wide and is the starting address of

the “write-protected” section of the memory array. All memory

locationsgreaterthanorequaltothisaddressarewrite-protected.

Inputinformation(Startbit,OpcodeandAddress)forthisPRREAD

instruction should be issued as listed under Table 1. Upon

receivingavalidinputinformation,decodingoftheopcodeandthe

address is made, followed by data transfer (address information)

from the Protect Register. This 8-bit data is then shifted out on the

DO pin with the MSB first and the LSB last. Like the READ

instruction a dummy-bit (logical 0) precedes this 8-bit data output

string. Output data changes are initiated on the rising edge of the

SKclock.Afterreadingthe8-bitdata,theCSsignalcanbebrought

low to end the PRREAD cycle. The PRE pin should be held high

during this cycle. Refer Protect Register Read cycle diagram.

I PRCLEAR instruction was executed first (to clear the Protect

I PREN instruction was executed immediately prior to

PRWRITE instruction

I PE pin is held high during this cycle

I PRE pin is held high during this cycle

Inputinformation(Startbit,OpcodeandAddress)forthisPRWRITE