FMS6243MTC14 [FAIRCHILD]
Low-Cost, 3-Channel, SD Video Filter Drivers with External Delay Control; 低成本， 3通道，与外部延迟控制SD视频滤波驱动器
| 型号： | FMS6243MTC14 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Low-Cost, 3-Channel, SD Video Filter Drivers with External Delay Control |
| 文件： | 总10页 (文件大小：467K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 2007
FMS6243
Low-Cost, 3-Channel, SD Video Filter Drivers with
External Delay Control
Features
Description
■ Three Fourth-Order 8MHz (SD) Filters
■ External Delay Control
The FMS6243 Low-Cost Video Filter (LCVF) is intended
to replace passive LC filters and drivers with a low-cost
integrated device. Three fourth-order filters provide
improved image quality compared to typical second- or
third-order passive solutions.
■ Transparent Input Clamping
■ Dual-Video Load Drive (2Vpp, 75Ω)
■ AC- or DC-Coupled Inputs
■ AC- or DC-Coupled Outputs
■ DC-Coupled Outputs Eliminate AC-Coupling
Capacitors
The FMS6243 can be directly driven by a DC-coupled
DAC output or an AC-coupled signal. Internal diode
clamps and bias circuitry can be used if AC-coupled
inputs are required (see the Applications section for
details).
■ 5V Only
■ Lead-Free Package: TSSOP-14
Delay for each channel can be independently controlled
with an external capacitor.
Applications
■ Cable Set-Top Boxes
■ Satellite Set-Top Boxes
■ DVD Players
The outputs can drive AC- or DC-coupled single (150Ω)
or dual (75Ω) loads. DC coupling the outputs removes
the need for output coupling capacitors. The input DC
levels are offset approximately +280mV at the output
(see the Applications section for details).
■ HDTV
■ Personal Video Recorders (PVR)
■ Video On Demand (VOD)
Ordering Information
Operating
Pb- Temperature
Part Number
Package
Free
Range
Packing Method
Tube
FMS6243MTC14 14-Lead TSSOP, JEDEC MO-153, 4.4mm Wide
FMS6243MTC14X 14-Lead TSSOP, JEDEC MO-153, 4.4mm Wide
Yes
-40°C to 85°C
-40°C to 85°C
Yes
Tape and Reel
2X
2X
IN1
Transparent Clamp
Transparent Clamp
Transparent Clamp
OUT1
OUT2
OUT3
Del1
IN2
Del2
2X
IN3
Del3
8MHz, 4th-order
Figure 1. Functional Block Diagram
© 2007 Fairchild Semiconductor Corporation
FMS6243 Rev. 1.0.0
www.fairchildsemi.com
Pin Assignments
1
2
3
4
5
6
7
14
13
12
11
10
9
VCC
DCap1
GND
IN1
GND
OUT1
OUT2
OUT3
DCap3
GND
IN2
IN3
GND
DCap2
8
Figure 2. Pin Configuration
Pin Definitions
Pin #
Name
Type
Description
1
DCap1
INPUT
External Group Delay and Chroma/Luma Delay Adjustment for Channel 1
Must be tied to ground, do not float
2
3
GND
IN1
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
Video input channel 1
4
IN2
Video input channel 2
5
IN3
Video input channel 3
6
GND
DCap2
GND
DCap3
OUT3
OUT2
OUT1
GND
VCC
Must be tied to ground, do not float
7
External Group Delay and Chroma/Luma Delay Adjustment for Channel 2
Must be tied to ground, do not float
8
9
External Group Delay and Chroma/Luma Delay Adjustment for Channel 3
10
11
12
13
14
OUTPUT Filtered output for channel 3
OUTPUT Filtered output for channel 2
OUTPUT Filtered output for channel 1
INPUT
INPUT
Must be tied to ground, do not float
+5V supply, do not float
© 2007 Fairchild Semiconductor Corporation
FMS6243 Rev. 1.0.0
www.fairchildsemi.com
2
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be opera-
ble above the recommended operating conditions and stressing the parts to these levels is not recommended. In addi-
tion, extended exposure to stresses above the recommended operating conditions may affect device reliability. The
absolute maximum ratings are stress ratings only.
Symbol
VCC
Parameter
Min.
-0.3
-0.3
Max.
6.0
Units
V
DC Supply Voltage
VI/O
Analog and Digital I/O
VCC +0.3
50
V
IOUT
Output Current Any One Channel, Do Not Exceed
mA
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbols
TA
Parameter
Operating Temperature Range
VCC Range
Min.
-40
Typ.
Max.
85
Units
°C
VCC
4.75
5.00
5.25
V
Electrostatic Discharge Conditions
Symbols
HBM
Parameter
Value
Units
kV
Human Body Model
8
2
CDM
Charged Device Model
kV
Reliability Information
Symbol
Parameter
Min.
Typ.
Max.
150
Units
°C
TJ
TSTG
TL
Junction Temperature
Storage Temperature Range
-65
150
°C
Reflow Temperature (Soldering)
260
°C
Thermal Resistance, Still Air
JEDEC Standard Multi-Layer Test Boards,
ΘJA
100
°C/W
© 2007 Fairchild Semiconductor Corporation
FMS6243 Rev. 1.0.0
www.fairchildsemi.com
3
DC Specifications
TA = 25°C, VCC = 5.0V, RS = 37.5Ω; all inputs are AC coupled with 0.1μF; all outputs are AC coupled with 220μF into
150Ω loads; unless otherwise noted.
Symbol
ICC
Parameter
Supply Current(1)
Video Input Voltage Range
Conditions
Min. Typ. Max. Units
No Load
Referenced to GND if DC-coupled
24
34
mA
VIN
1.4
Vpp
Power Supply Rejection Ratio DC
(All Channels)
PSRR
48
dB
Note:
1. 100% tested at 25°C.
AC Electrical Specifications
TA = 25°C, VIN = 1VPP, VCC = 5.0V, RS = 37.5Ω; all inputs are AC coupled with 0.1µF; all outputs are AC coupled with
220µF into 150Ω loads; unless otherwise noted.
Symbol
AV
Parameter
Channel Gain(1)
Conditions
Min. Typ. Max. Units
All Channels
All Channels
All Channels
5.6
5.5
6.0
6.5
8.0
44
6.6
dB
MHz
MHz
dB
%
f1dB
-1dB Bandwidth(1)
-3dB Bandwidth
fC
fSB
Attenuation (Stopband Reject) All Channels at f = 27MHz
DG
Differential Gain
All Channels
All Channels
0.3
0.6
0.4
-70
DP
Differential Phase
°
THD
XTALK
Output Distortion (All Channels) VOUT = 1.8Vpp, 1MHz
Crosstalk (Channel-to-Channel) f = 1MHz
%
dB
Signal-to-Noise Ratio
All Channels, Chroma Weighting;
SNR
75
dB
5MHz Low Pass
Note:
1. 100% tested at 25°C.
© 2007 Fairchild Semiconductor Corporation
FMS6243 Rev. 1.0.0
www.fairchildsemi.com
4
Application Information
The FMS6243 Low-Cost Video Filter (LCVF) provides
6dB gain from input to output. In addition, the input is
slightly offset to optimize the output driver performance.
The offset is held to the minimum required value to
decrease the standing DC current into the load. Typical
voltage levels are shown in the diagram below:
I/O Configurations
For DC-coupled DAC drive with DC-coupled outputs, use
this configuration:
Figure 5. DC-Coupled Inputs and Outputs
Alternatively, if the DAC’s average DC output level
causes the signal to exceed the range of 0V to 1.4V, it
can be AC-coupled as follows:
Figure 6. AC-Coupled Inputs, DC-Coupled Outputs
When driven by an unknown external source or a
SCART switch with its own clamping circuitry, the inputs
should be AC-coupled like this:
Figure 3. Typical Voltage Levels
The FMS6243 provides an internal diode clamp to sup-
port AC-coupled input signals. If the input signal does not
go below ground, the input clamp does not operate. This
allows DAC outputs to directly drive the FMS6243 without
an AC coupling capacitor. When the input is AC-coupled,
the diode clamp sets the sync tip (or lowest voltage) just
below ground. The worst-case sync tip compression due
to the clamp can not exceed 7mV. The input level set by
the clamp combined with the internal DC offset keeps the
output within its acceptable range.
For symmetric signals like Chroma, U, V, Pb, and Pr, the
average DC bias is fairly constant and the inputs can be
AC-coupled with the addition of a pull-up resistor to set
the DC input voltage. DAC outputs can also drive these
signals without the AC-coupling capacitor. A conceptual
illustration of the input clamp circuit is shown below:
Figure 7. SCART with DC-Coupled Outputs
The same method can be used for biased signals with
the addition of a pull-up resistor to make sure the clamp
never operates. The internal pull-down resistance is
800kΩ ±20% so the external resistance should be
7.5MΩ to set the DC level to 500mV.
Figure 4. Input Clamp Circuit
Figure 8. Biased SCART with DC-Coupled Outputs
© 2007 Fairchild Semiconductor Corporation
FMS6243 Rev. 1.0.0
www.fairchildsemi.com
5
The same circuits can be used with AC-coupled outputs
if desired. Here is the DC-coupled input with an AC-cou-
pled output.
where:
VO = 2Vin + 0.280V
I
CH = (ICC / 3) + (VO/RL)
VIN = RMS value of input signal
ICC = 24mA
Vs = 5V
0V - 1.4V
DVD or
STB
LCVF
Clamp
Inactive
75Ω
RL = channel load resistance
SoC
Board layout can also affect thermal characteristics.
Refer to the Layout Considerations section for more
information.
DAC
Output
The FMS6243 is specified to operate with output cur-
rents typically less than 50mA, more than sufficient for a
dual (75Ω) video load. Internal amplifiers are current lim-
ited to a maximum of 100mA and should withstand brief-
duration, short-circuit conditions; however, this capability
is not guaranteed.
Figure 9. DC-Coupled Inputs, AC-Coupled Outputs
External video
0V - 1.4V
source must
be AC coupled
0.1μ
220μ
LCVF
Clamp
Active
75Ω
Group Delay Adjustment
75Ω
The FMS6243 has the ability to independently adjust
each channel for Sin X/X group delay and Chroma/Luma
delay. This is accomplished by placing a capacitor from
the device delay adjust pin to ground. The group delay
can be adjusted from the nominal of +10ns to -80ns. This
means that, under a nominal situation, a video system
may have an overall group delay measurement of
+50ns. If the system specification is +40ns, the
FMS6243 could be used to decrease this group delay to
fall well within specification with a guard band to allow for
system variation.
Figure 10. AC-coupled Inputs and Outputs
External video
source must
7.5MΩ
0.1μ
be AC coupled
LCVF
Bias
Input
75Ω
Adding a 50pF capacitor to the desired channel DCap
pin (see Figure 15) generates a -20ns delay through the
FMS6243, which, when summed with the +50ns of the
system, gives a new system overall group delay of
+30ns. It now meets the system specification with a
+10ns guard band for system group delay variation.
75Ω
500mV +/-350mV
Figure 11. Biased AC-Coupled Inputs with
AC-Coupled Outputs
Figure 12 shows the effect on group delay by adding
capacitance to the FMS6243 DCap pins. The correct
capacitor can be chosen by determining the format of the
video system (NTSC 3.58 or PAL 4.43), then choosing
the desired group delay to sum with overall system
delay. The desired delay and format line intersection is
the delay capacitor needed for the DCap pins.
NOTE: The video tilt or line time distortion is dominated
by the AC-coupling capacitor. The value may need to be
increased beyond 220µF to obtain satisfactory operation
in some applications.
Power Dissipation
40
400kHz Ref
4.43MHz
3.58MHz
The output drive configuration must be considered when
calculating overall power dissipation. Care must be taken
not to exceed the maximum die junction temperature.
The following example can be used to calculate power
dissipation and internal temperature rise:
20
0
10pF
20pF
30pF
40pF
50pF
60pF
70pF
80pF
-20
-40
-60
-80
-100
Tj = TA + Pd • ΘJA
where:
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Frequency (MHz)
Pd = PCH1 + PCH2 + PCH3
and PCHx = Vs • ICH - (VO2/RL)
Figure 12. Group Delay vs. Delay Cap. Value
© 2007 Fairchild Semiconductor Corporation
FMS6243 Rev. 1.0.0
www.fairchildsemi.com
6
Signal Peaking Adjustment
Group Delay and Peaking Adjustment
Simultaneously
The peaking of a video input signal can be adjusted by
placing a peaking capacitor across the series-75ohm
resistor on the output of the FMS6243. Where the input
video signal to the FMS6243 has a soft roll-off, meaning
the input video signal is attenuated at 4Mhz by -0.5dB,
the Chroma/Luma gain is approximately -5% and fails a
system specification of +- 2.5%. This attenuation can be
adjusted by adding a 150pF capacitor across the series-
75ohm resistor on the output (see Figure 15). This brings
the attenuation at 4.0Mhz to approximately 0dB, giving a
Chroma/Luma gain of 0%. Figure 13 shows the peaking
effect of adding a peaking capacitor across the series-
75ohm resistor. The graph shows a 10pF delay capacitor
with a 10pF, 50pF, and 100pF peaking capacitor.
If both a group delay adjustment and a peaking adjust-
ment need to be incorporated into the system design, the
following methodology should be followed. Address the
group delay adjustment first, then the peaking adjus-
ment, because the group delay adjustment causes a
video signal attenuation at 4Mhz.
6.35
4.43MHz
3.58MHz
400KHz
6.30
6.25
6.20
6.15
6.10
6.05
6.00
5.95
5.90
10pF
40pF
80pF
6.40
6.35
10pF10pF
10pF50pF
10pF100pF
6.30
6.25
6.20
6.15
6.10
6.05
6.00
5.95
5.90
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Frequency (MHz)
Figure 14. Frequency Response vs. Delay Cap. Value
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Frequency (MHz)
Figure 13. Frequency Response Delay Capacitor vs.
Peaking Capacitor
VCC
peaking
Delay Cap
Out1
1
2
3
4
5
6
7
14
13
12
11
10
9
DCAP1
GND1
IN1
VCC
GND4
OUT1
75
220ꢀF
peaking
In1
In2
In3
Out2
IN2
OUT2
75
220ꢀF
IN3
OUT3
Delay Cap
GND2
DCAP2
DCAP3
GND3
peaking
8
Out3
Delay Cap
75
220ꢀF
Figure 15. Schematic
© 2007 Fairchild Semiconductor Corporation
FMS6243 Rev. 1.0.0
www.fairchildsemi.com
7
Layout Considerations
It is critical that the delay capacitor pins (1, 7, and 9)
have the delay capacitor placed as close to the device
pin as possible. The ground connection should be as
short as possible, ideally a direct connect to the adjacent
ground pin. These layout considerations create the best
environment for the device and reduce noise.
Thermal Considerations
Since the interior of most systems, such as set-top
boxes, TVs, and DVD players, are at +70°C; consider-
ation must be given to providing an adequate heat sink
for the device package for maximum heat dissipation.
When designing a system board, determine how much
power each device dissipates. Ensure that devices of
high power are not placed in the same location, such as
directly above (top plane) or below (bottom plane), each
other on the PCB.
General layout and supply bypassing play a major role in
high-frequency performance and thermal characteristics.
Fairchild offers a demonstration board to guide layout
and aid device evaluation. The demo board is a four-
layer board with full power and ground planes. Following
this layout configuration provides optimum performance
and thermal characteristics for the device. For the best
results, follow the steps and recommended routing rules
listed below.
PCB Thermal Layout Considerations
■ Understand the system power requirements and
environmental conditions.
■ Maximize thermal performance of the PCB.
■ Consider using 70μm of copper for high-power
designs.
Recommended Routing / Layout Rules
■ Do not run analog and digital signals in parallel.
■ Use separate analog and digital power planes to
supply power.
■ Traces should run on top of the ground plane at all
times.
■ No trace should run over ground / power splits.
■ Avoid routing at 90-degree angles.
■ Minimize clock and video data trace length differ-
ences.
■ Make the PCB as thin as possible by reducing FR4
thickness.
■ Use vias in the power pad to tie adjacent layers
together.
■ Remember that baseline temperature is a function of
board area, not copper thickness.
■
Modeling techniques provide first-order approximation.
■ Include 10μF and 0.1μF ceramic power supply bypass
capacitors.
■ Place the 0.1μF capacitor within 0.1 inches of the
device power pin.
■ Place the 10μF capacitor within 0.75 inches of the
device power pin.
■ For multi-layer boards, use a large ground plane to
help dissipate heat.
■ For two-layer boards, use a ground plane that extends
beyond the device body at least 0.5 inches on all
sides.
■ Include a metal paddle under the device on the top
layer.
■ Minimize all trace lengths to reduce series inductance.
© 2007 Fairchild Semiconductor Corporation
FMS6243 Rev. 1.0.0
www.fairchildsemi.com
8
Mechanical Dimensions
Dimensions are in millimeters unless otherwise noted.
Figure 16. 14-Lead, Thin-Shrink Small Outline Package (TSSOP)
© 2007 Fairchild Semiconductor Corporation
FMS6243 Rev. 1.0.0
www.fairchildsemi.com
9
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PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
This datasheet contains the design specifications for product development.
Specifications may change in any manner without notice.
Advance Information
Formative or In Design
This datasheet contains preliminary data; supplementary data will be pub-
lished at a later date. Fairchild Semiconductor reserves the right to make
changes at any time without notice to improve design.
Preliminary
First Production
Full Production
Not In Production
This datasheet contains final specifications. Fairchild Semiconductor reserves
the right to make changes at any time without notice to improve design.
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Obsolete
This datasheet contains specifications on a product that has been discontin-
ued by Fairchild semiconductor. The datasheet is printed for reference infor-
mation only.
Rev. I24
© 2007 Fairchild Semiconductor Corporation
FMS6243 Rev. 1.0.0
www.fairchildsemi.com
10
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