FOD8160 [FAIRCHILD]
High Noise Immunity, 3.3 V / 5 V, 10 Mbit/sec, Logic Gate Optocoupler in Wide-Body SOP 5-Pin; 高抗干扰， 3.3 V / 5 V ， 10兆位/秒，逻辑门宽体SOP 5引脚
| 型号： | FOD8160 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | High Noise Immunity, 3.3 V / 5 V, 10 Mbit/sec, Logic Gate Optocoupler in Wide-Body SOP 5-Pin |
| 文件： | 总15页 (文件大小：3167K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 2013
FOD8160
High Noise Immunity, 3.3 V / 5 V, 10 Mbit/sec, Logic Gate
Optocoupler in Wide-Body SOP 5-Pin
Features
Description
®
■ Optoplanar packaging technology allows more than
10 mm creepage and clearance distance, and 0.5 mm
insulation distance to achieve reliable and high
voltage insulation
The FOD8160 is a 3.3 V / 5 V high-speed logic gate
optocoupler with open collector output, which supports
isolated communications to allow digital signals to
communicate between systems without conducting
ground loops or hazardous voltages. It utilizes Fairchild’s
■ High noise immunity characterized by common-mode
®
prioprietary Optoplanar coplanar packaging technology
transient immunity (CMTI)
and optimized IC design to achieve high noise immunity,
characterized by high common-mode rejection
specifications.
– 20 kV/µs Minimum CMTI
■ Specifications guaranteed over 3 V to 5.5 V supply
voltage and -40°C to 100°C extended industrial
temperature range
The FOD8160, packaged in a wide-body SOP 5-Pin
package, consists of an aluminium gallium arsenide
(AlGaAs) LED and an integrated high-speed
photodetector. The output of the detector IC is an open
collector Schottky-clamped transistor. The electrical and
switching characteristics are guaranteed over the
extended industrial temperature range of -40°C to 100°C
■ High speed, 10 Mbit/sec Data Rate (NRZ)
■ Safety and regulatory approvals
– UL1577, 5,000 VAC
for 1 minute
RMS
– DIN-EN/IEC60747-5-5, 1,414 V peak working
insulation voltage (pending approval)
and a V range of 3 V to 5.5 V.
CC
Applications
■ Isolating intelligent power module
Functional Schematic
■ Isolating industrial communication interface
V
V
1
3
6
5
4
ANODE
CC
Related Resources
■ www.fairchildsemi.com/products/opto/
■ www.fairchildsemi.com/pf/FO/FODM8061.html
■ www.fairchildsemi.com/pf/FO/FODM611.html
O
CATHODE
GND
©2012 Fairchild Semiconductor Corporation
FOD8160 Rev. 1.0.1
www.fairchildsemi.com
Truth Table
Output
LED
Off
On
HIGH
LOW
Pin Definitions
Pin #
Name
Description
1
Anode
Anode
3
4
5
6
Cathode
GND
Cathode
Output Ground
Output Voltage
Output Supply Voltage
V
O
V
CC
Pin Configuration
1
6
5
4
V
V
ANODE
CATHODE
CC
O
3
GND
©2012 Fairchild Semiconductor Corporation
FOD8160 Rev. 1.0.1
www.fairchildsemi.com
2
Safety and Insulation Ratings
As per DIN EN/IEC60747-5-5 (pending approval), this optocoupler is suitable for “safe electrical insulation” only within
the safety limit data below. Compliance with the safety ratings shall be ensured by means of protective circuits.
Symbol
Parameter
Installation Classifications per DIN VDE 0110/1.89 Table 1
For Rated Mains Voltage < 150 Vrms
For Rated Mains Voltage < 300 Vrms
For Rated Mains Voltage < 450 Vrms
For Rated Mains Voltage < 600 Vrms
Climatic Classification
Min.
Typ.
Max. Unit
I–IV
I–IV
I–IV
I–IV
40/100/21
2
Pollution Degree (DIN VDE 0110/1.89)
Comparative Tracking Index
CTI
175
V
Input to Output Test Voltage, Method b,
2,651
V
V
PR
peak
V
x 1.875 = V , 100% Production Test with
IORM
PR
t
= 1 s, Partial Discharge < 5 pC
m
Input to Output Test Voltage, Method a,
x 1.5 = V , Type and Sample Test with
2,121
peak
V
IORM
PR
t
= 60 s, Partial Discharge < 5 pC
m
V
Maximum Working Insulation Voltage
Highest Allowable Over Voltage
External Creepage
1,414
8,000
10.0
10.0
0.5
V
V
IORM
peak
V
IOTM
peak
mm
mm
mm
External Clearance
Insulation Thickness
Safety Limit Values – Maximum Values Allowed in the
Event of a Failure
T
Case Temperature
Input Current
150
200
600
°C
mA
mW
Ω
S
I
S,INPUT
P
Output Power
S,OUTPUT
9
R
Insulation Resistance at T , V = 500 V
10
IO
S
IO
©2012 Fairchild Semiconductor Corporation
FOD8160 Rev. 1.0.1
www.fairchildsemi.com
3
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only. T = 25°C unless otherwise specified.
A
Symbol
Parameter
Value
Units
°C
T
Storage Temperature
-40 to +125
-40 to +100
-40 to +125
260 for 10 sec
STG
T
Operating Temperature
Junction Temperature
°C
OPR
T
°C
J
T
Lead Solder Temperature
°C
SOL
(Refer to Reflow Temperature Profile on page 12)
Input Characteristics
I
Average Forward Input Current
Reverse Input Voltage
25
5.0
45
mA
V
F
V
R
(1)
PD
Input Power Dissipation
mW
I
Output Characteristics
V
Supply Voltage
0 to 7.0
V
V
CC
V
Output Voltage
-0.5 to V + 0.5
O
CC
I
Average Output Current
Output Power Dissipation
50
85
mA
mW
O
(1)
PD
O
Note:
1. No derating required up to 100°C.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
Parameter
Min.
Max.
Unit
T
Ambient Operating Temperature
-40
3.0
0
+100
5.5
ºC
A
(2)
V
Supply Voltages
V
CC
V
Logic Low Input Voltage
Logic Low Input Current
Logic High Input Current
0.8
V
µA
FL
FL
I
250
15
I
6.0
mA
FH
N
Fan Out (at R = 1 kΩ)
5
TTL loads
Ω
L
R
Output Pull-up Resistor
330
4,000
L
Note:
2. 0.1 µF bypass capacitor must be connected between pins 4 and 6.
©2012 Fairchild Semiconductor Corporation
FOD8160 Rev. 1.0.1
www.fairchildsemi.com
4
Isolation Characteristics
Apply over all recommended conditions; typical value is measured at T = 25°C.
A
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
V
Input-Output Isolation
Voltage
T = 25°C, R.H. < 50%, t = 1.0 min,
5,000
VAC
RMS
ISO
A
(3)(4)
I
≤ 20 µA
I-O
(3)
11
R
C
Isolation Resistance
Isolation Capacitance
V
= 500 V
I-O
10
Ω
ISO
(3)
V
= 0 V, frequency = 1.0 MHz
1.0
pF
ISO
I-O
Notes:
3. Device is considered a two-terminal device: pins 1 and 3 are shorted together and pins 4, 5, and 6 are shorted
together.
4. 5,000 VAC
for 1-minute duration is equivalent to 6,000 VAC
for 1-second duration.
RMS
RMS
Electrical Characteristics
Apply over all recommended conditions; T = -40°C to +100°C, 3.0 V ≤ V ≤ 5.5 V; unless otherwise specified.
A
CC
Typical value is measured at T = 25°C and V = 3.3 V or V = 5 V.
A
CC
CC
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Figure
INPUT CHARACTERISTICS
Forward Voltage
V
I = 10 mA
1.05
5.0
1.45
-1.8
1.80
V
1
F
F
Δ(V / T ) Temperature Coefficient
mV/°C
F
A
of Forward Voltage
BV
Input Reverse
I = 10 µA
V
R
R
Breakdown Voltage
I
Threshold Input Current V = 0.6 V,
2.5
0.4
6.0
0.6
mA
2
3
FHL
O
I
(sink) = 13 mA
OL
OUTPUT CHARACTERISTICS
V
Logic Low Output
Voltage
I = rated I ,
FHL
V
OL
F
I
(sink) = 13 mA
OL
I
Logic High Output
Current
I = 250 µA, V = 3.3 V
8.0
3.0
5.3
7.1
3.5
5.3
50.0
40.0
8.5
µA
µA
4
OH
F
O
I = 250 µA, V = 5.0 V
4
F
O
I
Logic Low Output
Supply Current
I = 10 mA, V = 3.3 V
mA
mA
mA
mA
5, 7
5, 7
6, 7
6, 7
CCL
F
CC
I = 10 mA, V = 5.0 V
10.0
7.0
F
CC
I
Logic High Output
Supply Current
I = 0 mA, V = 3.3 V
F CC
CCH
I = 0 mA, V = 5.0 V
9.0
F
CC
©2012 Fairchild Semiconductor Corporation
FOD8160 Rev. 1.0.1
www.fairchildsemi.com
5
Switching Characteristics
Apply over all recommended conditions; T = -40°C to +100°C, V = 3.3 V, I = 6.0 mA; unless otherwise specified.
A
CC
F
Typical value is measured at T = 25°C and V = 3.3 V.
A
CC
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Figure
Data Rate
R = 350 Ω
10
80
Mbit/sec
ns
L
t
Propagation Delay to
Logic Low Output
R = 350 Ω, C = 15 pF
40
50
10
8, 9, 13
8, 9, 13
PHL
L
L
t
Propagation Delay to
Logic High Output
R = 350 Ω, C = 15 pF
90
35
40
ns
ns
PLH
L
L
PWD
Pulse Width Distortion, R = 350 Ω, C = 15 pF
10, 11,
13
L
L
| t
– t
|
PHL
PLH
t
Propagation Delay Skew R = 350 Ω, C = 15 pF
ns
PSK
L
L
(5)
t
Output Rise Time
(10% to 90%)
R = 350 Ω, C = 15 pF
20
10
40
ns
12, 13
12, 13
14
R
L
L
t
Output Fall Time
(90% to 10%)
R = 350 Ω, C = 15 pF
ns
F
L
L
| CM |
Common-Mode
Transient Immunity at
Output High
I = 0 mA, V > 2 V,
20
20
kV/µs
H
F
O
(6)
V
= 1,000 V
CM
| CM |
Common-Mode
Transient Immunity at
Output Low
I = 6.0 mA, V < 0.8 V,
40
kV/µs
14
L
F
O
(6)
V
= 1,000 V
CM
Apply over all recommended conditions; T = -40°C to +100°C, V = 5 V, I = 6.0 mA; unless otherwise specified.
A
CC
F
Typical value is measured at T = 25°C and V = 5 V.
A
CC
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Figure
Data Rate
R = 350 Ω
10
80
Mbit/sec
ns
L
t
Propagation Delay to
Logic Low Output
R = 350 Ω, C = 15 pF
37
41
4
8, 9, 13
8, 9, 13
PHL
L
L
t
Propagation Delay to
Logic High Output
R = 350 Ω, C = 15 pF
90
25
40
ns
ns
PLH
L
L
PWD
Pulse Width Distortion, R = 350 Ω, C = 15 pF
10, 11,
13
L
L
| t
– t
|
PHL
PLH
t
Propagation Delay Skew RL = 350 Ω, CL = 15 pF(5)
ns
ns
PSK
t
Output Rise Time
(10% to 90%)
R = 350 Ω, C = 15 pF
22
9
12, 13
12, 13
14
R
L
L
t
Output Fall Time
(90% to 10%)
R = 350 Ω, C = 15 pF
ns
F
L
L
| CM |
Common-Mode
Transient Immunity at
Output High
I = 0 mA, V > 2 V,
20
20
40
kV/µs
H
F
O
(6)
V
= 1,000 V
CM
| CM |
Common-Mode
Transient Immunity at
Output Low
I = 6.0 mA, V < 0.8 V,
40
kV/µs
14
L
F
O
(6)
V
= 1,000 V
CM
©2012 Fairchild Semiconductor Corporation
FOD8160 Rev. 1.0.1
www.fairchildsemi.com
6
Notes:
5. t
is equal to the magnitude of the worst-case difference in t
and/or t
between any two units from the same
PSK
PHL
PLH
manufacturing date code that are operated at same case temperature( 5°C), at same operating conditions, with
equal loads (R = 350 Ω, C = 15 pF), and with an input rise time less than 5 ns.
L
L
6. Common-mode transient immunity at output HIGH is the maximum tolerable positive dVcm/dt on the leading edge
of the common-mode impulse signal, V , to assure that the output remains HIGH. Common-mode transient
CM
immunity at output LOW is the maximum tolerable negative dVcm/dt on the trailing edge of the common pulse signal,
V
, to assure that the output remains LOW.
CM
©2012 Fairchild Semiconductor Corporation
FOD8160 Rev. 1.0.1
www.fairchildsemi.com
7
Typical Performance Characteristics
100
3.0
2.5
2.0
1.5
1.0
I
= 13 mA
OL
10
1
V
CC
= 3.3 V
V
= 5.0 V
CC
0.1
-40°C
25°C
T
A
= 100°C
0.01
0.001
-40
-20
0
20
40
60
80
100
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
TA – AMBIENT TEMPERATURE (°C)
VF – FORWARD VOLTAGE (V)
Figure 2.Threshold Input Current (I
) vs. Ambient Temperature
Figure 1. Input LED Current (I ) vs. Forward Voltage (V )
FHL
F
F
30
0.50
0.45
0.40
0.35
0.30
0.25
0.20
I = 250 μA
F
I
I
= 13 mA
OL
= 6 mA
V
= 3.3 V / 5.0 V
O
F
25
20
15
10
5
V
= 3.3 V
CC
V
= 5.0 V
CC
V
= 3.3 V
= 5.0 V
CC
V
CC
40
0
-40
-20
0
20
60
80
100
-40
-20
0
20
40
60
80
100
TA – AMBIENT TEMPERATURE (°C)
TA – AMBIENT TEMPERATURE (°C)
Figure 4. Logic High Output Current (I
vs. Ambient Temperature
)
Figure 3. Logic Low Output Voltage (V
vs. Ambient Temperature
)
OH
OL
10
8
10
8
I
= 10 mA
I = 0 mA
F
F
V
= 5.0 V
CC
6
6
V
CC
= 5.0 V
V
CC
= 3.3 V
4
4
V
CC
= 3.3 V
2
2
0
-40
0
-40
-20
0
20
40
60
80
100
-20
0
20
40
60
80
100
TA – AMBIENT TEMPERATURE (°C)
TA – AMBIENT TEMPERATURE (°C)
Figure 5. Logic Low Output Supply Current (I
vs. Ambient Temperature
)
Figure 6. Logic High Output Supply Current (I
)
CCH
CCL
vs. Ambient Temperature
©2012 Fairchild Semiconductor Corporation
FOD8160 Rev. 1.0.1
www.fairchildsemi.com
8
Typical Performance Characteristics (Continued)
10
80
70
60
50
40
30
20
I
T
= 0 mA (for I
), 10 mA (for I
CCL
)
Frequency = 5 MHz, 50% Duty Cycle
I = 6 mA, R = 350 Ω
F
F
CCH
= 25°C
A
L
8
6
4
2
0
I
CCL
t
@ V = 3.3 V
CC
PLH
I
CCH
t
@ V = 5.0 V
CC
PLH
t
@ V = 3.3 V
CC
PHL
t
@ V = 5.0 V
CC
PHL
3.0
3.5
4.0
4.5
5.0
5.5
-40
-20
0
20
40
60
80
100
VCC – OUTPUT SUPPLY VOLTAGE (V)
TA – AMBIENT TEMPERATURE (°C)
Figure 8. Propagation Delay vs. Ambient Temperature
Figure 7. Output Supply Current (I
)
CC
)
vs. Output Supply Voltage (V
CC
70
60
50
40
30
20
20
16
12
8
Frequency = 5 MHz, 50% Duty Cycle
= 350 Ω, T = 25°C
Frequency = 5 MHz, 50% Duty Cycle
R
L
I
F
= 6 mA, R = 350 Ω
A
L
V
CC
= 3.3 V
t
@ V
CC
= 3.3 V
= 5.0 V
PLH
t
@ V
CC
PLH
t
@ V
= 3.3 V
PHL
CC
V
CC
= 5.0 V
4
t
@ V = 5.0 V
CC
PHL
0
-40
5
6
7
8
9
10
-20
0
20
40
60
80
100
IF – INPUT LED CURRENT (mA)
TA – AMBIENT TEMPERATURE (°C)
Figure 9. Propagation Delay vs. Input LED Current (I )
F
Figure 10. Pulse Width Distortion vs. Ambient Temperature
40
25
20
15
10
5
Frequency = 5 MHz, 50% Duty Cycle
Frequency = 5 MHz, 50% Duty Cycle
I = 6 mA, R = 350 Ω
F
R
L
= 350 Ω, T = 25°C
A
L
30
20
10
0
V
= 3.3 V
CC
t
t
@ V
@ V
= 5.0 V
= 3.3 V
R
CC
R
CC
V
CC
= 5.0 V
t
t
@ V
@ V
= 3.3 V
= 5.0 V
F
CC
F
CC
0
-40
-20
0
20
40
60
80
100
5
6
7
8
9
10
TA – AMBIENT TEMPERATURE (°C)
IF – INPUT LED CURRENT (mA)
Figure 12. Rise Time (t ) and Fall Time (t )
Figure 11. Pulse Width Distortion vs. Input LED Current (I )
R
F
F
vs. Ambient Temperature
©2012 Fairchild Semiconductor Corporation
FOD8160 Rev. 1.0.1
www.fairchildsemi.com
9
Test Circuit
I
F
Pulse Gen.
5 MHz
t = tr = 5 ns
f
DC = 50%
0.1 μF
Bypass
350 Ω
V
Node
Monitoring
O
C
L
Input
Monitoring
Mode
R
M
(I = 6 mA)
F
Input
50%
t
f
t
r
90%
1.5 V
10%
Output
V
OL
t
t
PLH
PHL
Figure 13.Test Circuit for Propagation Delay, Rise Time, and Fall Time
I
F
V
V
CC
0.1 μF
Bypass
350 Ω
Monitoring
O
Node
SW
C
L
R
M
V
CM
Pulse Gen
1 kV
0 V
V
CM
90%
10%
t
r
t
f
V
OH
V
V
(I = 0 mA)
F
O
2 V
0.8 V
(I = 6 mA)
F
O
V
OL
Figure 14.Test Circuit for Instantaneous Common-Mode Rejection Voltage
©2012 Fairchild Semiconductor Corporation
FOD8160 Rev. 1.0.1
www.fairchildsemi.com
10
Ordering Information
Part Number
Package
Packing Method
Tube (100 units per tube)
FOD8160
Wide Body SOP 5-Pin
Wide Body SOP 5-Pin
FOD8160R2
Tape and Reel (1,000 units per reel)
FOD8160V
(Preliminary)
Wide Body SOP 5-Pin, DIN EN/IEC60747-5-5 Option Tube (100 units per tube)
(Pending Approval)
FOD8160R2V
(Preliminary)
Wide Body SOP 5-Pin, DIN EN/ IEC60747-5-5 Option Tape and Reel (1,000 units per reel)
(Pending Approval)
All packages are lead free per JEDEC: J-STD-020B standard.
Marking Information
1
2
3
V
8160
8
D X YY KK W
6
4
5
7
Definitions
1
2
3
Fairchild logo
Device number, e.g., ‘8160’ for FOD8160
DIN EN/IEC60747-5-5 option (only appears on
component ordered with this option)
4
5
6
7
8
Plant code, e.g., ‘D’
Last-digit year code, e.g., ‘D’ for 2013
Two-digit work week ranging from ‘01’ to ‘53’
Lot-traceability code
Package assembly code, W
©2012 Fairchild Semiconductor Corporation
FOD8160 Rev. 1.0.1
www.fairchildsemi.com
11
Reflow Profile
Max. Ramp-up Rate = 3°C/s
Max. Ramp-down Rate = 6°C/s
T
P
260
240
220
200
180
160
140
120
100
80
t
P
T
L
T
smax
t
L
Preheat Area
T
smin
t
s
60
40
20
0
120
Time 25°C to Peak
240
360
Time (seconds)
Profile Freature
Pb-Free Assembly Profile
150°C
Temperature Minimum (T
)
smin
Temperature Maximum (T
)
200°C
smax
Time (t ) from (T
to T )
smax
60–120 Seconds
3°C/Second max.
217°C
S
smin
Ramp-Up Rate (t to t )
L
P
Liquidous Temperature (T )
L
Time (t ) Maintained Above (T )
60–150 Seconds
260°C +0°C / –5°C
30 Seconds
L
L
Peak Body Package Temperature
Time (t ) within 5°C of 260°C
P
Ramp-Down Rate (T to T )
6°C/Second max.
8 Minutes max.
P
L
Time 25°C to Peak Temperature
©2012 Fairchild Semiconductor Corporation
FOD8160 Rev. 1.0.1
www.fairchildsemi.com
12
Package Dimensions
0.20 C A-B
D
3.95
0.60
2X
1.27
4
6
1.38
1.27
A
6
4
4.60
11.38
11.80
11.60
9.20
1
3
0.10 C D
3
1
2X
0.33 C
PIN ONE
INDICATOR
2.54
2.54
0.25
C A-B D
B
5X
LAND PATTERN
RECOMMENDATION
0.51
0.31
5 TIPS
2.65
2.45
A
0.10 C
SEATING
PLANE
2.90
2.60
0.10 C
0.30
0.10
5X
C
NOTES: UNLESS OTHERWISE SPECIFIED
1.35
1.15
A) THIS PACKAGE DOES NOT
CONFORM TO ANY STANDARD.
B) ALL DIMENSIONS ARE IN
MILLIMETERS.
(R0.54)
C) DIMENSIONS ARE EXCLUSIVE OF
BURRS, MOLD FLASH AND TIE BAR
PROTRUSIONS
D) DRAWING CONFORMS TO ASME
Y14.5M-1994
GAUGE
PLANE
0.25
0.19
8°
0°
E) DRAWING FILE NAME:
MKT-M05AREV2
0.74
0.44
0.25
(R1.29)
C
SEATING
PLANE
SCALE: 3.2:1
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©2012 Fairchild Semiconductor Corporation
FOD8160 Rev. 1.0.1
www.fairchildsemi.com
13
Carrier Tape Specification (SOIC-5L OPTO R2 & R2V Option)
Po
P2
Do
E
t
F
W
W1
Bo
d
K1
Ko
P
Ao
D1
User Direction of Feed
Symbol
Description
Dimmension in mm
W
t
Tape Width
24.00 +0.20 / -0.10
0.30 0.05
Tape Thickness
Po
Do
D1
E
Sprocket Hole Pitch
Sprocket Hole Diameter
Pocket Hole Diameter
Sprocket Hole Location
Pocket Location
4.00 0.20
1.50 +0.10 / -0.00
1.50 +0.25 / -0.00
1.75 0.10
F
11.50 0.10
2.00 0.10
P2
P
Pocket Pitch
8.00 0.10
Ao
Bo
Ko
K1
W1
d
Pocket Dimension
4.50 0.10
12.00 0.10
3.35 0.10
2.85 0.10
Cover Tape Width
21.30 0.10
0.05 0.01
Cover Tape Thickness
Max Component Rotation or Tilt
10°
©2012 Fairchild Semiconductor Corporation
FOD8160 Rev. 1.0.1
www.fairchildsemi.com
14
©2012 Fairchild Semiconductor Corporation
FOD8160 Rev. 1.0.1
www.fairchildsemi.com
15
相关型号：
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