FQB12N20L [FAIRCHILD]
200V LOGIC N-Channel MOSFET; LOGIC 200V N沟道MOSFET型号: | FQB12N20L |
厂家: | FAIRCHILD SEMICONDUCTOR |
描述: | 200V LOGIC N-Channel MOSFET |
文件: | 总9页 (文件大小:609K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
February 2001
FQB12N20L / FQI12N20L
200V LOGIC N-Channel MOSFET
General Description
Features
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for high efficiency switching DC/DC converters,
switch mode power supply, motor control.
•
•
•
•
•
•
•
11.6A, 200V, R
= 0.28Ω @V = 10 V
DS(on) GS
Low gate charge ( typical 16 nC)
Low Crss ( typical 17 pF)
Fast switching
100% avalanche tested
Improved dv/dt capability
Low level gate drive requirement allowing direct
opration from logic drivers
D
!
D
"
! "
"
!
G
"
G
S
D2-PAK
FQB Series
I2-PAK
FQI Series
G
D
S
!
S
Absolute Maximum Ratings
T = 25°C unless otherwise noted
C
Symbol
Parameter
FQB12N20L / FQI12N20L
Units
V
V
I
Drain-Source Voltage
200
11.6
DSS
- Continuous (T = 25°C)
Drain Current
A
D
C
- Continuous (T = 100°C)
7.35
46.4
± 20
210
A
C
I
(Note 1)
Drain Current
- Pulsed
A
DM
V
E
I
Gate-Source Voltage
V
GSS
(Note 2)
(Note 1)
(Note 1)
(Note 3)
Single Pulsed Avalanche Energy
Avalanche Current
mJ
A
AS
11.6
AR
E
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
9.0
mJ
V/ns
W
AR
dv/dt
5.5
Power Dissipation (T = 25°C) *
3.5
P
A
D
Power Dissipation (T = 25°C)
90
W
C
- Derate above 25°C
Operating and Storage Temperature Range
0.72
-55 to +150
W/°C
°C
T , T
J
STG
Maximum lead temperature for soldering purposes,
T
300
°C
L
1/8" from case for 5 seconds
Thermal Characteristics
Symbol
Parameter
Typ
--
Max
1.39
40
Units
°C/W
°C/W
°C/W
R
R
R
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient *
Thermal Resistance, Junction-to-Ambient
θJC
θJA
θJA
--
--
62.5
* When mounted on the minimum pad size recommended (PCB Mount)
©2001 Fairchild Semiconductor Corporation
Rev. A1, February 2001
Electrical Characteristics
T = 25°C unless otherwise noted
C
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BV
V
= 0 V, I = 250 µA
GS D
Drain-Source Breakdown Voltage
200
--
--
--
--
V
DSS
∆BV
Breakdown Voltage Temperature
Coefficient
DSS
I
= 250 µA, Referenced to 25°C
0.14
V/°C
D
/
∆T
J
I
V
V
V
V
= 200 V, V = 0 V
--
--
--
--
--
--
--
--
1
µA
µA
nA
nA
DSS
DS
GS
Zero Gate Voltage Drain Current
= 160 V, T = 125°C
10
DS
GS
GS
C
I
= 20 V, V = 0 V
Gate-Body Leakage Current, Forward
Gate-Body Leakage Current, Reverse
100
-100
GSSF
DS
I
= -20 V, V = 0 V
GSSR
DS
On Characteristics
V
V
V
V
V
= V , I = 250 µA
Gate Threshold Voltage
1.0
--
--
2.0
V
Ω
S
GS(th)
DS
GS
D
= 10 V, I = 5.8 A
R
Static Drain-Source
On-Resistance
0.22
0.25
0.28
0.32
GS
GS
D
DS(on)
= 5 V, I = 5.8 A
D
(Note 4)
g
= 30 V, I = 5.8 A
Forward Transconductance
--
12.7
--
FS
DS
D
Dynamic Characteristics
C
C
C
Input Capacitance
--
--
--
830
120
17
1080
155
22
pF
pF
pF
iss
V
= 25 V, V = 0 V,
GS
DS
Output Capacitance
oss
rss
f = 1.0 MHz
Reverse Transfer Capacitance
Switching Characteristics
t
t
t
t
Turn-On Delay Time
Turn-On Rise Time
Turn-Off Delay Time
Turn-Off Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
--
--
--
--
--
--
--
15
190
60
40
390
130
250
21
ns
ns
d(on)
V
= 100 V, I = 11.6 A,
DD
D
r
R
= 25 Ω
G
ns
d(off)
f
(Note 4, 5)
(Note 4, 5)
120
16
ns
Q
Q
Q
nC
nC
nC
g
V
V
= 160 V, I = 11.6 A,
DS
D
2.8
7.6
--
= 5 V
gs
gd
GS
--
Drain-Source Diode Characteristics and Maximum Ratings
I
Maximum Continuous Drain-Source Diode Forward Current
--
--
--
--
--
--
--
11.6
46.4
1.5
--
A
A
S
I
Maximum Pulsed Drain-Source Diode Forward Current
SM
V
t
V
V
= 0 V, I = 11.6 A
Drain-Source Diode Forward Voltage
Reverse Recovery Time
--
V
SD
GS
S
= 0 V, I = 11.6 A,
128
0.56
ns
µC
rr
GS
S
(Note 4)
dI / dt = 100 A/µs
Q
Reverse Recovery Charge
--
F
rr
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 2.3mH, I = 11.6A, V = 50V, R = 25 Ω, Starting T = 25°C
AS
DD
G
J
3. I ≤ 11.6A, di/dt ≤ 300A/µs, V ≤ BV Starting T = 25°C
SD
DD
DSS, J
4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2%
5. Essentially independent of operating temperature
©2001 Fairchild Semiconductor Corporation
Rev. A1, February 2001
Typical Characteristics
VGS
Top :
10 V
8.0V
6.0V
5.0V
4.5V
4.0V
3.5V
101
101
℃
150
Bottom : 3.0 V
100
100
℃
25
※
Notes :
μ
℃
-55
※
Notes :
1. 250 s Pulse Test
℃
2. TC = 25
1. V = 30V
DS μ
2. 250 s Pulse Test
-1
-1
10
10
-1
100
101
0
2
4
6
8
10
10
VGS, Gate-Source Voltage [V]
VDS , Drain-Source Voltage [V]
Figure 1. On-Region Characteristics
Figure 2. Transfer Characteristics
1.5
1.2
0.9
0.6
0.3
0.0
101
VGS = 5 V
VGS = 10V
100
℃
℃
25
150
※
Notes :
1. V = 0V
2. 250 s Pulse Test
GS μ
-1
10
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0
6
12
18
24
30
36
ID , Drain Current [A]
VSD, Source-Drain voltage [V]
Figure 3. On-Resistance Variation vs.
Drain Current and Gate Voltage
Figure 4. Body Diode Forward Voltage
Variation vs. Source Current
and Temperature
12
10
8
1800
1500
1200
900
600
300
0
C
iss = Cgs + Cgd (Cds = shorted)
Coss = Cds + C
gd
Crss = C
gd
VDS = 40V
VDS = 100V
VDS = 160V
C
iss
6
Coss
※
Notes :
4
1. VGS = 0 V
2. f = 1 MHz
C
rss
2
※
Note : ID = 11.6 A
25
0
-1
10
100
101
0
5
10
15
20
30
QG, Total Gate Charge [nC]
VDS, Drain-Source Voltage [V]
Figure 5. Capacitance Characteristics
Figure 6. Gate Charge Characteristics
©2001 Fairchild Semiconductor Corporation
Rev. A1, February 2001
Typical Characteristics (Continued)
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1.2
1.1
1.0
※Notes :
1. VGS = 0 V
2. ID = 250 μA
0.9
0.8
※
Notes :
1. VGS = 10 V
2. ID = 5.8 A
-100
-50
0
50
100
150
200
-100
-50
0
50
100
150
200
TJ, Junction Temperature [oC]
T, Junction Temperature [oC]
J
Figure 7. Breakdown Voltage Variation
vs. Temperature
Figure 8. On-Resistance Variation
vs. Temperature
12
9
Operation in This Area
102
is Limited by R DS(on)
100 µs
1 ms
10 ms
101
100
6
DC
3
※
Notes :
1. TC = 25 o
2. TJ = 150 o
C
C
3. Single Pulse
-1
0
25
10
100
101
102
50
75
100
125
150
℃
TC, Case Temperature [
]
VDS, Drain-Source Voltage [V]
Figure 9. Maximum Safe Operating Area
Figure 10. Maximum Drain Current
vs. Case Temperature
1 0 0
D = 0 .5
※
N o te s
1 . Z θ J C(t)
2 . D u ty F a c to r, D = t1 /t2
:
0 .2
0 .1
℃
/W M a x.
=
1 .3 9
3 . T J M
-
T C
=
P D
* Z θ J C(t)
M
1 0 -1
0 .0 5
PDM
0 .0 2
0 .0 1
t1
s in g le p u ls e
t2
1 0 -2
1 0 -5
1 0 -4
1 0 -3
1 0 -2
1 0 -1
1 0 0
1 0 1
t1 , S q u a re W a v e P u ls e D u ra tio n [s e c ]
Figure 11. Transient Thermal Response Curve
©2001 Fairchild Semiconductor Corporation
Rev. A1, February 2001
Gate Charge Test Circuit & Waveform
VGS
Same Type
50KΩ
as DUT
Qg
12V
200nF
5V
300nF
VDS
VGS
Qgs
Qgd
DUT
3mA
Charge
Resistive Switching Test Circuit & Waveforms
RL
VDS
90%
VDS
VDD
VGS
RG
10%
VGS
DUT
5V
td(on)
tr
td(off)
tf
t on
t off
Unclamped Inductive Switching Test Circuit & Waveforms
BVDSS
--------------------
BVDSS - VDD
L
1
2
2
----
EAS
=
LIAS
VDS
ID
BVDSS
IAS
RG
VDD
ID (t)
VDD
VDS (t)
DUT
10V
t p
t p
Time
©2001 Fairchild Semiconductor Corporation
Rev. A1, February 2001
Peak Diode Recovery dv/dt Test Circuit & Waveforms
+
DUT
VDS
_
I SD
L
Driver
RG
Same Type
as DUT
VDD
VGS
• dv/dt controlled by RG
• ISD controlled by pulse period
Gate Pulse Width
--------------------------
VGS
D =
Gate Pulse Period
10V
( Driver )
IFM , Body Diode Forward Current
I SD
di/dt
( DUT )
IRM
Body Diode Reverse Current
Body Diode Recovery dv/dt
VSD
VDS
( DUT )
VDD
Body Diode
Forward Voltage Drop
©2001 Fairchild Semiconductor Corporation
Rev. A1, February 2001
Package Dimensions
D2PAK
4.50 ±0.20
9.90 ±0.20
+0.10
–0.05
1.30
0.10 ±0.15
2.40 ±0.20
0.80 ±0.10
1.27 ±0.10
+0.10
0.50
–0.05
2.54 TYP
2.54 TYP
10.00 ±0.20
(8.00)
(4.40)
10.00 ±0.20
(2XR0.45)
0.80 ±0.10
©2001 Fairchild Semiconductor Corporation
Rev. A1, February 2001
Package Dimensions (Continued)
I2PAK
4.50 ±0.20
9.90 ±0.20
+0.10
–0.05
1.30
1.27 ±0.10
1.47 ±0.10
0.80 ±0.10
+0.10
–0.05
0.50
2.40 ±0.20
2.54 TYP
2.54 TYP
10.00 ±0.20
©2001 Fairchild Semiconductor Corporation
Rev. A1, February 2001
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not
intended to be an exhaustive list of all such trademarks.
SyncFET™
TinyLogic™
VCX™
ACEx™
FASTr™
GlobalOptoisolator™
GTO™
PowerTrench®
QFET™
QS™
QT Optoelectronics™
Quiet Series™
LILENT SWITCHER®
SMART START™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
Bottomless™
CoolFET™
CROSSVOLT™
DOME™
UHC™
HiSeC™
ISOPLANAR™
MICROWIRE™
OPTOLOGIC™
OPTOPLANAR™
PACMAN™
POP™
E2CMOS™
EnSigna™
FACT™
FACT Quiet Series™
FAST®
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR
INTERNATIONAL.
As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or In
Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Obsolete
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
©2001 Fairchild Semiconductor Corporation
Rev. G
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