FQI13N50_技术文档

March 2001

TM

QFET

FQB13N50 / FQI13N50

500V N-Channel MOSFET

General Description

Features

These N-Channel enhancement mode power field effect

transistors are produced using Fairchild’s proprietary,

planar stripe, DMOS technology.

•

12.5A, 500V. R

= 0.43Ω @V = 10 V

DS(on) GS

Low gate charge ( typical 45 nC).

Low Crss ( typical 25 pF).

Fast switching.

100% avalanche tested.

Improved dv/dt capability.

This advanced technology is especially tailored to minimize

on-state

resistance,

provide

superior

switching

performance, and withstand high energy pulse in the

avalanche and commutation mode. These devices are well

suited for high efficiency switch mode power supply, power

factor correction, and electronic lamp ballast based on half

bridge.

D

!

D

●

◀

▲

●

G!

G

S

D²-PAK

FQB Series

I²-PAK

FQI Series

G

D

S

!

S

Absolute Maximum Ratings

T = 25°C unless otherwise noted

C

Symbol

Parameter

FQB13N50 / FQI13N50

Units

V

I

Drain-Source Voltage

500

12.5

7.9

DSS

- Continuous (T = 25°C)

Drain Current

A

D

C

- Continuous (T = 100°C)

A

C

I

(Note 1)

Drain Current

- Pulsed

50

A

DM

V

E

I

Gate-Source Voltage

± 30

810

V

GSS

(Note 2)

(Note 1)

(Note 3)

Single Pulsed Avalanche Energy

Avalanche Current

mJ

A

AS

12.5

17

AR

E

Repetitive Avalanche Energy

Peak Diode Recovery dv/dt

mJ

V/ns

W

AR

dv/dt

4.5

Power Dissipation (T = 25°C) *

3.13

170

P

A

D

Power Dissipation (T = 25°C)

W

C

- Derate above 25°C

Operating and Storage Temperature Range

1.35

-55 to +150

W/°C

°C

T , T

J

STG

Maximum lead temperature for soldering purposes,

T

300

°C

L

1/8" from case for 5 seconds

Thermal Characteristics

Symbol

Parameter

Typ

--

Max

0.74

40

Units

°C/W

R

Thermal Resistance, Junction-to-Case

Thermal Resistance, Junction-to-Ambient *

Thermal Resistance, Junction-to-Ambient

θJC

θJA

--

62.5

* When mounted on the minimum pad size recommended (PCB Mount)

Rev. A, March 2001

Electrical Characteristics

T = 25°C unless otherwise noted

C

Symbol

Parameter

Test Conditions

Min

Typ

Max

Units

Off Characteristics

BV

V

= 0 V, I = 250 µA

GS D

Drain-Source Breakdown Voltage

500

--

V

DSS

∆BV

Breakdown Voltage Temperature

Coefficient

DSS

I

= 250 µA, Referenced to 25°C

0.48

V/°C

D

/

∆T

J

I

V

= 500 V, V = 0 V

--

1

µA

nA

DSS

DS

GS

Zero Gate Voltage Drain Current

= 400 V, T = 125°C

10

DS

GS

C

I

= 30 V, V = 0 V

Gate-Body Leakage Current, Forward

Gate-Body Leakage Current, Reverse

100

-100

GSSF

DS

I

= -30 V, V = 0 V

GSSR

DS

On Characteristics

V

= V , I = 250 µA

Gate Threshold Voltage

3.0

--

5.0

0.43

--

V

Ω

S

GS(th)

DS

GS

DS

GS

D

R

Static Drain-Source

On-Resistance

DS(on)

= 10 V, I = 6.25 A

0.33

10

D

g

= 50 V, I = 6.25 A

(Note 4)

Forward Transconductance

--

FS

D

Dynamic Characteristics

C

Input Capacitance

--

1800

245

25

2300

320

35

pF

iss

V

= 25 V, V = 0 V,

GS

DS

Output Capacitance

oss

rss

f = 1.0 MHz

Reverse Transfer Capacitance

Switching Characteristics

t

Turn-On Delay Time

Turn-On Rise Time

Turn-Off Delay Time

Turn-Off Fall Time

Total Gate Charge

Gate-Source Charge

Gate-Drain Charge

--

40

140

100

85

90

290

210

180

60

ns

d(on)

V

= 250 V, I = 13.4 A,

DD

D

r

R

= 25 Ω

G

ns

d(off)

f

(Note 4, 5)

ns

Q

45

nC

g

V

= 400 V, I = 13.4 A,

DS

D

11

--

= 10 V

gs

gd

GS

(Note 4, 5)

22

--

Drain-Source Diode Characteristics and Maximum Ratings

I

Maximum Continuous Drain-Source Diode Forward Current

--

12.5

50

1.4

--

A

S

I

Maximum Pulsed Drain-Source Diode Forward Current

SM

V

t

V

= 0 V, I = 12.5 A

Drain-Source Diode Forward Voltage

Reverse Recovery Time

--

V

SD

GS

S

= 0 V, I = 13.4 A,

290

2.6

ns

µC

rr

GS

S

(Note 4)

dI / dt = 100 A/µs

Q

Reverse Recovery Charge

--

F

rr

Notes:

1. Repetitive Rating : Pulse width limited by maximum junction temperature

2. L = 9.3mH, I = 12.5A, V = 50V, R = 25 Ω, Starting T = 25°C

AS

DD

G

J

3. I ≤ 13.4A, di/dt ≤ 200A/µs, V

≤ BV Starting T = 25°C

SD

DD

DSS, J

4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2%

5. Essentially independent of operating temperature

Rev. A, March 2001

Typical Characteristics

V

Top :

15^GV^S

10 V

8.0V

7.0V

6.5V

6.0V

10¹

Bottom : 5.5V

℃

150

℃

25

10⁰

℃

-55

10⁰

※

Notes :

※

Notes :

1. V = 50V

2. 250 s Pulse Test

^DSμ

μ

1. 250 s Pulse Test

℃

2. T_C= 25

-1

10

-1

10

10⁰

10¹

2

4

6

8

10

V_GS, Gate-Source Voltage [V]

V_DS, Drain-Source Voltage [V]

Figure 1. On-Region Characteristics

Figure 2. Transfer Characteristics

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

1

V_GS= 10V

V_GS= 20V

10

0

10

150℃

25℃

※

Notes :

1. V = 0V

^GSμ

2. 250 s Pulse Test

※

℃

Note : T = 25

J

-1

10

0

10

20

30

40

50

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

V_SD, Source-Drain Voltage [V]

I_D, Drain Current [A]

Figure 3. On-Resistance Variation vs.

Drain Current and Gate Voltage

Figure 4. Body Diode Forward Voltage

Variation vs. Source Current

and Temperature

3500

3000

2500

2000

1500

1000

500

12

10

8

C

_iss= C_gs+ C_gd(C_ds= shorted)

C_oss= C_ds+ C

gd

V_DS= 100V

V_DS= 250V

C_rss= C

gd

V_DS= 400V

C

iss

C

oss

6

※

Notes :

4

1. V_GS= 0 V

2. f = 1 MHz

C

rss

2

※

Note : I_D= 13.4 A

0

10

0

-1

0

10

1

10

0

5

10

15

20

25

30

35

40

45

50

Q_G, Total Gate Charge [nC]

V_DS, Drain-Source Voltage [V]

Figure 5. Capacitance Characteristics

Figure 6. Gate Charge Characteristics

Rev. A, March 2001

Typical Characteristics (Continued)

3.0

2.5

2.0

1.5

1.0

0.5

0.0

1.2

1.1

1.0

※

Notes:

1. V = 0 V

0.9

0.8

2. I_D^G=^S250

A

※

Notes :

1. V = 10 V

μ

2. I_D^G=^S6.7 A

-100

-50

0

50

100

150

200

-100

-50

0

50

100

150

200

T, Junction Temperature [^oC]

J

Figure 7. Breakdown Voltage Variation

vs. Temperature

Figure 8. On-Resistance Variation

vs. Temperature

15

12

9

Operation in This Area

10²

is Limited by R _DS(on)

10 µs

100 µs

1 ms

10¹

10 ms

DC

6

10⁰

※

Notes :

1. T_C= 25 ^o

2. T_J= 150 ^o

3. Single Pulse

3

C

-1

0

25

10

10⁰

10¹

10²

10³

50

75

100

125

150

℃

T_C, Case Temperature [

]

V_DS, Drain-Source Voltage [V]

Figure 9. Maximum Safe Operating Area

Figure 10. Maximum Drain Current

vs. Case Temperature

1 0 ⁰

D = 0 .5

0 .2

※

N otes

1. Z _θ_JC(t)

2. D uty F actor, D = t₁/t₂

:

1 0 ^-1

℃

/W M ax.

=

0.74

0 .1

3. T _JM

-

T _C

=

P _DM* Z _θ_JC(t)

0 .0 5

P_DM

0 .0 2

t₁

0 .0 1

sin g le p u ls e

t₂

1 0 ^-2

1 0 ^-5

1 0 ^-4

1 0 ^-3

1 0 ^-2

1 0 ^-1

1 0 ⁰

1 0 ¹

t₁, S q u a re W a v e P u ls e D u ra tio n [se c ]

Figure 11. Transient Thermal Response Curve

Rev. A, March 2001

Gate Charge Test Circuit & Waveform

V_GS

Same Type

as DUT

50Kꢀ

Q_g

10V

12V

200nF

300nF

V_DS

Q_gs

Q_gd

V_GS

DUT

3mA

Charge

Resistive Switching Test Circuit & Waveforms

R_L

V_DS

90%

V_DD

( 0.5 rated V_DS

)

R_G

10%

V_in

DUT

10V

t_d(on)

t_r

t_d(off)

t_f

t_on

t _off

Unclamped Inductive Switching Test Circuit & Waveforms

BV_DSS

--------------------

BV_DSS-- V_DD

L

1

2

----

E_AS

=

L_LI_AS

V_DS

2

V_DD

BV_DSS

I_AS

I _D

R_G

I_D(t)

DUT

V_DD

V_DS(t)

10V

t _p

Time

Rev. A, March 2001

Peak Diode Recovery dv/dt Test Circuit & Waveforms

DUT

+

V_DS

_

I _S

L

Driver

R_G

Same Type

as DUT

V_DD

V_GS

• dv/dt controlled by R_G

• I_Scontrolled by pulse period

Gate Pulse Width

--------------------------

V_GS

D =

Gate Pulse Period

10V

( Driver )

I_FM, Body Diode Forward Current

I _S

di/dt

( DUT )

I_RM

Body Diode Reverse Current

Body Diode Recovery dv/dt

V_f

V_DS

( DUT )

V_DD

Body Diode

Forward Voltage Drop

Rev. A, March 2001

Package Dimensions

D²PAK

4.50 ±0.20

9.90 ±0.20

+0.10

–0.05

1.30

0.10 ±0.15

2.40 ±0.20

0.80 ±0.10

1.27 ±0.10

+0.10

0.50

–0.05

2.54 TYP

10.00 ±0.20

(8.00)

(4.40)

10.00 ±0.20

(2XR0.45)

0.80 ±0.10

Rev. A, March 2001

Package Dimensions ^(Continued)

I²PAK

4.50 ±0.20

9.90 ±0.20

+0.10

–0.05

1.30

1.27 ±0.10

1.47 ±0.10

0.80 ±0.10

+0.10

–0.05

0.50

2.40 ±0.20

2.54 TYP

10.00 ±0.20

Rev. A, March 2001

TRADEMARKS

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not

intended to be an exhaustive list of all such trademarks.

FAST^®

PACMAN™

SuperSOT™-3

ACEx™

SuperSOT™-6

SuperSOT™-8

SyncFET™

TinyLogic™

UHC™

Bottomless™

CoolFET™

CROSSVOLT™

DenseTrench™

DOME™

EcoSPARK™

E²CMOS™

EnSigna™

FASTr™

GlobalOptoisolator™

GTO™

HiSeC™

ISOPLANAR™

LittleFET™

MicroFET™

MICROWIRE™

OPTOLOGIC™

OPTOPLANAR™

POP™

PowerTrench^®

QFET™

QS™

QT Optoelectronics™

Quiet Series™

SLIENT SWITCHER^®

SMART START™

Star* Power™

Stealth™

UltraFET^®

VCX™

FACT™

FACT Quiet Series™

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY

PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY

LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;

NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR

CORPORATION.

As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the body,

or (b) support or sustain life, or (c) whose failure to perform

when properly used in accordance with instructions for use

provided in the labeling, can be reasonably expected to

result in significant injury to the user.

2. A critical component is any component of a life support

device or system whose failure to perform can be

reasonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification

Product Status

Definition

Advance Information

Formative or In

Design

This datasheet contains the design specifications for

product development. Specifications may change in

any manner without notice.

Preliminary

First Production

This datasheet contains preliminary data, and

supplementary data will be published at a later date.

Fairchild Semiconductor reserves the right to make

changes at any time without notice in order to improve

design.

No Identification Needed

Obsolete

Full Production

This datasheet contains final specifications. Fairchild

Semiconductor reserves the right to make changes at

any time without notice in order to improve design.

Not In Production

This datasheet contains specifications on a product

that has been discontinued by Fairchild semiconductor.

The datasheet is printed for reference information only.

Rev. H1


型号：	FQI13N50
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	500V N-Channel MOSFET 500V N沟道MOSFET
文件：	总9页 (文件大小：626K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

FQI13N50 [FAIRCHILD]

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