FQT7N10L [FAIRCHILD]

100V LOGIC N-Channel MOSFET; LOGIC 100V N沟道MOSFET


型号：	FQT7N10L
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	100V LOGIC N-Channel MOSFET LOGIC 100V N沟道MOSFET 晶体晶体管功率场效应晶体管开关脉冲光电二极管
文件：	总8页 (文件大小：644K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

May 2001

QFET

FQT7N10L

100V LOGIC N-Channel MOSFET

General Description

Features

These N-Channel enhancement mode power field effect

transistors are produced using Fairchild’s proprietary,

planar stripe, DMOS technology.

This advanced technology has been especially tailored to

minimize on-state resistance, provide superior switching

performance, and withstand high energy pulse in the

avalanche and commutation mode. These devices are well

suited for low voltage applications such as high efficiency

switching DC/DC converters, and DC motor control.

•

1.7A, 100V, R

Low gate charge ( typical 4.6 nC)

Low Crss ( typical 12 pF)

Fast switching

Improved dv/dt capability

= 0.35Ω @V = 10 V

DS(on) GS

Low level gate drive requirments allowing

direct operationfrom logic drives

! "

SOT-223

FQT Series

Absolute Maximum Ratings

T = 25°C unless otherwise noted

Symbol

Parameter

FQT7N10L

100

Units

Drain-Source Voltage

DSS

- Continuous (T = 25°C)

Drain Current

1.7

- Continuous (T = 70°C)

1.36

6.8

(Note 1)

Drain Current

- Pulsed

Gate-Source Voltage

± 20

GSS

(Note 2)

(Note 1)

(Note 3)

Single Pulsed Avalanche Energy

Avalanche Current

1.7

Repetitive Avalanche Energy

Peak Diode Recovery dv/dt

0.2

V/ns

dv/dt

6.0

Power Dissipation (T = 25°C)

2.0

- Derate above 25°C

Operating and Storage Temperature Range

0.016

-55 to +150

W/°C

°C

T , T

STG

Maximum lead temperature for soldering purposes,

300

°C

1/8" from case for 5 seconds

Thermal Characteristics

Symbol

Parameter

Typ

Max

Units

Thermal Resistance, Junction-to-Ambient *

62.5

°C/W

θJA

* When mounted on the minimum pad size recommended (PCB Mount)

Rev. A, May 2001

Electrical Characteristics

T = 25°C unless otherwise noted

Symbol

Parameter

Test Conditions

Min

Typ

Max

Units

Off Characteristics

= 0 V, I = 250 µA

GS D

Drain-Source Breakdown Voltage

100

DSS

∆BV

Breakdown Voltage Temperature

Coefficient

DSS

= 250 µA, Referenced to 25°C

0.1

V/°C

∆T

= 100 V, V = 0 V

µA

DSS

Zero Gate Voltage Drain Current

= 80 V, T = 125°C

= 20 V, V = 0 V

Gate-Body Leakage Current, Forward

Gate-Body Leakage Current, Reverse

100

-100

GSSF

= -20 V, V = 0 V

GSSR

On Characteristics

= V , I = 250 µA

Gate Threshold Voltage

1.0

2.0

Ω

GS(th)

= 10 V, I = 0.85 A

Static Drain-Source

On-Resistance

0.275

0.300

0.35

0.38

DS(on)

= 5 V, I = 0.85 A

= 30 V, I = 0.85 A

Forward Transconductance

2.75

(Note 4)

Dynamic Characteristics

Input Capacitance

220

290

iss

= 25 V, V = 0 V,

Output Capacitance

oss

rss

f = 1.0 MHz

Reverse Transfer Capacitance

Switching Characteristics

Turn-On Delay Time

Turn-On Rise Time

Turn-Off Delay Time

Turn-Off Fall Time

Total Gate Charge

Gate-Source Charge

Gate-Drain Charge

210

110

6.0

d(on)

= 50 V, I = 7.3 A,

100

= 25 Ω

d(off)

(Note 4, 5)

4.6

1.0

2.6

= 80 V, I = 7.3 A,

= 5 V

Drain-Source Diode Characteristics and Maximum Ratings

Maximum Continuous Drain-Source Diode Forward Current

1.7

6.8

1.5

Maximum Pulsed Drain-Source Diode Forward Current

= 0 V, I = 1.7 A

Drain-Source Diode Forward Voltage

Reverse Recovery Time

= 0 V, I = 7.3 A,

140

(Note 4)

dI / dt = 100 A/µs

Reverse Recovery Charge

Notes:

1. Repetitive Rating : Pulse width limited by maximum junction temperature

2. L = 26mH, I = 1.7A, V = 25V, R = 25 Ω, Starting T = 25°C

3. I ≤ 7.3A, di/dt ≤ 300A/µs, V

≤ BV Starting T = 25°C

DSS, J

4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2%

5. Essentially independent of operating temperature

Rev. A, May 2001

Typical Characteristics

Top :

10.0^GV^S

8.0 V

6.0 V

5.0 V

4.5 V

4.0 V

3.5 V

Bottom: 3.0 V

℃

150

10⁰

℃

-55

※

Notes :

※

Notes :

1. V = 30V

2. 250 s Pulse Test

1. 250 s Pulse Test

2. T_C= 25

^DSμ

℃

-1

V_GS, Gate-Source Voltage [V]

V_DS, Drain-Source Voltage [V]

Figure 1. On-Region Characteristics

Figure 2. Transfer Characteristics

1.5

1.2

0.9

0.6

0.3

0.0

V_GS= 5V

10⁰

V_GS= 10V

℃

150

℃

※

Notes :

1. V = 0V

^GSμ

2. 250 s Pulse Test

※

℃

Note : T = 25

-1

0.2

0.4

0.6

0.8

1.0

1.2

1.4

V_SD, Source-Drain Voltage [V]

I_D, Drain Current [A]

Figure 3. On-Resistance Variation vs.

Drain Current and Gate Voltage

Figure 4. Body Diode Forward Voltage

Variation vs. Source Current

and Temperature

600

500

400

300

200

100

_iss= C_gs+ C_gd(C_ds= shorted)

C_oss= C_ds+ C_gd

_rss= C_gd

V_DS= 50V

V_DS= 80V

※

Notes :

1. V_GS= 0 V

2. f = 1 MHz

iss

C_oss

rss

※

Note : I_D= 7.3 A

10^-1

10⁰

10¹

Q_G, Total Gate Charge [nC]

V_DS, Drain-Source Voltage [V]

Figure 5. Capacitance Characteristics

Figure 6. Gate Charge Characteristics

Rev. A, May 2001

Typical Characteristics (Continued)

3.0

2.5

2.0

1.5

1.0

0.5

0.0

1.2

1.1

1.0

※Notes :

0.9

1. V_GS= 0 V

※

Notes :

2. I_D= 250 μA

1. V_GS= 10 V

2. I_D= 0.85 A

0.8

-100

-50

100

150

200

-100

-50

100

150

200

T, Junction Temperature [^oC]

Figure 7. Breakdown Voltage Variation

vs. Temperature

Figure 8. On-Resistance Variation

vs. Temperature

2.0

1.6

1.2

0.8

0.4

0.0

Operation in This Area

is Limited by R _DS(on)

10¹

100 µs

1 ms

10 ms

100 ms

10⁰

-1

※

Notes :

1. T_C= 25 ^oC

2. T = 150 ^oC

3. Single Pulse

-2

10⁰

10¹

10²

-1

100

125

150

℃

T_C, Case Temperature [

]

V_DS, Drain-Source Voltage [V]

Figure 9. Maximum Safe Operating Area

Figure 10. Maximum Drain Current

vs. Case Temperature

1 0 ²

D = 0 .5

※

N otes

1. Z _θ_{J C}(t)

2. D u ty F ac to r, D = t₁/t₂

3. T _{J M}T _CP _DZ_θ_{J C}(t)

0 .2

1 0 ¹

℃

/W M a x.

6 2.5

0 .1

0 .05

0 .02

1 0 ⁰

P_DM

0 .01

t₁

sin gle pu lse

t₂

1 0 ^-1

1 0 ^-5

1 0 ^-4

1 0 ^-3

1 0 ^-2

1 0 ^-1

1 0 ⁰

1 0 ¹

1 0 ²

1 0 ³

t₁, S qu a re W a ve P ulse D u ration [se c]

Figure 11. Transient Thermal Response Curve

Rev. A, May 2001

Gate Charge Test Circuit & Waveform

V_GS

Same Type

50Kꢀ

as DUT

Q_g

12V

200nF

300nF

V_DS

V_GS

Q_gs

Q_gd

DUT

3mA

Charge

Resistive Switching Test Circuit & Waveforms

R_L

V_DS

90%

V_DS

V_DD

V_GS

R_G

10%

V_GS

DUT

t_d(on)

t_r

t_d(off)

t_f

t _on

t _off

Unclamped Inductive Switching Test Circuit & Waveforms

BV_DSS

--------------------

BV_DSS- V_DD

----

E_AS

LI_AS

V_DS

I_D

BV_DSS

I_AS

R_G

V_DD

I_D(t)

V_DD

V_DS(t)

DUT

10V

t _p

Time

Rev. A, May 2001

Peak Diode Recovery dv/dt Test Circuit & Waveforms

DUT

V_DS

I _SD

Driver

R_G

Same Type

as DUT

V_DD

V_GS

• dv/dt controlled by R_G

• I_SDcontrolled by pulse period

Gate Pulse Width

--------------------------

V_GS

D =

Gate Pulse Period

10V

( Driver )

I_FM, Body Diode Forward Current

I _SD

di/dt

( DUT )

I_RM

Body Diode Reverse Current

Body Diode Recovery dv/dt

V_SD

V_DS

( DUT )

V_DD

Body Diode

Forward Voltage Drop

Rev. A, May 2001

Package Dimensions

SOT-223

3.00 ±0.10

MAX1.80

+0.04

–0.02

0.06

2.30 TYP

0.70 ±0.10

+0.10

–0.05

(0.95)

0.25

4.60 ±0.25

6.50 ±0.20

Rev. A, May 2001

TRADEMARKS

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not

intended to be an exhaustive list of all such trademarks.

SuperSOT™-3

ACEx™

Bottomless™

CoolFET™

CROSSVOLT™

DenseTrench™

DOME™

EcoSPARK™

E²CMOS™

EnSigna™

FAST^®

FASTr™

FRFET™

GlobalOptoisolator™

GTO™

OPTOPLANAR™

PACMAN™

SuperSOT™-6

SuperSOT™-8

SyncFET™

TinyLogic™

UHC™

POP™

PowerTrench^®

QFET™

HiSeC™

QS™

UltraFET^®

VCX™

ISOPLANAR™

LittleFET™

MicroFET™

MICROWIRE™

OPTOLOGIC™

QT Optoelectronics™

Quiet Series™

SLIENT SWITCHER^®

SMART START™

Stealth™

FACT™

FACT Quiet Series™

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY

PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY

LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;

NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR

CORPORATION.

As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the body,

or (b) support or sustain life, or (c) whose failure to perform

when properly used in accordance with instructions for use

provided in the labeling, can be reasonably expected to

result in significant injury to the user.

2. A critical component is any component of a life support

device or system whose failure to perform can be

reasonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification

Product Status

Definition

Advance Information

Formative or In

Design

This datasheet contains the design specifications for

product development. Specifications may change in

any manner without notice.

Preliminary

First Production

This datasheet contains preliminary data, and

supplementary data will be published at a later date.

Fairchild Semiconductor reserves the right to make

changes at any time without notice in order to improve

design.

No Identification Needed

Obsolete

Full Production

This datasheet contains final specifications. Fairchild

Semiconductor reserves the right to make changes at

any time without notice in order to improve design.

Not In Production

This datasheet contains specifications on a product

that has been discontinued by Fairchild semiconductor.

The datasheet is printed for reference information only.

Rev. H2

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