FSA321_12 [FAIRCHILD]
USB2.0 Hi-Speed (480Mbps) and Audio Switches with Negative Signal Capability and Built-in Termination on Unselected Audio Paths; USB2.0高速传输（480Mbps ）和音频开关，可处理负信号功能，并内置终端上未选音频路径
| 型号： | FSA321_12 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | USB2.0 Hi-Speed (480Mbps) and Audio Switches with Negative Signal Capability and Built-in Termination on Unselected Audio Paths |
| 文件： | 总12页 (文件大小：590K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 2012
FSA321 — USB2.0 Hi-Speed (480Mbps) and
Audio Switches with Negative Signal Capability and
Built-in Termination on Unselected Audio Paths
Features
Description
The FSA321 is a Double-Pole, Double Throw (DPDT)
multiplexer that combines a low-distortion audio and a
USB2.0 High-Speed (HS) switch path. This configuration
enables audio and USB data to share a common
connector port. The architecture is designed to allow
audio signals to swing below ground. This means a
common USB and headphone jack can be used for
personal media players and portable peripheral devices.
.
.
.
.
.
.
.
.
.
.
Audio: 1.8 Typical On Resistance
HS-USB: 8 Typical On Resistance
HS-USB: 5pF Typical On Capacitance
USB Path -3db Bandwidth: > 720MHz
Negative Swing Capable Audio Channel
Power-off Protection on Common D+/R, D-/L Ports
Automatic USB Detection (Configurable)
OVT on all I/O Ports
Since USB2.0 is an industry standard for shared data-
path in portable devices, FSA321 can be configured for
automatic VBUS detection. The FSA321 includes a
power-off feature as well as over-voltage tolerance to
Flow-Through Pin Out Eliminates PCB Vias
minimize current consumption when VSW exceeds VCC
.
Built-In Termination on Unselected Audio Paths
to Inhibit Audio Pop
Typical applications involve switching in portables and
consumer applications, such as cell phones, digital
cameras, and notebooks with hubs or controllers.
Applications
.
.
MP3, Cell Phone, PDA, Digital Camera, and
Notebook
.
LCD Monitor, TV, and Set-Top Box
Ordering Information
Package
Part Number
Top Mark
Package Description
Number
FSA321UMX
MLP010A
GL
10-Lead Quad, Ultrathin Molded Leadless Package (MLP), 1.4 x 1.8mm
VCC
USB Sel
A/LP Sel
Control
Block
Rpd
Rpd
D+
R
D+/R
RT
D-
L
D-/L
RT
Figure 1. Analog Symbol
© 2007 Fairchild Semiconductor Corporation
FSA321 • Rev 1.0.6
www.fairchildsemi.com
Pin Configuration
R
2
D-
1
3
4
10 D+
L
GND
9
8
VCC
A/LP Sel
5
USB Sel
6
7
D-/L D+/R
Figure 2. UMLP
Pin Definitions
Pin #
Name
Description
9
VCC
Power supply
Audio Select Override and Power-Save Mode. This pin can be used to override USB Sel for
applications where analog audio is transmitted on the USB D+, D- lines. This same select pin is
5
A/LP Sel used to put the FSA321 in low-power mode when USB Sel is LOW, not transmitting audio signals
or USB data. The FSA321 has a weak internal pull-down, setting its default state to LOW and
allowing this pin to float when not in use.
8
USB Sel USB Path select pin. Can be connected to USB connector VBUS pin for automatic USB detection.
10, 1
2, 3
7, 6
D+, D-
R, L
USB data bus input sources
Audio right and left input sources
D+/R, D-/L USB and audio common connector ports
Truth Table
VCC
USB Sel(1)
A/LP Sel
Audio Mode
USB Mode
Remarks
LOW
HIGH(2)
HIGH(2)
HIGH(2)
HIGH(2)
Notes:
OFF
OFF
ON
OFF
ON
Disabled Inputs High-Z
USB Communication
Audio Override on USB
Low Power Mode
Audio Out
HIGH(2)
HIGH(2)
LOW
LOW
HIGH(2)
HIGH(2)
LOW
OFF
OFF
OFF
OFF
ON
LOW
1. Forcing USB Sel HIGH when VBUS is present allows for automatic USB detection.
2. HIGH is the threshold as defined to meet USB2.0 VCC requirements and audio supply threshold in a system
(see DC Tables).
© 2007 Fairchild Semiconductor Corporation
FSA321 • Rev.1.0.6
www.fairchildsemi.com
2
Functional Description
The FSA321 is a combined USB and audio switch that
enables sharing the D+/D- lines of a USB connector with
stereo audio CODEC outputs. The USB Sel pin has an
internal pull-down resistor that results in a default audio-
mode configuration. The switch can be configured for
auto USB detection by connecting the VBUS pin to the
USB Sel pin. The audio switch path also handles
negative signals, eliminating the need for large coupling
capacitors and greatly reducing the potential for audio
pop. Termination resistors on the audio R and L ports
are enabled when the switch is in USB mode, this also
helps reduce audio pop when enabling the audio path.
The FSA321 allows for an audio override state by
forcing A/LP Sel high when USB Sel is high. This is
useful for USB car kit applications or if the device is in a
cradle charger when “Send/End” is pressed.
Application Diagram
VCC
0.1µF
USB 2.0
Hi-Speed
D+
USB Sel
D+/R
Controller
D-
FSA321
D-/L
R
L
Audio
CODEC
Figure 3. Typical Application Diagram
© 2007 Fairchild Semiconductor Corporation
FSA321 • Rev.1.0.6
www.fairchildsemi.com
3
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
Max.
Unit
VCC
Supply Voltage
-0.5
-0.5
4.6
6.0
6.0
4.6
4.6
V
V
V
USB Sel
A/LP Sel
USB Select Control Signal
Power Save Mode Control Signal
-0.5
USB Path Active
Audio Path Active
USB Path Active
Audio Path Active
-1.0
Switch I/O Voltage(3)
VCC-4.6V
VSW
V
DC Switch I/O Voltage(3)
-0.50
5.25
IIK
Input Clamp Diode Current
Switch I/O Current (Continuous)
-50
50
mA
mA
mA
mA
mA
C
USB
ISW
Audio
USB
100
100
Peak Switch Current (Pulsed at
1ms Duration, <10% Duty Cycle)
ISWPEAK
Audio
250
TSTG
TJ
Storage Temperature Range
-65
+150
+150
+260
Maximum Junction Temperature
C
TL
Lead Temperature (Soldering, 10 seconds)
I/O to GND
Human Body Model,
JEDEC: JESD22-A114
C
11
8
All Other Pins
VCC to GND
12
2
ESD
kV
Charged Discharge Model, JEDEC: JESD22-C101
Air Gap
Contact
15
8
USB Connection Pins
IEC61000-4-2 System
(D+/R, D-/L, VBUS
)
Note:
3. The input and output negative ratings may be exceeded if the input and output diode current ratings are
observed.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Min.
Max.
Units
VCC
Supply Voltage
1.8
4.3
5.5
5.5
4.3
4.3
+85
284
V
V
USB Sel USB Select Control Signal
0
A/LP Sel Power-Save Mode Control Signal
0
0
V
USB Path Active
Audio Path Active
V
VSW
Switch I/O Voltage
VCC-4.3V
-40
V
TA
Operating Temperature
ºC
ºC/W
Thermal Resistance (Free Air)
UMLP
JA
© 2007 Fairchild Semiconductor Corporation
FSA321 • Rev.1.0.6
www.fairchildsemi.com
4
DC Electrical Characteristics
All typical values are at 25ºC unless otherwise specified.
TA = - 40 to +85°C
Min. Typ.(6) Max.
Symbol
Parameter
VCC (V)
Conditions
Unit
Common Pins
VIK
Clamp Diode Voltage
1.8 to 4.3 IIK = -18mA
1.8 to 2.7
-1.2
1.0
1.2
0.3
0.5
VIH
Control Input Voltage HIGH
V
2.7 to 4.3
1.8 to 2.7
VIL
Control Input Voltage LOW
2.7 to 4.3
V
IN = 0V
-1
-1
1
USB Sel and A/LP Sel Input
Current
IIN
1.8 to 4.3
0
µA
µA
VIN = 5.5V
10
D+/R, D-/L Common Ports,
IOFF
Power Off Leakage Current
VSW = 0V to 5.5V,
25
All other Pins = 0V
A/LP Sel and USB Sel Internal
Pull-Down Resistors
RPD
RT
1.8 to 4.3
1.8 to 4.3
3
M
Audio Path Termination
Resistors
200
USB Switch Path
USB Analog Signal Range
RONUSB HS Switch On Resistance(4)
1.8 to 4.3
0
4.3
11
V
Ω
Ω
1.8 to 4.3 VD+/D- = 0V, 0.4V, ION = 8mA
1.8 to 4.3 VD+/D- = 0V, ION = 8mA
8
(5,6)
∆RONUSB HS Delta RON
0.4
Audio Switch Path
VCC-
4.3V
Audio Analog Signal Range
1.8 to 4.3
VCC
2.7
V
VL/R = -1.0V, 0V, 1.0V
2.7
RONAudio Audio Switch On Resistance
1.8
Ω
I
ON = 60mA
(5)
∆RONAudio Audio Delta RON
2.7 to 4.3 VL/R = 0.7V ION = 60mA
2.7 to 4.3 ION = 60mA
0.4
0.8
Ω
Ω
RFLAT(Audio) Audio RON Flatness(7)
1.5
Total Switch Current Consumption
A/LP Sel = LOW,
USB Sel= HIGH, IOUT = 0
ICC
USB Active Mode Supply Current 1.8 to 4.3
0.5
10
0.8
15
mA
µA
USB Low Power Mode or Audio
Mode Quiescent Supply Current
A/LP Sel = HIGH,
1.8 to 4.3
ICC_LPM
VCC = 1.8-4.3V
Increase in ICC current per
control voltage and VCC LOW
POWER Mode A/LP Sel HIGH
VUSB Sel = 2.6V
10
15
15
20
µA
VUSB Sel = 1.8V
4.3
ICCT
Increase in ICC current per
control voltage and VCC
ACTIVE Mode A/LP Sel LOW
VUSB Sel = 2.6V
0.6
0.9
1.00
mA
VUSB Sel = 1.8V
0.65
Notes:
4. On resistance is determined by the voltage drop between the A and B pins at the indicated current through the switch.
5. ∆ RON = RON max – RON min measured at identical VCC, temperature, and voltage. Worst-case signal path, audio or
USB channel, is characterized.
6. Guaranteed by characterization, not production tested.
7. Flatness is defined as the difference between the maximum and minimum values of on resistance over the
specified range of conditions.
© 2007 Fairchild Semiconductor Corporation
FSA321 • Rev.1.0.6
www.fairchildsemi.com
5
AC Electrical Characteristics
All typical value are for VCC = 3.3V at 25ºC unless otherwise specified.
TA = - 40 to +85°C
Symbol
Parameter
V
CC (V)
Conditions
Unit
Min. Typ.(8) Max.
RL = 50Ω, CL = 0pF
Figure 9
tPDUSB
USB Switch Propagation Delay(8)
3.3
3.3
0.25
-110
ns
Non-Adjacent Channel Crosstalk
(Audio Mode)
f = 20kHz, RT = 32Ω,
CL = 0pF, Figure 17
dB
XtalkA
f = 240MHz,
RT = 20Ω, CL = 0pF
Figure 17
Non-Adjacent Channel Crosstalk
(USB Mode)
3.3
-45
dB
f = 20kHz, RT = 32Ω,
CL = 0pF
Off Isolation (Audio Mode)
Off Isolation (USB Mode)
3.3
3.3
-85
-40
dB
dB
OIRR
f = 240MHz,
RT = 20Ω, CL = 0pF
RT = 50Ω, CL = 0pF,
Signal 0dBm,
Figure 15
BW
-3db Bandwidth (USB Mode)
3.3
720
MHz
f = 20Hz to 20kHz,
RL = 32Ω, VIN = 2VPP
Figure 14
THD
Total Harmonic Distortion (Audio Mode)
Signal-to-Noise Ratio (Audio Mode)
3.3
3.3
0.11
-90
%
f = 20Hz to 20kHz
RL = 32Ω, VIN = 2VPP
SNR
dB
Note:
8. Guaranteed by characterization, not production tested.
© 2007 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSA321 • Rev.1.0.6
6
USB High-Speed-Related AC Electrical Characteristics
TA = - 40°C to +85°C
Min. Typ. Max.
Symbol
tSK(o)
Parameter
VCC (V)
Conditions
Unit
tR = tF = 750ps
(10-90%) at 240MHz CL =
0pF, RL = 50Ω
Channel-to-Channel Skew(9)
(USB Mode)
3.3
35
ps
Figure 11
Skew of Opposite Transitions
of the Same Output(9)
tR = tF = 750ps (10-90%) at
240MHz CL = 0pF, RL = 50Ω
Figure 10
tSK(P)
3.3
3.3
35
ps
ps
(USB Mode)
Total Jitter(9)
(USB Mode)
RL = 50ꢀ, CL = 50pF, tR = tF =
500ps (10-90%) at 480Mbps
(PRBS = 215 – 1)
tJ
130
Note:
9. Guaranteed by characterization, not production tested.
Capacitance
TA = - 40°C to +85°C
Symbol
Parameter
VCC (V)
Conditions
Unit
Min. Typ. Max.
CIN
Control Pin Input Capacitance
1.8 to 4.3 VBias = 0.2V
2.0
pF
pF
VBias = 0.2V, f = 240MHz,
1.8 to 4.3
1.8 to 5.5
5.4
6.0
Figure 13
D+/R, D-/L On Capacitance
(USB Mode)
CON(D+/R, D-/L)
VBias = 0.2V, f = 1MHz,
Figure 13
pF
COFF(D+, D-)
COFF(R/L)
USB Path Off Capacitance
Audio Path Off Capacitance
1.8 to 4.3 f = 1MHz, Figure 12
1.8 to 4.3 f = 1MHz, Figure 12
1.6
3.5
pF
pF
© 2007 Fairchild Semiconductor Corporation
FSA321 • Rev.1.0.6
www.fairchildsemi.com
7
Test Diagrams
VON
I(OFF)
A
Dnor R/L
VSW
VSW
D+/R or D-/L
D+/R or D-/L
D+, D-
or R/L
GND
ION
GND
GND
VCNTRL= fn (VCC
)
R
= VON / ION
V )
CNTRL = fn (VCC
Figure 4. On Resistance
Figure 5. Off Leakage
D+, D- or R,L
RL
D+/R or D-/L
VOUT
CL
D+, D- or R/L
IA(ON)
A
V
sw
RS
GND
GND
D+/R or
D-/L
V
VCNTRL = fn (VCC
)
sw
GND
G
ND
RL, RS, and CL, are functions of the application
environment (see tables for specific values).
CL includes test fixture and stray capacitance.
(V
)
VCNTRL = fn
CC
Figure 6. On Leakage
Figure 7. AC Test Circuit Load
tRISE= 750ps
tFALL= 750ps
t
RISE= 1µs
t
FALL= 1µs
Vbus
0.4V
Input – VD+/D
90%
50%
90%
50%
90%
Vth(max)
Vth(min)
Input -VCNTRL
-
10%
10%
90%
10%
10%
50%
GND
GND
VOH
Output -VOUT
VOL
VOH
90%
Output- VOUT
VOL
50%
tpLH
tOFF
tON
tpHL
VCNTRL = fn (VCC
)
Vth =Vbusth or Vaudioth
Figure 8. Turn-On / Turn-Off Waveforms (USB/Audio) Figure 9. USB Switch Propagation Delay Waveforms
© 2007 Fairchild Semiconductor Corporation
FSA321 • Rev.1.0.6
www.fairchildsemi.com
8
Test Diagrams (Continued)
t
tRISE = 750ps
FALL = 750ps
0.4V
tRISE = 750ps
tFALL= 750ps
90%
50%
90%
50%
Input – VD+/D
10%
10%
50%
0.4V
GND
90%
50%
90%
50%
Input – VD+/D -
10%
OH
10%
50%
Output1 - V
OUT
GND
50%
tpLH1
VOL
V
OH
tpHL1
Output- VOUT
50%
tpLH
t
V
V
OH
OL
sk(o)
tpHL
Output2 - VOUT
50%
50%
tpLH2 tpHL2
V
OL
Figure 10. Pulse Skew: tSK(P) = | tPHL – tPLH
|
Figure 11. Output Skew: tSK(O) = | tPLH1 – tPLH2
or | tPHL1 – tPHL2
|
|
Dn or R/L or
Dn or R/L or D+/R or D-/L
Capacitance
Meter
D+/R or D -/L
Capacitance
Meter
f = 240MHz
VCNTRL = fn (VCC
)
VCNTRL = fn (VCC
)
Dn or R/L or
D+/ R or D-/L
Dn or R/L or
D+/ R or D-/L
f = 1MHz
Figure 12. Channel Off Capacitance
Figure 13. Channel On Capacitance
Audio Analyzer
RS
V
IN
VS
GND
GND
VCNTRL
GND
VOUT
GND
RT
VCNTROL = fn (VCC
)
GND
RS and RT
are functions of the application
environment (see tables for specific values).
Figure 14. Total Harmonic Distortion
© 2007 Fairchild Semiconductor Corporation
FSA321 • Rev.1.0.6
www.fairchildsemi.com
9
Test Diagrams (Continued)
Network Analyzer
RS
V
IN
VS
GND
GND
VCNTRL
GND
VOUT
GND
RT
VCNTRL = fn (VCC
)
GND
RS and R T are functions of the application
environment (see tables for specific values).
Figure 15. USB Bandwidth
Network Analyzer
RS
VIN
RT
VS
GND
GND
VCNTRL
GND
GND
VOUT
GND
VCNTRL
= fn (
VCC
)
RT
GND
Off Isolation = 20 Log (VOUT / VIN
RS and RT are functions of the application
environment (see tables for specific values).
)
Figure 16. Channel Off Isolation
Network Analyzer
RS
NC
V
IN
VS
GND
GND
VCNTRL
GND
RT
GND
= fn (VCC
VCNTRL
)
VOUT
GND
RT
RS and RT are functions of the application
environment (see tables for specific values
GND
CROSSTALK = 20 Log (VOUT / V )
IN
Figure 17. Non-Adjacent Channel-to-Channel Crosstalk
© 2007 Fairchild Semiconductor Corporation
FSA321 • Rev.1.0.6
www.fairchildsemi.com
10
Physical Dimensions
(9X)
0.563
1.70
0.15 C
1.40
A
B
0.663
2X
1
2.10
1.80
PIN#1 IDENT
0.40
0.15 C
0.225
(10X)
TOP VIEW
2X
RECOMMENDED
LAND PATTERN
0.55 MAX.
0.152
0.10 C
9X
0.45
1.45
0.08 C
0.05
0.55
0.40
SEATING
PLANE
C
SIDE VIEW
1.85
0.35
(9X)
0.45
0.225
(10X)
3
OPTIONAL MINIMIAL
TOE LAND PATTERN
0.40
6
DETAIL A
1
NOTES:
PIN#1 IDENT
A. PACKAGE DOES NOT FULLY CONFORM TO
0.15
0.25
10
JEDEC STANDARD.
(10X)
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
0.10 C A B
0.05 C
BOTTOM VIEW
D. LAND PATTERN RECOMMENDATION IS
BASED ON FSC DESIGN ONLY.
E. DRAWING FILENAME: MKT-UMLP10Arev3.
0.55
0.45
0.10
0.10
0.10
DETAIL A
SCALE : 2X
PACKAGE
EDGE
LEAD
LEAD
OPTION 2
SCALE : 2X
OPTION 1
SCALE : 2X
Figure 18. 10-Lead, Quad Ultrathin Molded Leadless Package (UMLP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2007 Fairchild Semiconductor Corporation
FSA321 • Rev.1.0.6
www.fairchildsemi.com
11
© 2007 Fairchild Semiconductor Corporation
FSA321 • Rev.1.0.6
www.fairchildsemi.com
12
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