FSBH0F370-F116 [FAIRCHILD]
Switching Regulator/Controller, Current-mode, 106kHz Switching Freq-Max, BICMOS, PDIP8;
| 型号： | FSBH0F370-F116 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Switching Regulator/Controller, Current-mode, 106kHz Switching Freq-Max, BICMOS, PDIP8 信息通信管理 光电二极管 |
| 文件： | 总16页 (文件大小：938K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 2011
FSBH0F70A _F116, FSBH0170_F116,
FSBH0270_F116, FSBH0370_F116
Green Mode Fairchild Power Switch (FPS™)
Features
Description
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Brownout Protection with Hysteresis
Built-In 5ms Soft-Start Function
The highly integrated FSBH-series consists of an
integrated current-mode Pulse Width Modulator (PWM)
and an avalanche-rugged 700V SenseFET. It is
specifically designed for high-performance offline
Switched-Mode Power Supplies (SMPS) with minimal
external components.
Internal Avalanche-Rugged 700V SenseFET
Low Acoustic Noise During Light-Load Operation
High-Voltage Startup
The integrated PWM controller features include a
proprietary green-mode function that provides off-time
modulation to linearly decrease the switching frequency
at light-load conditions to minimize standby power
consumption. To avoid acoustic-noise problems, the
minimum PWM frequency is set above 18kHz. This
green-mode function enables the power supply to meet
international power conservation requirements. The
PWM controller is manufactured using the BiCMOS
process to further reduce power consumption. The
FSBH-series turns off some internal circuits to improve
power saving when VFB is lower than 1.6V, which allows
an operating current of only 2.5mA.
Linearly Decreasing PWM Frequency to 18KHz
Peak-Current-Mode Control
Cycle-by-Cycle Current Limiting
Leading-Edge Blanking (LEB)
Synchronized Slope Compensation
Internal Open-Loop Protection
VDD Under-Voltage Lockout (UVLO)
VDD Over-Voltage Protection (OVP)
Internal Auto-Restart Circuit (OVP, OTP)
Constant Power Limit (Full AC Input Range)
Internal OTP Sensor with Hysteresis
The FSBH-series has built-in synchronized slope
compensation to achieve stable peak-current-mode
control. The proprietary external line compensation
ensures constant output power limit over a wide AC
VIN Pin for Pull-HIGH Latch Function and
Pull-LOW Auto-Recovery Protection
input voltage range, from 90VAC to 264VAC
.
The FSBH-series provides many protection functions. In
addition to cycle-by-cycle current limiting, the internal
open-loop protection circuit ensures safety when an
open-loop or output short occurs. PWM output is
disabled until VDD drops below the VTH-OLP, then the
controller starts up again. As long as VDD exceeds 28V,
the internal OVP circuit is triggered.
Applications
General-purpose switched-mode power supplies and
flyback power converters, including:
.
.
Auxiliary Power Supply for PC and Server
SMPS for VCR, SVR, STB, DVD & DVCD Player,
Printer, Facsimile, and Scanner
Compared with a discrete MOSFET and controller or
RCC switching converter solution, the FSBH-series
reduces component count, design size, and weight;
while increasing efficiency, productivity, and system
reliability. These devices provide a basic platform that is
well suited for the design of cost-effective flyback
converters, such as in PC auxiliary power supplies.
.
Adapter for Camcorder
© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSBH0F70A_F116, FSBH0170/0270/0370_F116 • Rev. 1.0.1
1
Ordering Information
VIN Pin
(PIN #4)
Operating
Temperature Range
Packing
Method
Part Number
SenseFET
Package
FSBH0F70ANY_F116
FSBH0170NY_F116
FSBH0270NY_F116
FSBH0370NY_F116
0.5A 700V
1.0A 700V
2.0A 700V
3.0A 700V
Not Available
8-Pin, Dual In-Line
Package (DIP)
-40°C to +105°C
Tube
Enabled
Typical Application Diagram
HV
Drain
VIN
FB
VDD
GND
Figure 1.
Typical Flyback Application
Output Power Table(1)
230VAC ± 15%(2)
Adapter(3) Open Frame(4)
85-265VAC
Product
Adapter(3)
6W
Open Frame(4)
FSBH0F70A_F116
FSBH0170_F116
FSBH0270_F116
FSBH0370_F116
7W
10W
10W
15W
20W
25W
8W
9W
13W
16W
19W
14W
11W
17.5W
13W
Notes:
1. The maximum output power can be limited by junction temperature.
2. 230 VAC or 100/115 VAC with doublers.
3. Typical continuous power in a non-ventilated enclosed adapter with sufficient drain pattern as a heat sink at 50C
ambient.
4. Maximum practical continuous power in an open-frame design with sufficient drain pattern as a heat sink at 50C
ambient.
© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSBH0F70A_F116, FSBH0170/0270/0370_F116 • Rev. 1.0.1
2
Block Diagram
Figure 2.
FSBH0170/0270/0370_F116 Internal Block Diagram
Figure 3.
FSBH0F70A_F116 Internal Block Diagram
© 2010 Fairchild Semiconductor Corporation
FSBH0F70A_F116, FSBH0170/0270/0370_F116 • Rev. 1.0.1
www.fairchildsemi.com
3
Pin Configuration
F – Fairchild Logo
Z – Plant Code
X – 1-Digit Year Code
Y – 1-Digit Week Code
TT – 2-Digit Die-Run Code
T – Package Type (N:DIP)
P – Y: Green Package
M – Manufacture Flow Code
Figure 4.
Pin Configuration and Top Mark Information
Pin Definitions
Pin # Name Description
1
GND
Ground. SenseFET source terminal on primary side and internal controller ground.
Power Supply. The internal protection circuit disables PWM output as long as VDD exceeds the
OVP trigger point.
2
VDD
Feedback. The signal from the external compensation circuit is fed into this pin. The PWM duty
cycle is determined in response to the signal on this pin and the internal current-sense signal.
3
4
FB
Line-Voltage Detection. The line-voltage detection is used for brownout protection with
hysteresis and constant output power limit over universal AC input range. This pin has additional
protections that are pull-HIGH latch and pull-LOW auto recovery, depending on the application.
VIN
NC
HV
No Connection. FSBH0F70A_F116
5
6
7
8
Startup. For startup, this pin is pulled HIGH to the line input or bulk capacitor via resistors.
Drain SenseFET Drain. High-voltage power SenseFET drain connection.
Drain SenseFET Drain. High-voltage power SenseFET drain connection.
Drain SenseFET Drain. High-voltage power SenseFET drain connection.
© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSBH0F70A_F116, FSBH0170/0270/0370_F116 • Rev. 1.0.1
4
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
VDRAIN Drain Pin Voltage(5,6)
Parameter
Min.
Max.
700
1.5
4.0
8.0
12.0
10
Unit
FSBH0x70/A_F116
FSBH0F70A_F116
FSBH0170_F116
FSBH0270_F116
FSBH0370_F116
FSBH0F70A_F116
FSBH0170_F116
FSBH0270_F116
FSBH0370_F116
V
IDM
Drain Current Pulsed(7)
A
50
EAS
Single Pulsed Avalanche Energy(8)
mJ
140
230
30
VDD
VFB
VIN
VHV
PD
DC Supply Voltage
V
V
FB Pin Input Voltage
-0.3
-0.3
7.0
7.0
700
1.5
80
VIN Pin Input Voltage
V
HV Pin Input Voltage
V
Power Dissipation (TA＜50°C)
Junction-to-Air Thermal Resistance
Junction-to-Top Thermal Resistance(9)
Operating Junction Temperature
Storage Temperature Range
W
ΘJA
ψJT
TJ
C/W
C/W
C
20
Internally limited(10)
TSTG
TL
-55
+150
+260
C
Lead Temperature (Wave Soldering or IR, 10 Seconds)
FSBH0F70A_F116
C
5.0
5.0
5.0
5.0
2.0
2.0
2.0
1.5
FSBH0170_F116
FSBH0270_F116
FSBH0370_F116
FSBH0F70A_F116
FSBH0170_F116
FSBH0270_F116
FSBH0370_F116
Human Body Model
(All Pins Except HV pin): JESD22-A114
ESD
kV
Charged Device Model
(All Pins Except HV pin): JESD22-C101
Notes:
5. All voltage values, except differential voltages, are given with respect to the network ground terminal.
6. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
7. Non-repetitive rating: pulse width is limited by maximum junction temperature.
8. L = 51mH, starting TJ = 25C.
9. Measured on the package top surface.
10. Internally Limited of TJ refers to TOTP
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Min.
Max.
Unit
TA
Operating Ambient Temperature
-40
+105
°C
© 2010 Fairchild Semiconductor Corporation
FSBH0F70A_F116, FSBH0170/0270/0370_F116 • Rev. 1.0.1
www.fairchildsemi.com
5
Electrical Characteristics
VDD=15V and TA=25C unless otherwise specified.
Symbol
Parameter
Condition
Min. Typ. Max. Unit
SenseFET Section
Drain-Source
Breakdown Voltage
BVDSS
IDSS
VDS=700V, VGS=0V
700
V
VDS=700V, VGS=0V
50
200
Zero-Gate-Voltage
Drain Current
μA
VDS=560V, VGS=0V, TC=125C
FSBH0F70A_F116
14.00 19.00
FSBH0170_F116
FSBH0270_F116
FSBH0370_F116
FSBH0F70A_F116
FSBH0170_F116
FSBH0270_F116
FSBH0370_F116
FSBH0F70A_F116
FSBH0170_F116
FSBH0270_F116
FSBH0370_F116
FSBH0F70A_F116
FSBH0170_F116
FSBH0270_F116
FSBH0370_F116
FSBH0F70A_F116
FSBH0170_F116
FSBH0270_F116
FSBH0370_F116
FSBH0F70A_F116
FSBH0170_F116
FSBH0270_F116
FSBH0370_F116
FSBH0F70A_F116
FSBH0170_F116
FSBH0270_F116
FSBH0370_F116
FSBH0F70A_F116
FSBH0170_F116
FSBH0270_F116
FSBH0370_F116
8.80
6.00
4.00
162
250
550
315
18
11.00
7.20
4.75
211
325
715
410
24
Drain-Source On-
RDS(ON)
CISS
COSS
CRSS
tD(ON)
tR
VGS=10V, ID=0.5A
Ω
State Resistance(12)
VGS=0V, VDS=25V,
f=1MHz
Input Capacitance
Output Capacitance
pF
pF
pF
ns
ns
ns
ns
25
33
VGS=0V, VDS=25V,
f=1MHz
38
50
47
61
3.8
10.0
17.0
9.0
9.5
12.0
20.0
11.2
19
5.7
15.0
26.0
24.0
29.0
34.0
50.0
33.0
48
Reverse Transfer
Capacitance
VGS=0V, VDS=25V,
f=1MHz
Turn-On Delay
Rise Time
VDS=350V, ID=1.0A
VDS=350V, ID=1.0A
VDS=350V, ID=1.0A
VDS=350V, ID=1.0A
4
18
15
40
34
78
33.0
30.0
55.0
28.2
42
76.0
70.0
120.0
67.0
94
tD(OFF)
Turn-Off Delay
Fall Time
10
30
tF
25
60
32
74
Continued on the following page…
© 2010 Fairchild Semiconductor Corporation
FSBH0F70A_F116, FSBH0170/0270/0370_F116 • Rev. 1.0.1
www.fairchildsemi.com
6
Electrical Characteristics (Continued)
VDD=15V and TA=25C unless otherwise specified.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
Control Section
VDD Section
VDD-ON
Start Threshold Voltage
11
7
12
8
13
9
V
V
VDD-OFF
Minimum Operating Voltage
FSBH0170_F116
FSBH0270_F116
FSBH0370_F116
FSBH0F70A_F116
VDD-ON – 0.16V
30
IDD-ST
Startup Current
µA
VDD-ON – 0.16V
VDD=15V, VFB=3V
VDD=12V, VFB=1.6V
VTH-OLP+0.1V
240
3.0
1.5
30
5
320
3.5
2.5
70
400
4.0
3.5
90
IDD-OP
IDD-ZDC
IDD-OLP
VTH-OLP
VDD-OVP
Operating Supply Current
Operating Current for VFB<VFB-ZDC
Internal Sink Current
mA
mA
µA
V
IDD-OLP Off Voltage
6
7
VDD Over-Voltage Protection
27
75
28
29
V
tD-VDD-OVP VDD Over-Voltage Protection Debounce Time
130
200
µs
HV Section
HV 120VDC
,
IHV
Maximum Current Drawn from HV Pin
Leakage Current after Startup
1.5
3.5
1
5.0
20
mA
µA
VDD=0V with 10µF
HV=700V,
DD=VDD-OFF+1V
IHV-LC
V
Oscillator Section
fOSC
fOSC-G
DMAX
fDV
Frequency in Nominal Mode
Center Frequency
94
14
100
18
106
22
kHz
kHz
%
Green-Mode Frequency
Maximum Duty Cycle
85
Frequency Variation vs. VDD Deviation
VDD=11V to 22V
5
5
%
Frequency Variation vs. Temperature
Deviation(11)
fDT
%
TA=-25 to 85C
VIN Section
VIN-ON
VIN-OFF
tIN-OFF
VIN-H
PWM Turn-On Threshold Voltage
PWM Turn-Off Threshold Voltage
PWM Turn-Off Debounce Time
Pull-HIGH Latch Trigger Level
1.08
0.50
1.13
0.55
500
4.7
1.18
0.60
V
V
ms
V
4.4
0.2
5.0
0.4
tIN-H
Pull-HIGH Latch Debounce Time
Pull-LOW Auto-Recovery Trigger Level
100
0.3
µs
V
VIN-L
Feedback Input Section
AV
ZFB
FB Voltage to Current-Sense Attenuation
1/4.5
4
1/4.0
1/3.5
7
V/V
kΩ
V
Input Impedance
VFB-OPEN
Output High Voltage
FB Pin Open
5.5
Continued on the following page…
© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSBH0F70A_F116, FSBH0170/0270/0370_F116 • Rev. 1.0.1
7
Electrical Characteristics (Continued)
VDD=15V and TA=25C unless otherwise specified.
Symbol
VFB-N
Parameter
Green-Mode Entry FB Voltage
Green-Mode Ending FB Voltage
Zero Duty Cycle FB Voltage
Condition
Min.
2.3
Typ.
2.5
2.0
1.6
5.4
4.6
56
Max.
2.7
Unit
V
VFB-G
1.9
2.1
V
VFB-ZDC
V
FSBH0F70A_F116
FSBH0x70_F116
5.2
4.4
50
5.6
4.8
59
FB Open-Loop
Trigger Level
VFB-OLP
tD-OLP
V
FB Open-Loop Protection Delay
ms
Current-Sense Section(15)
FSBH0F70A_F116
FSBH0170_F116
FSBH0270_F116
FSBH0370_F116
V
IN Open
0.63
0.70
0.90
1.10
4.5
0.73
0.80
1.00
1.20
5.0
0.83
0.90
1.10
1.30
5.5
VIN=1.2V
VIN=1.2V
VIN=1.2V
Peak Current
Limit
ILIM
A
tSS
Constant Power Limit (FSBH0170, FSBH0270, FSBH0370)
Period During Soft-Start Time(11)
ms
VLMT1
VLMT2
Threshold Voltage 1 for Current Limit
Threshold Voltage 2 for Current Limit
VIN=1.2V
VIN=3.6V
0.73
0.56
0.80
0.63
0.87
0.70
V
V
Constant Power Limit (FSBH0F70A)
VLMT
Threshold Voltage for Current Limit
0.97
1.00
1.03
V
Over-Temperature Protection Section (OTP)
TOTP
Protection Junction Temperature(11,13)
Restart Junction Temperature(11,14)
+135
+142
+150
°C
°C
TRESTART
TOTP-25
Notes:
11. These parameters, although guaranteed, are not 100% tested in production.
12. Pulse test: pulse width ≤ 300µs, duty ≤ 2%.
13. When activated, the output is disabled and the latch is turned off.
14. The threshold temperature for enabling the output again and resetting the latch after over-temperature protection
has been activated.
15. These parameters, although guaranteed, are tested in wafer process.
Figure 5.
VFB vs. PWM Frequency
© 2010 Fairchild Semiconductor Corporation
FSBH0F70A_F116, FSBH0170/0270/0370_F116 • Rev. 1.0.1
www.fairchildsemi.com
8
Typical Characteristics
14
12
10
8
3.02
3.00
2.98
2.96
2.94
2.92
2.90
2.88
2.86
6
4
2
0
-40
-25 -10
5
20
35
50
65
80
95
110 125
110 125
110 125
-40 -25 -10
5
20
35
50
65
80
95 110 125
Temperature(°C)
Temperature(°C)
Figure 6.
IDD-ST vs. Temperature
Figure 7.
IDD-OP vs. Temperature
12.4
12.2
12.0
11.8
11.6
11.4
11.2
8.3
8.2
8.1
8.0
7.9
7.8
7.7
-40 -25 -10
5
20
35
50
65
80
95
-40
-25
-10
5
20
35
50
65
80
95
110 125
Temperature(°C)
Temperature(°C)
Figure 8.
VDD-ON vs. Temperature
Figure 9.
VDD-OFF vs. Temperature
6.6
6.4
6.2
6.0
5.8
5.6
5.4
5.2
5.0
28.42
28.41
28.40
28.39
28.38
28.37
28.36
28.35
-40
-25 -10
5
20
35
50
65
80
95
-40 -25 -10
5
20
35
50
65
80
95
110 125
Temperature(°C)
Temperature(°C)
Figure 10. VTH-OLP vs. Temperature
Figure 11. VDD-OVP vs. Temperature
4.0
3.5
3.0
2.5
2.0
1.5
1.0
7
6
5
4
3
2
1
0
-40 -25
-10
5
20
35
50
65
80
95
110 125
-40
-25
-10
5
20
35
50
65
80
95
110 125
Temperature(°C)
Temperature(°C)
Figure 12. IHV vs. Temperature
Figure 13. IHV-LC vs. Temperature
© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSBH0F70A_F116, FSBH0170/0270/0370_F116 • Rev. 1.0.1
9
Typical Characteristics
101.5
101.0
100.5
100.0
99.5
19.2
19.1
19.0
18.9
18.8
18.7
18.6
99.0
98.5
98.0
97.5
-40
-25 -10
5
20
35
50
65
80
95
110 125
-40 -25 -10
5
20
35
50
65
80
95
110 125
Temperature(°C)
Temperature(°C)
Figure 14. fOSC vs. Temperature
Figure 15. fOSC-G vs. Temperature
0.64
0.63
0.62
0.61
0.60
0.59
0.58
1.17
1.16
1.15
1.14
1.13
1.12
1.11
-40
-25 -10
5
20
35
50
65
80
95
110 125
-40
-25 -10
5
20
35
50
65
80
95
110 125
Temperature(°C)
Temperature(°C)
Figure 16. VIN-OFF vs. Temperature
Figure 17. VIN-ON vs. Temperature
4.63
4.62
4.61
4.60
4.59
4.58
4.57
0.34
0.33
0.32
0.31
0.30
0.29
0.28
-40
-25 -10
5
20
35
50
65
80
95
110 125
-40
-25 -10
5
20
35
50
65
80
95
110 125
Temperature(°C)
Temperature(°C)
Figure 18. VIN-H vs. Temperature
Figure 19. VIN-L vs. Temperature
4.75
4.70
4.65
4.60
4.55
4.50
4.45
4.40
4.35
2.60
2.55
2.50
2.45
2.40
2.35
2.30
-40
-25 -10
5
20
35
50
65
80
95
110 125
-40 -25
-10
5
20
35
50
65
80
95
110 125
Temperature(°C)
Temperature(°C)
Figure 20. VFB-OLP vs. Temperature
Figure 21. VFB-N vs. Temperature
© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSBH0F70A_F116, FSBH0170/0270/0370_F116 • Rev. 1.0.1
10
Typical Characteristics
2.20
2.15
2.10
2.05
2.00
1.95
1.90
1.85
1.80
1.800
1.700
1.600
1.500
1.400
1.300
1.200
-40
-25 -10
5
20
35
50
65
80
95
110 125
-40 -25 -10
5
20
35
50
65
80
95
110 125
Temperature(°C)
Temperature(°C)
Figure 22. VFB-G vs. Temperature
Figure 23. VFB-ZDC vs. Temperature
2.56
2.54
2.52
2.50
2.48
2.46
2.44
2.42
55.0
54.5
54.0
53.5
53.0
52.5
52.0
51.5
-40
-25 -10
5
20
35
50
65
80
95
110 125
-40
-25 -10
5
20
35
50
65
80
95
110 125
Temperature(°C)
Temperature(°C)
Figure 24.
I
DD-ZDC vs. Temperature
Figure 25. tD-OLP vs. Temperature
© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSBH0F70A_F116, FSBH0170/0270/0370_F116 • Rev. 1.0.1
11
Functional Description
Startup Operation
Brown-In/Out Function
The HV pin is connected to bulk voltage through an
external resistor, RHV, as shown in Figure 26. When AC
voltage is applied to the power system, an internal HV
startup circuit provides a high current (around 3.5mA) to
charge an external VDD capacitor until VDD voltage
exceeds the turn-on threshold voltage (VDD-ON). For
lower power consumption, the HV startup circuit shuts
down during normal operation. The external VDD
capacitor and auxiliary winding maintain the VDD voltage
and provide operating current to controller.
FSBH0x70 has a built-in internal brown-in/out protection
comparator monitoring voltage of VIN pin. Figure 28
shows a resistive divider with low-pass filtering for line-
voltage detection on the VIN pin.
Figure 28. Brown-In/Out Function on VIN Pin
Once the VIN pin voltage is lower than 0.6V and lasts
for 500ms, the PWM gate is disabled to protect the
system from over current. FSBH0x70 starts up as VIN
increases above 1.1V. Because the divider resistors of
the VIN pin are connected behind the bridge, the ratio
calculations for brownout in PFC and non-PFC system
are different, as shown in Figure 29. The formulas are
provided in the following equations:
Figure 26. Startup Circuit
Slope Compensation
The FSBH-series is designed for flyback power
converters. The peak-current-mode control is used to
optimize system performance. Slope compensation is
added to reduce current loop gain and improve power
Brownout with PFC:
RC
2
system stability. The FSBH-series has
synchronized, positive slope for each switching cycle.
a built-in,
2VAC _OUT
0.6
(1)
(2)
(3)
RA RB RC
Soft-Start
Brownout with non-PFC:
The FSBH-series has an internal soft-start circuit that
reduces the SenseFET switching current during power
system startup. The characteristic curve of soft-start
time versus VLMT level is shown in Figure 27. The VLMT
level rises in six steps. By doing so, the power system
can smoothly build up the rated output voltage and
effectively reduce voltage stress on the PWM switch
and output diode.
RC
2VAC _OUT 0.6
RA RB RC
Brown-in level is determined by:
RA RB RC
1.1
2
VAC _ IN
RC
Figure 27. Soft-Start Function
Figure 29.
VIN Level According to PFC Operation
© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSBH0F70A_F116, FSBH0170/0270/0370_F116 • Rev. 1.0.1
12
H/L Line Over-Power Compensation
Brown-In Function of FSBH0F70A
To limit the output power of the converter constantly,
high/low line over-power compensation is included.
Sensing the converter input voltage through the VIN pin,
the high/low line compensation function generates a
relative peak-current-limit threshold voltage for constant
power control, as shown in Figure 32.
The VIN pin functions are disabled in FSBH0F70A, but
FSBH0F70A has brown-in protection in the VDD pin.
There is a discharge current internal from VDD to ground
during startup. The HV source current must be larger
than IDD-ST to charge the capacitor of VDD. Therefore, the
brown-in level can be determined by RHV according to
the equation:
2VAC 12
IDDST
RHV
(4)
Green-Mode Operation
The FSBH-series uses feedback voltage (VFB) as an
indicator of the output load and modulates the PWM
frequency, as shown in Figure 30, such that the
switching frequency decreases as load decreases. In
heavy-load conditions, the switching frequency is
100kHz. Once VFB decreases below VFB-N (2.5V), the
PWM frequency starts to linearly decrease from 100kHz
to 18kHz to reduce switching losses. As VFB decreases
below VFB-G (2.0V), the switching frequency is fixed at
18kHz and the FSBH-series enters “deep” green mode to
reduce the standby power consumption.
Figure 32. Constant Power Control
Protections
The FSBH-series provides full protection functions to
prevent the power supply and the load from being
damaged. The protection features include:
Latch/Auto-Recovery Function
Besides the brownout protection and high/low line over-
power compensation, the FSBH0X70_F116 has
additional protections via the VIN pin, such as pull-HIGH
latch and pull-LOW auto-recovery that depends on the
application. As shown in Figure 33, when VIN level is
higher than 4.7V, FSBH-series is latched until the VDD is
discharged. FSBH-series is auto-recovery when the VIN
level is lower than 0.3V.
Figure 30. PWM Frequency
As VFB decreases below VFB-ZDC (1.6V), the FSBH-
series enters burst-mode operation. When VFB drops
below VFB-ZDC, FSBH-series stops switching and the
output voltage starts to drop, which causes the feedback
voltage to rise. Once VFB rises above VFB-ZDC, switching
resumes. Burst mode alternately enables and disables
switching, thereby reducing switching loss to improve
power saving, as shown in Figure 31.
Figure 33. VIN Pin Function
Open-Loop / Overload Protection (OLP)
When the upper branch of the voltage divider for the
shunt regulator (KA431 shown) is broken, as shown in
Figure 34, or over current or output short occurs, there
is no current flowing through the opto-coupler transistor,
which pulls the feedback voltage up to 6V.
When feedback voltage is above 4.6V for longer than
56ms, OLP is triggered. This protection is also triggered
when the SMPS output drops below the nominal value
longer than 56ms due to the overload condition.
Figure 31. Burst-Mode Operation
© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSBH0F70A_F116, FSBH0170/0270/0370_F116 • Rev. 1.0.1
13
VDD Over-Voltage Protection (OVP)
VDD over-voltage protection prevents IC damage caused
by over voltage on the VDD pin. The OVP is triggered
when VDD voltage reaches 28V. Debounce time (typically
130µs) prevents false trigger by switching noise.
Over-Temperature Protection (OTP)
The SenseFET and the control IC are integrated,
making it easier to detect the temperature of the
SenseFET. As the temperature exceeds approximately
142°C, thermal shutdown is activated.
Figure 34. OLP Operation
© 2010 Fairchild Semiconductor Corporation
FSBH0F70A_F116, FSBH0170/0270/0370_F116 • Rev. 1.0.1
www.fairchildsemi.com
14
Physical Dimensions
Figure 35.
8-Pin Dual In-Line Package (DIP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSBH0F70A_F116, FSBH0170/0270/0370_F116 • Rev. 1.0.1
15
© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSBH0F70A_F116, FSBH0170/0270/0370_F116 • Rev. 1.0.1
16
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