FSGL134R4 [FAIRCHILD]

Power Field-Effect Transistor, 10A I(D), 150V, 0.125ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-205AF, HERMETIC SEALED, METAL CAN-3;
FSGL134R4
型号: FSGL134R4
厂家: FAIRCHILD SEMICONDUCTOR    FAIRCHILD SEMICONDUCTOR
描述:

Power Field-Effect Transistor, 10A I(D), 150V, 0.125ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-205AF, HERMETIC SEALED, METAL CAN-3

开关 脉冲 晶体管
文件: 总9页 (文件大小:102K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
FSGL134R  
Data Sheet  
July 2001  
File Number 5011  
Radiation Hardened, SEGR Resistant  
N-Channel Power MOSFETs  
Features  
• 10A, 150V, r  
• UIS Rated  
Total Dose  
= 0.125  
DS(ON)  
itle  
bjec  
tho  
Fairchild Star*Power™ Rad Hard  
MOSFETs have been specifically  
TM  
developed for high performance  
applications in a commercial or  
- Meets Pre-RAD Specifications to 100K RAD (Si)  
military space environment.  
Star*Power MOSFETs offer the system designer both  
• Single Event  
- Safe Operating Area Curve for Single Event Effects  
extremely low r  
and Gate Charge allowing the  
DS(ON)  
2
- SEE Immunity for LET of 82MeV/mg/cm with  
yw  
s ()  
eato  
development of low loss Power Subsystems. Star*Power  
Gold FETs combine this electrical capability with total dose  
radiation hardness up to 100K RADs while maintaining the  
guaranteed performance for Single Event Effects (SEE)  
which the Fairchild FS families have always featured.  
V
V
up to 80% of Rated Breakdown and  
of 5V Off-Bias  
DS  
GS  
• Dose Rate  
- Typically Survives 3E9 RAD (Si)/s at 80% BV  
DSS  
OCI  
O
mar  
- Typically Survives 2E12 if Current Limited to I  
AS  
The Fairchild family of Star*Power FETs includes a series of  
devices in various voltage, current and package styles. The  
portfolio consists of Star*Power and Star*Power Gold  
products. Star*Power FETs are optimized for total dose and  
• Photo Current  
- 2nA Per-RAD (Si)/s Typically  
• Neutron  
r
while exhibiting SEE capability at full rated voltage  
DS(ON)  
- Maintain Pre-RAD Specifications  
for 1E13 Neutrons/cm  
up to an LET of 37. Star*Power Gold FETs have been  
optimized for SEE and Gate Charge combining SEE  
performance to 80% of the rated voltage for an LET of 82  
with extremely low gate charge characteristics.  
2
ge  
de  
eO  
nes  
OC  
EW  
mar  
2
- Usable to 1E14 Neutrons/cm  
Symbol  
D
This MOSFET is an enhancement-mode silicon-gate power  
field effect transistor of the vertical DMOS (VDMOS)  
structure. It is specifically designed and processed to be  
radiation tolerant. The MOSFET is well suited for  
applications exposed to radiation environments such as  
switching regulation, switching converters, power  
distribution, motor drives and relay drivers as well as other  
power control and conditioning applications. As with  
conventional MOSFETs these Radiation Hardened  
MOSFETs offer ease of voltage control, fast switching  
speeds and ability to parallel switching devices.  
G
S
Packaging  
TO-205AF  
Reliability screening is available as either TXV or Space  
equivalent of MIL-PRF-19500.  
Formerly available as type TA45228W.  
Ordering Information  
G
D
S
RAD LEVEL SCREENING LEVEL PART NUMBER/BRAND  
10K  
Engineering samples FSGL134D1  
100K  
100K  
TXV  
FSGL134R3  
FSGL134R4  
Space  
FSGL134R Rev. A1  
©2001 Fairchild Semiconductor Corporation  
4-1  
FSGL134R  
o
Absolute Maximum Ratings T = 25 C, Unless Otherwise Specified  
C
FSGL134R  
150  
UNITS  
Drain to Source Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V  
V
V
DS  
Drain to Gate Voltage (R  
= 20k) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V  
150  
GS  
DGR  
Continuous Drain Current  
o
T
T
= 25 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I  
10  
6
A
A
A
V
C
D
o
= 100 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I  
C
D
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I  
40  
±30  
DM  
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V  
GS  
Maximum Power Dissipation  
o
T
T
= 25 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P  
25  
10  
W
W
C
T
o
= 100 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P  
C
T
o
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
0.20  
40  
W/ C  
Single Pulsed Avalanche Current, L = 100µH, (See Test Figure) . . . . . . . . . . . . . . . . . . . . . .I  
A
A
A
AS  
Continuous Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I  
10  
S
Pulsed Source Current (Body Diode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I  
40  
SM  
o
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T , T  
-55 to 150  
300  
C
J
STG  
o
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T  
(Distance >0.063in (1.6mm) from Case, 10s Max)  
C
L
Weight (Typical)  
1.0 (Typical)  
g
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the  
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
o
Electrical Specifications  
T
= 25 C, Unless Otherwise Specified  
C
PARAMETER  
SYMBOL  
BV  
TEST CONDITIONS  
= 1mA, V = 0V  
MIN  
TYP  
MAX  
-
UNITS  
V
Drain to Source Breakdown Voltage  
Gate Threshold Voltage  
I
150  
-
DSS  
GS(TH)  
D
GS  
o
V
V
I
= V  
DS  
,
T
T
T
T
T
T
T
= -55 C  
-
-
5.5  
4.5  
-
V
GS  
= 1mA  
C
C
C
C
C
C
C
o
D
= 25 C  
2.0  
-
V
o
= 125 C  
1.0  
-
-
V
o
Zero Gate Voltage Drain Current  
Gate to Source Leakage Current  
I
V
V
= 120V,  
= 0V  
= 25 C  
-
25  
250  
100  
200  
1.30  
0.125  
0.219  
20  
40  
35  
25  
28  
12  
10  
-
µA  
µA  
nA  
nA  
V
DSS  
DS  
GS  
o
= 125 C  
-
-
o
I
V
= ±30V  
= 25 C  
-
-
GSS  
GS  
o
= 125 C  
-
-
Drain to Source On-State Voltage  
Drain to Source On Resistance  
V
V
= 12V, I = 10A  
-
-
DS(ON)  
GS  
D
o
r
I
V
= 6A,  
T
T
= 25 C  
-
0.110  
DS(ON)12  
D
C
= 12V  
o
GS  
= 125 C  
-
-
-
C
Turn-On Delay Time  
Rise Time  
t
V
R
R
= 75V, I = 10A,  
-
ns  
ns  
ns  
ns  
nC  
nC  
nC  
nC  
nC  
V
d(ON)  
DD  
D
= 7.5, V  
= 12V,  
L
GS  
t
-
-
r
= 7.5Ω  
GS  
Turn-Off Delay Time  
Fall Time  
t
-
-
d(OFF)  
t
-
-
f
Total Gate Charge  
Gate Charge Source  
Gate Charge Drain  
Gate Charge at 20V  
Threshold Gate Charge  
Plateau Voltage  
Q
V
= 0V to 12V  
75V < V  
< 120V,  
-
26  
10  
8
g(12)  
GS  
DD  
= 10A  
I
D
Q
Q
-
gs  
-
gd  
Q
V
V
= 0V to 20V  
= 0V to 2V  
-
40  
3
g(20)  
GS  
GS  
Q
-
-
g(TH)  
V
I
= 10A, V  
= 15V  
-
7
-
(PLATEAU)  
D
DS  
= 25V, V = 0V,  
GS  
Input Capacitance  
Output Capacitance  
Reverse Transfer Capacitance  
C
V
-
1200  
275  
16  
-
-
pF  
pF  
pF  
ISS  
DS  
f = 1MHz  
C
C
-
-
OSS  
-
-
RSS  
o
Thermal Resistance Junction to Case  
R
-
5.0  
C/W  
JC  
θ
FSGL134R Rev. A1  
©2001 Fairchild Semiconductor Corporation  
4-2  
FSGL134R  
Source to Drain Diode Specifications  
PARAMETER  
Forward Voltage  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
1.5  
190  
-
UNITS  
V
V
I
I
= 10A  
-
-
-
-
-
SD  
SD  
Reverse Recovery Time  
Reverse Recovery Charge  
t
= 10A, dI /dt = 100A/µs  
ns  
rr  
SD  
SD  
Q
1.0  
µC  
RR  
o
Electrical Specifications up to 100K RAD T = 25 C, Unless Otherwise Specified  
C
PARAMETER  
Drain to Source Breakdown Volts  
Gate to Source Threshold Volts  
Gate to Body Leakage  
SYMBOL  
TEST CONDITIONS  
= 0, I = 1mA  
MIN  
MAX  
-
UNITS  
(Note 3)  
BV  
V
V
V
V
V
V
150  
V
V
DSS  
GS  
GS  
GS  
GS  
GS  
GS  
D
(Note 3)  
V
= V , I = 1mA  
DS  
2.0  
4.5  
GS(TH)  
D
(Notes 2, 3)  
(Note 3)  
I
I
= ±30V, V  
= 0V  
= 120V  
-
-
-
-
100  
25  
nA  
µA  
V
GSS  
DS  
Zero Gate Leakage  
= 0, V  
DSS  
DS  
= 12V, I = 10A  
Drain to Source On-State Volts  
Drain to Source On Resistance  
NOTES:  
(Notes 1, 3)  
(Notes 1, 3)  
V
1.30  
0.125  
DS(ON)  
D
r
= 12V, I = 6  
DS(ON)12  
D
1. Pulse test, 300µs Max.  
2. Absolute value.  
3. Insitu Gamma bias must be sampled for both V  
GS  
= 12V, V  
DS  
= 0V and V  
= 0V, V  
= 80% BV .  
DSS  
GS  
DS  
Single Event Effects (SEB, SEGR) Note 4  
ENVIRONMENT (NOTE 5)  
(Note 6)  
(Note 7)  
MAXIMUM  
APPLIED  
TYPICAL LET  
(MeV/mg/cm)  
TYPICAL RANGE  
V
BIAS  
V
BIAS  
GS  
(V)  
DS  
(V)  
TEST  
SYMBOL  
(µ)  
Single Event Effects Safe Operating Area  
SEESOA  
37  
60  
82  
82  
36  
32  
28  
28  
-20  
-10  
-5  
150  
150  
120  
90  
-10  
NOTES:  
4. Testing conducted at Brookhaven National Labs or Texas A&M.  
2
o
5. Fluence = 1E5 ions/cm (typical), T = 25 C.  
6. Ion Species: LET = 37, Br or Kr; LET = 60, I or Xe; LET = 82, Au  
7. Does not exhibit Single Event Burnout (SEB) or Single Event Gate Rupture (SEGR).  
Performance Curves Unless Otherwise Specified  
2
µ
µ
µ
LET = 37MeV/mg/cm , RANGE = 36  
2
LET = 60MeV/mg/cm , RANGE = 32  
200  
160  
120  
80  
2
LET = 82MeV/mg/cm , RANGE = 28  
LET = 37  
2
FLUENCE = 1E5 IONS/cm (TYPICAL)  
150  
100  
50  
LET = 82  
40  
LET = 60  
20  
o
0
TEMP = 25  
-4  
C
0
5
10  
15  
25  
30  
35  
40  
0
0
-8  
-12  
-16  
-20  
-24  
NEGATIVE V  
BIAS (V)  
GS  
V
(V)  
GS  
FIGURE 1. SINGLE EVENT EFFECTS SAFE OPERATING AREA  
FIGURE 2. TYPICAL SEE SIGNATURE CURVE  
FSGL134R Rev. A1  
©2001 Fairchild Semiconductor Corporation  
4-3  
FSGL134R  
Performance Curves Unless Otherwise Specified (Continued)  
1E-3  
12  
10  
8
1E-4  
ILM = 10A  
30A  
1E-5  
6
100A  
300A  
4
1E-6  
2
0
1E-7  
-50  
0
50  
150  
100  
o
10  
30  
100  
300  
1000  
DRAIN SUPPLY (V)  
T
, CASE TEMPERATURE ( C)  
C
FIGURE 3. TYPICAL DRAIN INDUCTANCE REQUIRED TO  
FIGURE 4. MAXIMUM CONTINUOUS DRAIN CURRENT vs  
TEMPERATURE  
LIMIT GAMMA DOT CURRENT TO I  
AS  
100  
10  
1
o
T
= 25  
C
C
12V  
Q
G
100  
µ
s
1ms  
Q
Q
GD  
OPERATION IN THIS  
AREA MAY BE  
LIMITED BY r  
DS(ON)  
GS  
V
G
10ms  
.1  
1
10  
100  
500  
CHARGE  
FIGURE 6. BASIC GATE CHARGE WAVEFORM  
V
, DRAIN-TO-SOURCE VOLTAGE (V)  
DS  
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA  
70  
2.5  
V
V
V
V
= 14V  
= 12V  
= 10V  
= 8V  
GS  
GS  
GS  
GS  
PULSE DURATION = 250ms, V  
= 12V, I = 6A  
D
GS  
60  
50  
40  
30  
20  
10  
0
2.0  
1.5  
1.0  
0.5  
0
V
= 6V  
GS  
0
2
4
6
8
10  
-80  
-40  
0
40  
80  
120  
160  
o
V
, DR A IN -TO-SO UR C E VOLTA G E (V)  
DS  
T
, JUNCTION TEMPERATURE ( C)  
J
FIGURE 7. TYPICAL NORMALIZED r  
TEMPERATURE  
vs JUNCTION  
FIGURE 8. TYPICAL OUTPUT CHARACTERISTICS  
DS(ON)  
FSGL134R Rev. A1  
©2001 Fairchild Semiconductor Corporation  
4-4  
FSGL134R  
Performance Curves Unless Otherwise Specified (Continued)  
10  
1
0.5  
0.2  
0.1  
0.1  
0.05  
0.02  
0.01  
P
DM  
SINGLE PULSE  
0.01  
NOTES:  
DUTY FACTOR: D = t /t  
t
1
2
1
t
PEAK T = P  
DM  
x Z  
+ T  
2
J
θJC  
C
0.001  
-5  
-4  
-3  
10  
-2  
10  
-1  
0
1
10  
10  
10  
10  
10  
t, RECTANGULAR PULSE DURATION (s)  
FIGURE 9. NORMALIZED MAXIMUM TRANSIENT THERMAL RESPONSE  
100  
o
STARTING T = 25  
C
J
o
STARTING T = 150  
J
C
10  
IF R = 0  
t
= (L) (I ) / (1.3 RATED BV  
- V  
DD  
)
AV  
IF R  
AS  
DSS  
0
t
= (L/R) ln [(I *R) / (1.3 RATED BV  
- V ) + 1]  
DD  
AV  
AS  
DSS  
1
.001  
1
10  
.01  
t
.1  
, TIME IN AVALANCHE (ms)  
AV  
FIGURE 10. UNCLAMPED INDUCTIVE SWITCHING  
Test Circuits and Waveforms  
ELECTRONIC SWITCH OPENS  
WHEN I IS REACHED  
AS  
V
DS  
L
BV  
+
I
-
DSS  
CURRENT  
TRANSFORMER  
AS  
t
P
V
DS  
I
AS  
V
VARY t TO OBTAIN  
DD  
P
+
50Ω  
REQUIRED PEAK I  
AS  
V
DD  
V
20V  
-
GS  
50V-150V  
DUT  
50Ω  
t
P
0V  
t
AV  
FIGURE 11. UNCLAMPED ENERGY TEST CIRCUIT  
FIGURE 12. UNCLAMPED ENERGY WAVEFORMS  
FSGL134R Rev. A1  
©2001 Fairchild Semiconductor Corporation  
4-5  
FSGL134R  
Test Circuits and Waveforms  
t
t
ON  
OFF  
t
d(OFF)  
V
DD  
t
d(ON)  
t
t
f
r
R
L
V
DS  
90%  
90%  
V
DS  
V
= 12V  
GS  
10%  
10%  
DUT  
0V  
90%  
50%  
R
GS  
50%  
V
GS  
10%  
PULSE WIDTH  
FIGURE 13. RESISTIVE SWITCHING TEST CIRCUIT  
FIGURE 14. RESISTIVE SWITCHING WAVEFORMS  
Screening Information  
Screening is performed in accordance with the latest revision in effect of MIL-PRF-19500, (Screening Information Table).  
o
Delta Tests and Limits (JANTXV Equivalent, JANS Equivalent) T = 25 C, Unless Otherwise Specified  
C
PARAMETER  
Gate to Source Leakage Current  
Zero Gate Voltage Drain Current  
Drain to Source On Resistance  
Gate Threshold Voltage  
NOTES:  
SYMBOL  
TEST CONDITIONS  
= ±30V  
MAX  
UNITS  
nA  
I
V
V
±20 (Note 8)  
±25 (Note 8)  
±20% (Note 9)  
±20% (Note 9)  
GSS  
GS  
I
= 80% Rated Value  
o
µA  
DSS  
DS  
r
T
= 25 C at Rated I  
D
DS(ON)  
C
V
I
= 1.0mA  
V
GS(TH)  
D
8. Or 100% of Initial Reading (whichever is greater).  
9. Of Initial Reading.  
Screening Information  
TEST  
JANTXV EQUIVALENT  
JANS EQUIVALENT  
Unclamped Inductive Switching  
Thermal Response  
Gate Stress  
V
= 20V, L = 0.1mH; Limit = 40A  
V
= 20V, L = 0.1mH; Limit = 40A  
GS(PEAK)  
GS(PEAK)  
t
= 10ms; V = 25V; I = 1A; LIMIT = 60mV  
t
= 10ms; V = 25V; I = 1A; LIMIT = 60mV  
H
H
H
H
H
H
V
= 45V, t = 250µs  
V
= 45V, t = 250µs  
GS  
GS  
Pind  
Optional  
Required  
MIL-PRF-19500 Group A,  
Subgroup 2 (All Static Tests at 25 C)  
Pre Burn-In Tests (Note 10)  
MIL-PRF-19500 Group A,  
Subgroup 2 (All Static Tests at 25 C)  
o
o
Steady State Gate  
Bias (Gate Stress)  
MIL-PRF-750, Method 1042, Condition B  
MIL-PRF-750, Method 1042, Condition B  
V
= 80% of Rated Value,  
V
= 80% of Rated Value,  
GS  
= 150 C, Time = 48 hours  
GS  
T = 150 C, Time = 48 hours  
A
o
o
T
A
Interim Electrical Tests (Note 10)  
All Delta Parameters Listed in the Delta Tests and  
Limits Table  
All Delta Parameters Listed in the Delta Tests and  
Limits Table  
Steady State Reverse  
Bias (Drain Stress)  
MIL-PRF-750, Method 1042, Condition A  
MIL-PRF-750, Method 1042, Condition A  
V
= 80% of Rated Value,  
V
= 80% of Rated Value,  
DS  
= 150 C, Time = 160 hours  
DS  
T = 150 C, Time = 240 hours  
A
o
o
T
A
PDA  
10%  
5%  
Final Electrical Tests (Note 10)  
MIL-PRF-19500, Group A, Subgroup 2  
MIL-PRF-19500, Group A,  
Subgroups 2 and 3  
NOTE:  
10. Test limits are identical pre and post burn-in.  
Additional Tests  
PARAMETER  
Safe Operating Area  
Thermal Impedance  
SYMBOL  
TEST CONDITIONS  
= 120V, t = 10ms  
MAX  
0.7  
UNITS  
A
SOA  
V
DS  
= 500ms; V = 25V; I = 1A  
V  
SD  
t
230  
mV  
H
H
H
FSGL134R Rev. A1  
©2001 Fairchild Semiconductor Corporation  
4-6  
FSGL134R  
Rad Hard Data Packages - Fairchild Power Transistors  
TXV Equivalent  
Class S - Equivalents  
1. RAD HARD TXV EQUIVALENT - STANDARD DATA  
PACKAGE  
1. RAD HARD “S” EQUIVALENT - STANDARD DATA  
PACKAGE  
A. Certificate of Compliance  
A. Certificate of Compliance  
B. Serialization Records  
C. Assembly Flow Chart  
D. SEM Photos and Report  
B. Assembly Flow Chart  
C. Preconditioning - Attributes Data Sheet  
D. Group A  
E. Group B  
F. Group C  
G. Group D  
- Attributes Data Sheet  
- Attributes Data Sheet  
- Attributes Data Sheet  
- Attributes Data Sheet  
E. Preconditioning - Attributes Data Sheet  
- HTRB - Hi Temp Gate Stress Post  
Reverse Bias Data and Delta Data  
- HTRB - Hi Temp Drain Stress Post  
Reverse Bias Delta Data  
2. RAD HARD TXV EQUIVALENT - OPTIONAL DATA  
PACKAGE  
F. Group A  
G. Group B  
H. Group C  
I. Group D  
- Attributes Data Sheet  
- Attributes Data Sheet  
- Attributes Data Sheet  
- Attributes Data Sheet  
A. Certificate of Compliance  
B. Assembly Flow Chart  
C. Preconditioning - Attributes Data Sheet  
- Pre and Post Burn-In Read and Record  
Data  
2. RAD HARD MAX. “S” EQUIVALENT - OPTIONAL  
DATA PACKAGE  
D. Group A  
E. Group B  
- Attributes Data Sheet  
A. Certificate of Compliance  
B. Serialization Records  
C. Assembly Flow Chart  
D. SEM Photos and Report  
- Attributes Data Sheet  
- Pre and Post Read and Record Data for  
Intermittent Operating Life (Subgroup B3)  
- Bond Strength Data (Subgroup B3)  
- Pre and Post High Temperature Operating  
Life Read and Record Data (Subgroup B6)  
E. Preconditioning - Attributes Data Sheet  
- HTRB - Hi Temp Gate Stress Post  
Reverse Bias Data and Delta Data  
- HTRB - Hi Temp Drain Stress Post  
Reverse Bias Delta Data  
F. Group C  
G. Group D  
- Attributes Data Sheet  
- Pre and Post Read and Record Data for  
Intermittent Operating Life (Subgroup C6)  
- Bond Strength Data (Subgroup C6)  
- X-Ray and X-Ray Report  
- Attributes Data Sheet  
- Pre and Post RAD Read and Record Data  
F. Group A  
G. Group B  
H. Group C  
I. Group D  
- Attributes Data Sheet  
- Subgroups A2, A3, A4, A5 and A7 Data  
- Attributes Data Sheet  
- Subgroups B1, B3, B4, B5 and B6 Data  
- Attributes Data Sheet  
- Subgroups C1, C2, C3 and C6 Data  
- Attributes Data Sheet  
- Pre and Post Radiation Data  
FSGL134R Rev. A1  
©2001 Fairchild Semiconductor Corporation  
4-7  
FSGL134R  
TO-205AF  
3 LEAD JEDEC TO-205AF HERMETIC METAL CAN PACKAGE  
ØD  
INCHES  
MIN  
MILLIMETERS  
ØD  
1
SYMBOL  
MAX  
0.180  
0.021  
0.370  
0.335  
0.105  
0.210  
0.105  
0.020  
0.034  
0.045  
0.560  
-
MIN  
4.07  
0.41  
8.89  
8.01  
2.42  
4.83  
2.42  
0.26  
0.72  
0.74  
12.70  
1.91  
MAX  
4.57  
0.53  
9.39  
8.50  
2.66  
5.33  
2.66  
0.50  
0.86  
1.14  
14.22  
-
NOTES  
P
A
0.160  
0.016  
0.350  
0.315  
0.095  
0.190  
0.095  
0.010  
0.028  
0.029  
0.500  
0.075  
-
2, 3  
-
A
Øb  
ØD  
SEATING  
PLANE  
h
ØD  
e
-
1
L
Øb  
4
4
4
-
e
1
2
e
e
e
1
h
j
-
o
90  
2
k
L
P
-
e
2
1
3
3
5
o
45  
j
k
NOTES:  
1. These dimensions are within allowable dimensions of Rev. E of  
JEDEC TO-205AF outline dated 11-82.  
2. Lead dimension (without solder).  
3. Solder coating may vary along lead length, add typically 0.002  
inches (0.05mm) for solder coating.  
4. Positionof lead to be measured 0.100inches (2.54mm) from bottom  
of seating plane.  
5. This zone controlled for automatic handling. The variation in  
actual diameter within this zone shall not exceed 0.010 inches  
(0.254mm).  
6. Lead no. 3 butt welded to stem base.  
7. Controlling dimension: Inch.  
8. Revision 3 dated 6-94.  
FSGL134R Rev. A1  
©2001 Fairchild Semiconductor Corporation  
4-8  
FSGL134R  
TRADEMARKS  
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is  
not intended to be an exhaustive list of all such trademarks.  
®
ACEx™  
Bottomless™  
CoolFET™  
CROSSVOLT™  
DenseTrench™  
DOME™  
FAST  
OPTOPLANAR™  
PACMAN™  
POP™  
STAR*POWER™  
Stealth™  
SuperSOT™-3  
SuperSOT™-6  
SuperSOT™-8  
SyncFET™  
FASTr™  
FRFET™  
GlobalOptoisolator™  
GTO™  
HiSeC™  
Power247™  
PowerTrench  
®
QFET™  
EcoSPARK™  
E CMOS™  
Ensigna™  
FACT™  
ISOPLANAR™  
LittleFET™  
MicroFET™  
MICROWIRE™  
OPTOLOGIC™  
QS™  
QTOptpelectronics™  
Quiet Series™  
SILENTSWITCHER  
SMART START™  
TinyLogic™  
2
TruTranslation™  
UHC™  
®
®
UltraFET  
FACT Quiet Series™  
VCX™  
STAR*POWER is used under license  
DISCLAIMER  
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY  
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY  
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;  
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.  
LIFE SUPPORT POLICY  
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT  
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR  
CORPORATION.  
As used herein:  
1. Life support devices or systems are devices or systems  
which, (a) are intended for surgical implant into the body,  
or (b) support or sustain life, or (c) whose failure to perform  
when properly used in accordance with instructions for use  
provided in the labeling, can be reasonably expected to  
result in significant injury to the user.  
2. A critical component is any component of a life support  
device or system whose failure to perform can be  
reasonably expected to cause the failure of the life support  
device or system, or to affect its safety or effectiveness.  
PRODUCT STATUS DEFINITIONS  
Definition of Terms  
Datasheet Identification  
Product Status  
Definition  
Advance Information  
Formative or  
In Design  
This datasheet contains the design specifications for  
product development. Specifications may change in  
any manner without notice.  
Preliminary  
First Production  
This datasheet contains preliminary data, and  
supplementary data will be published at a later date.  
Fairchild Semiconductor reserves the right to make  
changes at any time without notice in order to improve  
design.  
No Identification Needed  
Obsolete  
Full Production  
This datasheet contains final specifications. Fairchild  
Semiconductor reserves the right to make changes at  
any time without notice in order to improve design.  
Not In Production  
This datasheet contains specifications on a product  
that has been discontinued by Fairchild semiconductor.  
The datasheet is printed for reference information only.  
FSGL134R Rev. A1  
©2001 Fairchild Semiconductor Corporation  
4-9  

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