FSL126MRT_技术文档

May 2012

FSL126MRT

Green-Mode Fairchild Power Switch (FPS™)

Features

Description

The FSL126MRT is an integrated Pulse Width

Modulation (PWM) controller and SenseFET specifically

designed for offline Switch-Mode Power Supplies

(SMPS) with minimal external components. The PWM

controller includes an integrated fixed-frequency

oscillator, Under-Voltage Lockout (UVLO), Leading-

Edge Blanking (LEB), optimized gate driver, internal

soft-start, temperature-compensated precise current

sources for loop compensation, and self-protection

circuitry. Compared with a discrete MOSFET and PWM

controller solution, the FSL126MRT can reduce total

cost, component count, size, and weight; while

simultaneously increasing efficiency, productivity, and

system reliability. This device provides a basic platform

suited for cost-effective design of a flyback converter.

. Internal Avalanched Rugged 650V SenseFET

. Advanced Soft Burst-Mode Operation for Low

Standby Power and Low Audible Noise

. Random Frequency Fluctuation for Low EMI

. Pulse-by-Pulse Current Limit

. Various Protection Functions: Overload Protection

(OLP), Over-Voltage Protection (OVP), Abnormal

Over-Current Protection (AOCP), Internal Thermal

Shutdown (TSD) with Hysteresis and Under-Voltage

Lockout (UVLO) with Hysteresis

. Low Operating Current(0.4mA) in Burst Mode

. Internal Startup Circuit

. Built-in Soft-Start: 15ms

. Auto-Restart Mode

Applications

. Power Supply for STB Home Appliances, and DVD

Combination

Ordering Information

Output Power Table⁽²⁾

Operating

Junction

Temperature

Part

Number

CurrentR_DS(ON)230V_AC± 15%⁽³⁾

85~265V_AC

Package

Replaces Device

Limit (Max.)

Open

Adapter⁽⁴⁾

Frame⁽⁵⁾

TO-220F

6-Lead⁽¹⁾

W-Forming

-40°C ~

+125°C

FSL126MRT

1.2A

30W

40W

17W

25W KA5M0265RYDTU

6.2Ω

Notes:

1. Pb-free package per JEDEC J-STD-020B.

2. The junction temperature can limit the maximum output power.

3. 230V_ACor 100/115V_ACwith voltage doubler.

4. Typical continuous power in a non-ventilated enclosed adapter measured at 50°C ambient temperature.

5. Maximum practical continuous power in an open-frame design at 50°C ambient temperature.

FSL126MRT • Rev. 1.0.0

www.fairchildsemi.com

Application Circuit

V_O

AC

IN

V_STR

Drain

GND

V_CC

FB

Figure 1.

Typical Application Circuit

Internal Block Diagram

V_STR

V_CC

Drain

6

3

1

V_burst

0.40V / 0.55V

I_CH

Soft Burst

V_REF

V_CCGood

7.5V / 12V

Random

OSC

V_CC

V_REF

Soft-Start

2.0µA

I_DELAY

90µA

I_FB

S

R

Q

PWM

Gate

Driver

FB

4

5

3R

R

LEB (350ns)

NC

2

GND

V_AOCP

V_SD

7.0V

TSD

S

R

Q

V_CC

V_CCGood

Q

V_OVP

24.5V

Figure 2.

Internal Block Diagram

FSL126MRT • Rev. 1.0.0

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2

Pin Configuration

Figure 3.

Pin Configuration (Top View)

Pin Definitions

Pin #

Name

Drain

GND

Description

1

2

SenseFET Drain. High-voltage power SenseFET drain connection.

Ground. This pin is the control ground and the SenseFET source.

Power Supply. This pin is the positive supply input, which provides the internal operating

current for both startup and steady-state operation.

3

V_CC

Feedback. This pin is internally connected to the inverting input of the PWM comparator.

The collector of an opto-coupler is typically tied to this pin. For stable operation, a capacitor

should be placed between this pin and GND. If the voltage of this pin reaches 7V, the overload

protection triggers, which shuts down the FPS.

4

5

6

FB

NC

No Connection

Startup. This pin is connected directly, or through a resistor, to the high-voltage DC link.

At startup, the internal high-voltage current source supplies internal bias and charges the

external capacitor connected to the V_CCpin. Once V_CCreaches 12V, the internal current

source (I_CH) is disabled.

V_STR

FSL126MRT • Rev. 1.0.0

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3

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only.

Symbol

V_STR

V_DS

Parameter

Min.

Max.

650

26

Unit

V

V_STRPin Voltage

Drain Pin Voltage

V_CCPin Voltage

V

V_CC

V_FB

V

Feedback Pin Voltage

Drain Current Pulsed⁽⁶⁾

-0.3

10.0

8

V

I_DM

A

I_DS

Continuous Switching Drain Current

Single Pulsed Avalanche Energy⁽⁷⁾

Total Power Dissipation (T_C=25°C)⁽⁸⁾

Maximum Junction Temperature

Operating Junction Temperature⁽⁹⁾

Storage Temperature

2

A

E_AS

73

mJ

W

°C

P_D

50

150

+125

+150

T_J

-40

-55

T_STG

Notes:

6. Repetitive peak switching current when the inductive load is assumed: Limited by maximum duty (D_MAX=0.74)

and junction temperature (see Figure 4).

7. L=45mH, starting T_J=25°C.

8. Infinite cooling condition (refer to the SEMI G30-88).

9. Although this parameter guarantees IC operation, it does not guarantee all electrical characteristics.

Figure 4.

Repetitive Peak Switching Current

ESD Capability

Symbol

Parameter

Value

Unit

Human Body Model, JESD22-A114

Charged Device Model, JESD22-C101

5

2

ESD

KV

Thermal Impedance

T_A=25°C unless otherwise specified.

Symbol

Parameter

Value

63.5

2.9

Unit

°C/W

θ_JA

θ_JC

Junction-to-Ambient Thermal Impedance⁽¹⁰⁾

Junction-to-Case Thermal Impedance⁽¹¹⁾

Notes:

10. Free standing without heat sink under natural convection condition, per JEDEC 51-2 and 1-10.

11. Infinite cooling condition per Mil Std. 883C method 1012.1.

www.fairchildsemi.com

FSL126MRT • Rev. 1.0.0

4

Electrical Characteristics

T_J= 25°C unless otherwise specified.

Symbol

Parameter

Condition

Min. Typ. Max.

Unit

SenseFET Section

BV_DSS

I_DSS

Drain-Source Breakdown Voltage

Zero-Gate-Voltage Drain Current

Drain-Source On-State Resistance

Input Capacitance⁽¹²⁾

Output Capacitance⁽¹²⁾

Reverse Transfer Capacitance⁽¹²⁾

Rise Time

650

V

_CC=0V, I_D=250μA

250

V_DS=520V, T_A=125°C

μA

Ω

R_DS(ON)

C_ISS

C_OSS

C_RSS

t_r

V_GS=10V, I_D=1A

4.9

210

33.3

4.1

6.2

V_DS=25V, V_GS=0V, f=1MHz

V_DS=325V, I_D=2A, R_G=25Ω

pF

ns

16.4

23

t_f

Fall Time

t_d(on)

t_d(off)

Turn-On Delay

23

Turn-Off Delay

17.2

Control Section

f_S

Δf_S

Switching Frequency⁽¹²⁾

Switching Frequency Variation⁽¹²⁾

V_CC=14V, V_FB=4V

-25°C < T_J< 125°C

V_CC=14V, V_FB=4V

V_CC=14V, V_FB=0V

V_FB=0

61

67

±5

67

73

±10

73

kHz

%

D_MAX

D_MIN

I_FB

Maximum Duty Ratio

%

Minimum Duty Ratio

0

%

Feedback Source Current

65

11

90

12

7.5

15

115

13

μA

V

V_START

V_STOP

t_S/S

V_FB=0V, V_CCSweep

After Turn-on, V_FB=0V

V_CCSweep

UVLO Threshold Voltage

Internal Soft-Start Time

7.0

8.0

V

ms

Burst-Mode Section

V_BURH

0.46

0.33

0.55

0.40

150

0.66

0.48

V

V_BURL

Burst-Mode Voltage

V_CC=14V, V_FBSweep

Hys

mV

Protection Section

I_LIM

V_SD

Peak Drain Current Limit

1.05

6.45

1.2

1.20

7.00

2.0

1.34

7.55

2.8

A

V

di/dt=300mA/μs

Shutdown Feedback Voltage

Shutdown Delay Current

Leading-Edge Blanking Time^(12,14)

V_CC=14V, V_FBSweep

V_CC=14V, V_FB=4V

I_DELAY

t_LEB

μA

ns

V

350

24.5

140

60

V_OVP

T_SD

Over-Voltage Protection

V_CCSweep

23.0

130

26.0

150

Shutdown Temperature

Hysteresis

°C

Thermal Shutdown Temperature⁽¹²⁾

Hys

Continued on the following page…

FSL126MRT • Rev. 1.0.0

www.fairchildsemi.com

5

Electrical Characteristics (Continued)

T_J= 25°C unless otherwise specified.

Symbol

Parameter

Condition

Min.

Typ. Max.

Unit

Total Device Section

Operating Supply Current,

(Control Part in Burst Mode)

I_OP

I_OPS

V

_CC=14V, V_FB=0V

0.3

0.4

1.00

120

0.5

mA

μA

Operating Switching Current,

(Control Part and SenseFET Part)

V_CC=14V, V_FB=2V

1.35

V_CC=11V (Before V_CC

Reaches V_START

I_START

Start Current

85

155

1.3

)

I_CH

Startup Charging Current

V_CC=V_FB=0V, V_STR=40V

V_CC=V_FB=0V, V_STRSweep

0.7

1.0

26

mA

V

V_STR

Minimum V_STRSupply Voltage

Notes:

12. Although these parameters are guaranteed, they are not 100% tested in production.

13. Average value.

14. t_LEBincludes gate turn-on time.

Comparison of KA5M0265R and FSL126MRT

Function

KA5M0265RYDTU

FSL126MRT

Built-in

Advantages of FSL126MRT

Random Frequency

Fluctuation

N/A

7mA

N/A

Low EMI

Operating Current

0.4mA

Very low stand-by power

High-Voltage

Startup Circuit

Built-in

OLP

OVP

OLP

OVP

TSD

Protections

Enhanced protections and high reliability

AOCP

TSD with Hysteresis

The difference of input power between the

low and high input voltage is quite small.

Power Balance

Long t_CLD

Very Short t_CLD

FSL126MRT • Rev. 1.0.0

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6

Typical Performance Characteristics

Characteristic graphs are normalized at T_A=25°C.

1.40

1.30

1.20

1.10

1.00

0.90

0.80

0.70

0.60

1.40

1.30

1.20

1.10

1.00

0.90

0.80

0.70

-40'C -20'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C

0.60

-40'C -20'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 12

Temperature [ °C]

Figure 5.

Operating Supply Current (I_OP) vs. T_A

Figure 6.

Operating Switching Current (I_OPS) vs. T_A

1.40

1.30

1.20

1.10

1.00

0.90

0.80

0.70

0.60

1.40

1.30

1.20

1.10

1.00

0.90

0.80

0.70

0.60

-40'C -20'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 12

Temperature [ °C]

Figure 7.

Startup Charging Current (I_CH) vs. T_A

Figure 8.

Peak Drain Current Limit (I_LIM) vs. T_A

1.40

1.30

1.20

1.10

1.00

0.90

0.80

0.70

0.60

1.40

1.30

1.20

1.10

1.00

0.90

0.80

0.70

0.60

-40'C -20'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C

-40'C -20'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 12

Temperature [ °C]

Figure 9.

Feedback Source Current (I_FB) vs. T_A

Figure 10. Shutdown Delay Current (I_DELAY) vs. T_A

FSL126MRT • Rev. 1.0.0

www.fairchildsemi.com

7

Typical Performance Characteristics

Characteristic graphs are normalized at T_A=25°C.

1.40

1.30

1.20

1.10

1.00

0.90

0.80

0.70

1.40

1.30

1.20

1.10

1.00

0.90

0.80

0.70

0.60

-40'C -20'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125

Temperature [ °C]

Figure 11. UVLO Threshold Voltage (V_START) vs. T_A

Figure 12. UVLO Threshold Voltage (V_STOP) vs. T_A

1.40

1.30

1.20

1.10

1.00

0.90

0.80

0.70

1.40

1.30

1.20

1.10

1.00

0.90

0.80

0.70

0.60

-40'C -20'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125

-40'C -20'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 12

Temperature [ °C]

Figure 13. Shutdown Feedback Voltage (V_SD) vs. T_A

Figure 14. Over-Voltage Protection (V_OVP) vs. T_A

1.40

1.30

1.20

1.10

1.00

0.90

0.80

0.70

1.40

1.30

1.20

1.10

1.00

0.90

0.80

0.70

0.60

-40'C -20'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125

Temperature [ °C]

Figure 15. Switching Frequency (f_S) vs. T_A

Figure 16. Maximum Duty Ratio (D_MAX) vs. T_A

www.fairchildsemi.com

FSL126MRT • Rev. 1.0.0

8

Functional Description

1. Startup: At startup, an internal high-voltage current

source supplies the internal bias and charges the

external capacitor (C_VCC) connected to the V_CCpin, as

illustrated in Figure 17. When V_CCreaches 12V, the

FSL126MRT begins switching and the internal high-

voltage current source is disabled. Normal switching

operation continues and the power is supplied from the

auxiliary transformer winding unless V_CCgoes below the

stop voltage of 7.5V.

3. Feedback Control: This device employs Current-

Mode control, as shown in Figure 18. An opto-coupler

(such as the FOD817) and shunt regulator (such as the

KA431) are typically used to implement the feedback

network. Comparing the feedback voltage with the

voltage across the R_SENSEresistor makes it possible to

control the switching duty cycle. When the reference pin

voltage of the shunt regulator exceeds the internal

reference voltage of 2.5V, the opto-coupler LED current

increases, pulling down the feedback voltage and

reducing drain current. This typically occurs when the

input voltage is increased or the output load is decreased.

3.1 Pulse-by-Pulse Current Limit: Because Current-

Mode control is employed, the peak current through

the SenseFET is limited by the inverting input of PWM

comparator (V_FB*), as shown in Figure 18. Assuming

that the 90μA current source flows only through the

internal resistor (3R + R =27kꢀ), the cathode voltage

of diode D2 is about 2.4V. Since D1 is blocked when

the feedback voltage (V_FB) exceeds 2.4V, the

maximum voltage of the cathode of D2 is clamped at

this voltage. Therefore, the peak value of the current

through the SenseFET is limited.

3.2 Leading-Edge Blanking (LEB): At the instant the

internal SenseFET is turned on, a high-current spike

usually occurs through the SenseFET, caused by

primary-side capacitance and secondary-side rectifier

reverse recovery. Excessive voltage across the

Figure 17. Startup Block

2. Soft-Start: The internal soft-start circuit increases

PWM comparator inverting input voltage, together with

the SenseFET current, slowly after startup. The typical

soft-start time is 15ms. The pulse width to the power

switching device is progressively increased to establish

the correct working conditions for the transformers,

inductors, and capacitors. The voltage on the output

capacitors is progressively increased to smoothly

establish the required output voltage. This helps prevent

transformer saturation and reduces stress on the

secondary diode during startup.

R_SENSEresistor leads to incorrect feedback operation

in the Current-Mode PWM control. To counter this

effect, the leading-edge blanking (LEB) circuit inhibits

the PWM comparator for t_LEB(350ns) after the

SenseFET is turned on.

Figure 18. Pulse Width Modulation Circuit

FSL126MRT • Rev. 1.0.0

www.fairchildsemi.com

9

increasing until it reaches 7.0V, when the switching

operation is terminated, as shown in Figure 20. The

delay for shutdown is the time required to charge C_FB

from 2.4V to 7.0V with 2.0µA. This protection is

implemented in Auto-Restart Mode.

4. Protection Circuits: The FSL126MRT has several

self-protective functions, such as Overload Protection

(OLP), Abnormal Over-Current Protection (AOCP),

Over-Voltage Protection (OVP), and Thermal Shutdown

(TSD). All the protections are implemented as auto-

restart. Once the fault condition is detected, switching is

terminated and the SenseFET remains off. This causes

V_CCto fall. When V_CCfalls to the Under-Voltage Lockout

(UVLO) stop voltage of 7.5V, the protection is reset and

the startup circuit charges the V_CCcapacitor. When V_CC

reaches the start voltage of 12.0V, the FSL126MRT

resumes normal operation. If the fault condition is not

removed, the SenseFET remains off and V_CCdrops to

stop voltage again. In this manner, the auto-restart can

alternately enable and disable the switching of the

power SenseFET until the fault condition is eliminated.

Because these protection circuits are fully integrated

into the IC without external components, reliability is

improved without increasing cost.

Fault

occurs

Fault

removed

Power

on

V_DS

Figure 20. Overload Protection

4.2 Abnormal Over-Current Protection (AOCP):

When the secondary rectifier diodes or the

transformer pins are shorted, a steep current with

extremely high di/dt can flow through the SenseFET

during the minimum turn-on time. Even though the

FSL126MRT has overload protection, it is not enough

to protect in that abnormal case; due to the severe

current stress imposed on the SenseFET until OLP is

triggered. The internal AOCP circuit is shown in

Figure 21. When the gate turn-on signal is applied to

the power SenseFET, the AOCP block is enabled and

monitors the current through the sensing resistor. The

voltage across the resistor is compared with a preset

AOCP level. If the sensing resistor voltage is greater

than the AOCP level, the set signal is applied to the

S-R latch, resulting in the shutdown of the SMPS.

V_CC

12.0V

7.5V

t

Normal

operation

Fault

situation

Normal

operation

Figure 19. Auto-Restart Protection Waveforms

4.1 Overload Protection (OLP): Overload is defined

as the load current exceeding its normal level due to

an unexpected abnormal event. In this situation, the

protection circuit should trigger to protect the SMPS.

However, even when the SMPS is in normal

operation, the overload protection circuit can be

triggered during the load transition. To avoid this

undesired operation, the overload protection circuit is

designed to trigger only after a specified time to

determine whether it is a transient situation or a true

overload situation. Because of the pulse-by-pulse

current-limit capability, the maximum peak current

through the SenseFET is limited and, therefore, the

maximum input power is restricted with a given input

voltage. If the output consumes more than this

maximum power, the output voltage (V_OUT) decreases

below the set voltage. This reduces the current

through the opto-coupler LED, which also reduces the

opto-coupler transistor current, increasing the

feedback voltage (V_FB). If V_FBexceeds 2.4V, D1 is

blocked and the 2.0µA current source starts to charge

C_FBslowly up_.In this condition, V_FBcontinues

Figure 21. Abnormal Over-Current Protection

FSL126MRT • Rev. 1.0.0

www.fairchildsemi.com

10

4.4 Over-Voltage Protection (OVP): If the

secondary-side feedback circuit malfunctions or a

solder defect causes an opening in the feedback path,

the current through the opto-coupler transistor

becomes almost zero. Then V_FBclimbs up in a similar

manner to the overload situation, forcing the preset

maximum current to be supplied to the SMPS until the

overload protection is triggered. Because more energy

than required is provided to the output, the output

voltage may exceed the rated voltage before the

overload protection is triggered, resulting in the

breakdown of the devices in the secondary side. To

prevent this situation, an OVP circuit is employed. In

general, the V_CCis proportional to the output voltage

and the FS136MRT uses V_CCinstead of directly

monitoring the output voltage. If V_CCexceeds 24.5V,

an OVP circuit is triggered, resulting in the termination

of the switching operation. To avoid undesired

activation of OVP during normal operation, V_CCshould

be designed to be below 24.5V.

6. Random Frequency Fluctuation (RFF): Fluctuating

switching frequency of an SMPS can reduce EMI by

spreading the energy over a wide frequency range. The

amount of EMI reduction is directly related to the

switching frequency variation, which is limited internally.

The switching frequency is determined randomly by

external feedback voltage and an internal free-running

oscillator at every switching instant. This random

frequency fluctuation scatters the EMI noise around

typical switching frequency (67kHz) effectively and can

reduce the cost of the input filter included to meet the

EMI requirements (e.g. EN55022).

4.5 Thermal Shutdown (TSD): The SenseFET and

the control IC on a die in one package makes it easier

for the control IC to detect the over temperature of the

SenseFET. If the temperature exceeds 140°C, the

thermal shutdown is triggered and stops operation.

The FSL126MRT operates in Auto-Restart Mode until

the temperature decreases to around 80°C, when

normal operation resumes.

Figure 23. Random Frequency Fluctuation

5. Soft Burst-Mode Operation: To minimize power

dissipation in Standby Mode, the FSL126MRT enters

Burst-Mode operation. As the load decreases, the

feedback voltage decreases. The device automatically

enters Burst Mode when the feedback voltage drops

below V_BURL(400mV), as shown in Figure 22. At this

point, switching stops and the output voltages start to

drop at a rate dependent on standby current load. This

causes the feedback voltage to rise. Once it passes

V_BURH(550mV), switching resumes. The feedback

voltage then falls and the process repeats. Burst Mode

alternately enables and disables switching of the

SenseFET, reducing switching loss in Standby Mode.

Figure 22. Burst-Mode Operation

FSL126MRT • Rev. 1.0.0

www.fairchildsemi.com

11

Physical Dimensions

10.16

9.96

2.74

2.34

(0.70)

(7.00)

3.28

Ø

3.40

3.20

3.08

(5.40)

6.90

6.50

16.07

15.67

20.00

19.00

(13.05)

24.00

23.00

(0.48)

R0.55

3.06

2.46

8.13

7.13

1.40

1.20

0.80

0.70

(7.15)

(1.13)

0.70

0.50

2,4,6

1,3,5

1

6

0.60

0.45

2.19

1.75

1.27

3.81

3.48

2.88

NOTES: UNLESS OTHERWISE SPECIFIED

A) THIS PACKAGE DOES NOT COMPLY

5°

TO ANY CURRENT PACKAGING STANDARD.

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS ARE EXCLUSIVE OF BURRS,

MOLD FLASH, AND TIE BAR EXTRUSIONS.

D) LEADFORM OPTION A

E) DFAWING FILENAME: TO220A06REV4

Figure 24. TO-220F-6L (W-Forming)

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the

warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

FSL126MRT • Rev. 1.0.0

www.fairchildsemi.com

12

FSL126MRT • Rev. 1.0.0

www.fairchildsemi.com

13


型号：	FSL126MRT
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	Green-Mode Fairchild Power Switch (FPSâ¢) 绿色模式飞兆功率开关（ FPSA ?? ¢ ）稳压器开关式稳压器或控制器电源电路开关式控制器
文件：	总13页 (文件大小：873K)
中文：	中文翻译
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FSL126MRT [FAIRCHILD]

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FSL127HNY

FSL128MRTWDTU

FSL13

FSL130D

FSL130D1

FSL130D3

FSL130D4

FSL130R

FSL130R1