FSTU32160 [FAIRCHILD]
16-Bit to 32-Bit Multiplexer/Demultiplexer Bus Switch with -2V Undershoot Protection; 16位至32位多路复用器/多路解复用器总线开关具有-2V下冲保护型号: | FSTU32160 |
厂家: | FAIRCHILD SEMICONDUCTOR |
描述: | 16-Bit to 32-Bit Multiplexer/Demultiplexer Bus Switch with -2V Undershoot Protection |
文件: | 总6页 (文件大小:99K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
May 1999
Revised March 2000
FSTU32160
16-Bit to 32-Bit Multiplexer/Demultiplexer Bus Switch
with −2V Undershoot Protection
General Description
Features
■ Undershoot hardened to −2V (A and B Ports).
■ Slower Output Enable times prevent signal disruption
■ 4Ω switch connection between two ports.
The Fairchild Switch FSTU32160 is a 16-bit to 32-bit high-
speed CMOS TTL-compatible multiplexer/demultiplexer
bus switch. The low on resistance of the switch allows
inputs to be connected to outputs without adding propaga-
tion delay or generating additional ground bounce noise.
■ Minimal propagation delay through the switch.
■ Low lCC
.
The device can be used in applications where two buses
need to be addressed simultaneously. The FSTU32160 is
designed so that the A Port demultiplexes into B1 or B2 or
■ Zero bounce in flow-through mode.
■ Control inputs compatible with TTL level.
■ See Applications Note AN-5008 for details
both. The A and B Ports are “undershoot hardened” with
UHC protection to support an extended range to 2.0V
below ground. Fairchild’s integrated Undershoot Hardened
Circuit, UHC senses undershoot at the I/O’s, and responds
by preventing voltage differentials from developing and
turning on the switch.
Two select (SEL1, SEL2) inputs provide switch enable con-
trol. When SEL1, SEL2 are HIGH, the device precharges
the B Port to a selectable bias voltage (Bias V) to minimize
live insertion noise.
Ordering Code:
Order Number
Package Number
Package Description
FSTU32160MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
UHC is a trademark of Fairchild Semiconductor Corporation.
© 2000 Fairchild Semiconductor Corporation
DS500244
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Connection Diagram
Pin Descriptions
Pin Name
SEL1, SEL2
A
Description
Select Inputs
Bus A
B1, B2
Bus B
Truth Table
Inputs
Function
SEL1
SEL2
L
H
L
H
L
x A = x B1
x A = x B2
L
x A = x B1 and x B2
x B1, x B2 = BiasV
H
H
Logic Diagram
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions (Note 4)
Supply Voltage (VCC
)
−0.5V to +7.0V
−2.0V to +7.0V
−0.5V to +7.0V
DC Switch Voltage (VS) (Note 2)
BiasV Voltage Range
Power Supply Operating (VCC
Precharge Supply (BiasV)
)
4.0V to 5.5V
1.5 to VCC
0V to 5.5V
0V to 5.5V
DC Input Control Pin Voltage
(VIN) (Note 3)
Input Voltage (VIN
)
−0.5V to +7.0V
−50 mA
Output Voltage (VOUT
)
DC Input Diode Current (lIK) VIN < 0V
Input Rise and Fall Time (tr, tf)
Switch Control Input
DC Output Current (IOUT
DC VCC/GND Current (ICC/IGND
Storage Temperature Range (TSTG
)
128 mA
0nS/V to 5nS/V
0nS/V to DC
)
+/− 100 mA
−65°C to +150 °C
Switch I/O
)
Free Air Operating Temperature (TA)
−40 °C to +85 °C
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Note 2: V is the voltage observed/applied at either the A or B Ports across
S
the switch.
Note 3: The input and output negative voltage ratings may be exceeded if
the input and output diode current ratings are observed.
Note 4: Unused control inputs must be held HIGH or LOW. They may not
float.
DC Electrical Characteristics
T
= −40 °C to +85 °C
A
Symbol
Parameter
V
Units
Conditions
Min
Typ
Max
CC
(V)
4.5
(Note 5)
V
V
V
Clamp Diode Voltage
−1.2
V
V
I
= −18mA
IN
IK
IH
IL
HIGH Level Input Voltage
LOW Level Input Voltage
Input Leakage Current
4.0–5.5
4.0–5.5
5.5
2.0
0.8
±1.0
10
V
I
I
I
I
µA
µA
mA
0 ≤ V ≤ 5.5V
IN
I
0
V
= 5.5V
IN
Output Current
4.5
0.25
BiasV = 2.4V, SEL = 2.0V
X
O
B
= 0
X
, I
OFF-STATE Leakage Current
OFF-STATE Leakage Current
5.5
5.5
±1.0
±1.0
µA
µA
0 ≤ A, ≤ V , V
CC
OZH OZL
BiasV = BiasV = 5.5V
1
2
, I
0 ≤ B, ≤ V , V
CC
OZH OZL
BiasV = BiasV = FLOATING
1
2
R
Switch On Resistance
(Note 6)
4.5
4.5
4.5
4.0
5.5
5.5
4
4
7
7
Ω
Ω
V
V
V
V
V
= 0V, I = 64 mA
IN
ON
IN
IN
IN
IN
IN
= 0V, I = 30 mA
IN
8
14
20
3
Ω
= 2.4V, I = 15 mA
IN
11
Ω
= 2.4V, I = 15 mA
IN
I
Quiescent Supply Current
µA
mA
= V or GND, I
= 0
OUT
CC
CC
∆ I
Increase in I per Input
2.5
One input at 3.4V
Other inputs at V or GND
CC
CC
CC
I
Bias Pin Leakage Current
Voltage Undershoot
5.5
5.5
±1.0
−2.0
µA
SEL , SEL = 0V
1 2
BIAS
B
= 0V, BiasV = 5.5V
X
X
V
V
0.0 mA ≥ I ≥ −50 mA
IN
IKU
SEL , SEL = 5.5V
1
2
Note 5: Typical values are at V = 5.0V and T = +25°C
CC
A
Note 6: Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance is determined by the lower of the
voltages on the two (A or B) pins.
3
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AC Electrical Characteristics
T
= −40 °C to +85 °C,
A
C
= 50 pF, RU= RD = 500Ω
L
Symbol
Parameter
Units
Conditions
Figure No.
V
= 4.5 − 5.5V
V
= 4.0V
CC
CC
Min
Max
Min
Max
t
t
, t
A or B, to B or A (Note 7)
0.25
0.25
ns
V = OPEN
Figure 2
Figure 3
PHL PLH
I
Output Enable Time,
SEL to A, B
V = OPEN for t
Figure 2
Figure 3
PZH
PZL
PHZ
PLZ
I
PZH
PHZ
7.0
7.0
1.0
1.0
30.0
30.0
6.9
35.0
35.0
7.3
ns
ns
ns
ns
BiasV = GND
t
t
t
Output Enable Time,
SEL to A, B
V = 7V for t
Figure 2
Figure 3
I
PZL
BiasV = 3V
Output Disable Time,
SEL to A, B
V = OPEN for t
Figure 2
Figure 3
I
BiasV = GND
Output Disable Time,
SEL to A, B
V = 7V for t
,
Figure 2
Figure 3
I
PLZ
7.7
7.7
BiasV = 3V
Note 7: This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On
resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage source (zero output impedance).
Capacitance (Note 8)
Symbol
Parameter
Typ
Max
Units
Conditions
= 5.0V
C
Control pin Input Capacitance
4
pF
V
IN
CC
C
Input/Output Capacitance “OFF State”
8
pF
V
= 5.0V, Switch OFF
I/O OFF
CC
Note 8: T = +25°C, f = 1 MHz, Capacitance is characterized but not tested.
A
Undershoot Characteristic (Note 9)
Symbol
Parameter
Min
Typ
− 0.3
OH
Max
Units
Conditions
V
Output Voltage During Undershoot
2.5
V
V
Figure 1
OUTU
Note 9: This test is intended to characterize the device’s protective capabilities by maintaining output signal integrity during an input transient voltage
undershoot event.
FIGURE 1.
Device Test Conditions
Transient
Input Voltage (V ) Waveform
IN
Parameter
Value
see Waveform
100K
Units
V
V
Ω
V
V
IN
R
= R
1
2
V
11.0
TRI
V
5.5
CC
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4
AC Loading and Waveforms
Note: Input driven by 50Ω source terminated in 50Ω
Note: C includes load and stray capacitance, C = 50 pF
L
L
Note: Input PRR = 1.0 MHz, t = 500 ns
W
FIGURE 2. AC Test Circuit
FIGURE 3. AC Waveforms
5
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Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD56
Technology Description
The Fairchild Switch family derives from and embodies Fairchild’s proven switch technology used for several years in its
74LVX3L384 (FST3384) bus switch product.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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6
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